include/configs/P1022DS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   4  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   5  *          Timur Tabi <timur@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include "../board/freescale/common/ics307_clk.h"
  12
  13 #ifdef CONFIG_SDCARD
  14 #define CONFIG_SPL_FLUSH_IMAGE
  15 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  16 #define CONFIG_SPL_PAD_TO               0x20000
  17 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  18 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  19 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  20 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  21 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
  22 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  23 #ifdef CONFIG_SPL_BUILD
  24 #define CONFIG_SPL_COMMON_INIT_DDR
  25 #endif
  26 #endif
  27
  28 #ifdef CONFIG_SPIFLASH
  29 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  30 #define CONFIG_SPL_FLUSH_IMAGE
  31 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  32 #define CONFIG_SPL_PAD_TO               0x20000
  33 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
  38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SPL_COMMON_INIT_DDR
  41 #endif
  42 #endif
  43
  44 #define CONFIG_NAND_FSL_ELBC
  45 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  46 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
  47
  48 #ifdef CONFIG_MTD_RAW_NAND
  49 #ifdef CONFIG_TPL_BUILD
  50 #define CONFIG_SPL_FLUSH_IMAGE
  51 #define CONFIG_SPL_NAND_INIT
  52 #define CONFIG_SPL_COMMON_INIT_DDR
  53 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  54 #define CONFIG_TPL_TEXT_BASE            0xf8f81000
  55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  56 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  57 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  58 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  59 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  60 #elif defined(CONFIG_SPL_BUILD)
  61 #define CONFIG_SPL_INIT_MINIMAL
  62 #define CONFIG_SPL_FLUSH_IMAGE
  63 #define CONFIG_SPL_MAX_SIZE             4096
  64 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  65 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
  66 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
  67 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  68 #endif
  69 #define CONFIG_SPL_PAD_TO               0x20000
  70 #define CONFIG_TPL_PAD_TO               0x20000
  71 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  72 #endif
  73
  74 /* High Level Configuration Options */
  75
  76 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  77 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  78 #endif
  79
  80 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  81 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
  82 #define CONFIG_PCIE3                    /* PCIE controller 3 (ULI bridge) */
  83 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  84 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  85
  86 #define CONFIG_ENABLE_36BIT_PHYS
  87
  88 #ifdef CONFIG_PHYS_64BIT
  89 #define CONFIG_ADDR_MAP
  90 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  91 #endif
  92
  93 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  94 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  95 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  96
  97 /*
  98  * These can be toggled for performance analysis, otherwise use default.
  99  */
 100 #define CONFIG_L2_CACHE
 101 #define CONFIG_BTB
 102
 103 #define CONFIG_SYS_CCSRBAR              0xffe00000
 104 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 105
 106 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 107        SPL code*/
 108 #ifdef CONFIG_SPL_BUILD
 109 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 110 #endif
 111
 112 /* DDR Setup */
 113 #define CONFIG_DDR_SPD
 114 #define CONFIG_VERY_BIG_RAM
 115
 116 #ifdef CONFIG_DDR_ECC
 117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 118 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 119 #endif
 120
 121 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 122 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 123
 124 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 125 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 126
 127 /* I2C addresses of SPD EEPROMs */
 128 #define CONFIG_SYS_SPD_BUS_NUM          1
 129 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
 130
 131 /* These are used when DDR doesn't use SPD.  */
 132 #define CONFIG_SYS_SDRAM_SIZE           2048
 133 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 134 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 135 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 136 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 137 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
 138 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
 139 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 140 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
 141 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
 142 #define CONFIG_SYS_DDR_MODE_1           0x00441221
 143 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 144 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
 145 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 146 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
 147 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
 148 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
 149 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 150 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 151 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 152 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
 153
 154 /*
 155  * Memory map
 156  *
 157  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 158  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
 159  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
 160  *
 161  * Localbus cacheable (TBD)
 162  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 163  *
 164  * Localbus non-cacheable
 165  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 166  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 167  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
 168  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 169  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 170  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 171  */
 172
 173 /*
 174  * Local Bus Definitions
 175  */
 176 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
 177 #ifdef CONFIG_PHYS_64BIT
 178 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 179 #else
 180 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 181 #endif
 182
 183 #define CONFIG_FLASH_BR_PRELIM  \
 184         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 185 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 186
 187 #ifdef CONFIG_MTD_RAW_NAND
 188 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 189 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 190 #else
 191 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 192 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 193 #endif
 194
 195 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 196 #define CONFIG_SYS_FLASH_QUIET_TEST
 197 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 198
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 200 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 201
 202 #ifndef CONFIG_SYS_MONITOR_BASE
 203 #ifdef CONFIG_TPL_BUILD
 204 #define CONFIG_SYS_MONITOR_BASE         CONFIG_TPL_TEXT_BASE
 205 #elif defined(CONFIG_SPL_BUILD)
 206 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 207 #else
 208 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 209 #endif
 210 #endif
 211
 212 #define CONFIG_SYS_FLASH_EMPTY_INFO
 213
 214 /* Nand Flash */
 215 #if defined(CONFIG_NAND_FSL_ELBC)
 216 #define CONFIG_SYS_NAND_BASE            0xff800000
 217 #ifdef CONFIG_PHYS_64BIT
 218 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 219 #else
 220 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 221 #endif
 222
 223 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 224 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 225 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 226 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 227
 228 /* NAND flash config */
 229 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 230                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 231                                | BR_PS_8               /* Port Size = 8 bit */ \
 232                                | BR_MS_FCM             /* MSEL = FCM */ \
 233                                | BR_V)                 /* valid */
 234 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
 235                                | OR_FCM_PGS            /* Large Page*/ \
 236                                | OR_FCM_CSCT \
 237                                | OR_FCM_CST \
 238                                | OR_FCM_CHT \
 239                                | OR_FCM_SCY_1 \
 240                                | OR_FCM_TRLX \
 241                                | OR_FCM_EHTR)
 242 #ifdef CONFIG_MTD_RAW_NAND
 243 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 244 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 245 #else
 246 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 247 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 248 #endif
 249
 250 #endif /* CONFIG_NAND_FSL_ELBC */
 251
 252 #define CONFIG_HWCONFIG
 253
 254 #define CONFIG_FSL_NGPIXIS
 255 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 256 #ifdef CONFIG_PHYS_64BIT
 257 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 258 #else
 259 #define PIXIS_BASE_PHYS         PIXIS_BASE
 260 #endif
 261
 262 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 263 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 264
 265 #define PIXIS_LBMAP_SWITCH      7
 266 #define PIXIS_LBMAP_MASK        0xF0
 267 #define PIXIS_LBMAP_ALTBANK     0x20
 268 #define PIXIS_SPD               0x07
 269 #define PIXIS_SPD_SYSCLK_MASK   0x07
 270 #define PIXIS_ELBC_SPI_MASK     0xc0
 271 #define PIXIS_SPI               0x80
 272
 273 #define CONFIG_SYS_INIT_RAM_LOCK
 274 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 275 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
 276
 277 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 278         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 279 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 280
 281 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 282 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 283
 284 /*
 285  * Config the L2 Cache as L2 SRAM
 286 */
 287 #if defined(CONFIG_SPL_BUILD)
 288 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 289 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
 290 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 291 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 292 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 293 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 294 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 295 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 296 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 297 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 298 #elif defined(CONFIG_MTD_RAW_NAND)
 299 #ifdef CONFIG_TPL_BUILD
 300 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 301 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 302 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 303 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 304 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 305 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 306 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 307 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 308 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 309 #else
 310 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 311 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 312 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 313 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 314 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 315 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 316 #endif
 317 #endif
 318 #endif
 319
 320 /*
 321  * Serial Port
 322  */
 323 #define CONFIG_SYS_NS16550_SERIAL
 324 #define CONFIG_SYS_NS16550_REG_SIZE     1
 325 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 326 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 327 #define CONFIG_NS16550_MIN_FUNCTIONS
 328 #endif
 329
 330 #define CONFIG_SYS_BAUDRATE_TABLE       \
 331         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 332
 333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 335
 336 /* Video */
 337
 338 #ifdef CONFIG_FSL_DIU_FB
 339 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 340 #define CONFIG_VIDEO_LOGO
 341 #define CONFIG_VIDEO_BMP_LOGO
 342 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 343 /*
 344  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 345  * disable empty flash sector detection, which is I/O-intensive.
 346  */
 347 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 348 #endif
 349
 350 #ifdef CONFIG_ATI
 351 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 352 #define CONFIG_BIOSEMU
 353 #define CONFIG_ATI_RADEON_FB
 354 #define CONFIG_VIDEO_LOGO
 355 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 356 #endif
 357
 358 /* I2C */
 359 #ifndef CONFIG_DM_I2C
 360 #define CONFIG_SYS_I2C
 361 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 362 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 363 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 364 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 365 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 366 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 367 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 368 #endif
 369 #define CONFIG_SYS_I2C_FSL
 370
 371 /*
 372  * I2C2 EEPROM
 373  */
 374 #define CONFIG_ID_EEPROM
 375 #define CONFIG_SYS_I2C_EEPROM_NXID
 376 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 377 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 378 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 379
 380 /*
 381  * General PCI
 382  * Memory space is mapped 1-1, but I/O space must start from 0.
 383  */
 384
 385 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 386 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 387 #ifdef CONFIG_PHYS_64BIT
 388 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 389 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 390 #else
 391 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 392 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 393 #endif
 394 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 395 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 396 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 397 #ifdef CONFIG_PHYS_64BIT
 398 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 399 #else
 400 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 401 #endif
 402 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 403
 404 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 405 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 406 #ifdef CONFIG_PHYS_64BIT
 407 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 408 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 409 #else
 410 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 411 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 412 #endif
 413 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 414 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 415 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 416 #ifdef CONFIG_PHYS_64BIT
 417 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 418 #else
 419 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 420 #endif
 421 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 422
 423 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 424 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 425 #ifdef CONFIG_PHYS_64BIT
 426 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 427 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 428 #else
 429 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 430 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 431 #endif
 432 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 433 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 434 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 435 #ifdef CONFIG_PHYS_64BIT
 436 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 437 #else
 438 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 439 #endif
 440 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 441
 442 #ifdef CONFIG_PCI
 443 #define CONFIG_PCI_INDIRECT_BRIDGE
 444 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 445 #endif
 446
 447 /* SATA */
 448 #define CONFIG_FSL_SATA_V2
 449
 450 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 451 #define CONFIG_SATA1
 452 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 453 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 454 #define CONFIG_SATA2
 455 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 456 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 457
 458 #ifdef CONFIG_FSL_SATA
 459 #define CONFIG_LBA48
 460 #endif
 461
 462 #ifdef CONFIG_MMC
 463 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 464 #endif
 465
 466 #ifdef CONFIG_TSEC_ENET
 467
 468 #define CONFIG_TSECV2
 469
 470 #define CONFIG_TSEC1            1
 471 #define CONFIG_TSEC1_NAME       "eTSEC1"
 472 #define CONFIG_TSEC2            1
 473 #define CONFIG_TSEC2_NAME       "eTSEC2"
 474
 475 #define TSEC1_PHY_ADDR          1
 476 #define TSEC2_PHY_ADDR          2
 477
 478 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 479 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 480
 481 #define TSEC1_PHYIDX            0
 482 #define TSEC2_PHYIDX            0
 483
 484 #define CONFIG_ETHPRIME         "eTSEC1"
 485 #endif
 486
 487 /*
 488  * Dynamic MTD Partition support with mtdparts
 489  */
 490
 491 /*
 492  * Environment
 493  */
 494 #if defined(CONFIG_SDCARD)
 495 #define CONFIG_FSL_FIXED_MMC_LOCATION
 496 #define CONFIG_SYS_MMC_ENV_DEV  0
 497 #elif defined(CONFIG_MTD_RAW_NAND)
 498 #ifdef CONFIG_TPL_BUILD
 499 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 500 #endif
 501 #elif defined(CONFIG_SYS_RAMBOOT)
 502 #define SPL_ENV_ADDR            (CONFIG_SYS_MONITOR_BASE - 0x1000)
 503 #endif
 504
 505 #define CONFIG_LOADS_ECHO
 506 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 507
 508 /*
 509  * USB
 510  */
 511 #define CONFIG_HAS_FSL_DR_USB
 512 #ifdef CONFIG_HAS_FSL_DR_USB
 513 #ifdef CONFIG_USB_EHCI_HCD
 514 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 515 #define CONFIG_USB_EHCI_FSL
 516 #endif
 517 #endif
 518
 519 /*
 520  * Miscellaneous configurable options
 521  */
 522 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 523
 524 /*
 525  * For booting Linux, the board info and command line data
 526  * have to be in the first 64 MB of memory, since this is
 527  * the maximum mapped by the Linux kernel during initialization.
 528  */
 529 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 530 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 531
 532 #ifdef CONFIG_CMD_KGDB
 533 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 534 #endif
 535
 536 /*
 537  * Environment Configuration
 538  */
 539
 540 #define CONFIG_HOSTNAME         "p1022ds"
 541 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 542 #define CONFIG_BOOTFILE         "uImage"
 543 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 544
 545 #define CONFIG_LOADADDR         1000000
 546
 547 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 548         "netdev=eth0\0"                                         \
 549         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 550         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 551         "tftpflash=tftpboot $loadaddr $uboot && "               \
 552                 "protect off $ubootaddr +$filesize && "         \
 553                 "erase $ubootaddr +$filesize && "               \
 554                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 555                 "protect on $ubootaddr +$filesize && "          \
 556                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 557         "consoledev=ttyS0\0"                                    \
 558         "ramdiskaddr=2000000\0"                                 \
 559         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 560         "fdtaddr=1e00000\0"                                     \
 561         "fdtfile=p1022ds.dtb\0"                                 \
 562         "bdev=sda3\0"                                           \
 563         "hwconfig=esdhc;audclk:12\0"
 564
 565 #define CONFIG_HDBOOT                                   \
 566         "setenv bootargs root=/dev/$bdev rw "           \
 567         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 568         "tftp $loadaddr $bootfile;"                     \
 569         "tftp $fdtaddr $fdtfile;"                       \
 570         "bootm $loadaddr - $fdtaddr"
 571
 572 #define CONFIG_NFSBOOTCOMMAND                                           \
 573         "setenv bootargs root=/dev/nfs rw "                             \
 574         "nfsroot=$serverip:$rootpath "                                  \
 575         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 576         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 577         "tftp $loadaddr $bootfile;"                                     \
 578         "tftp $fdtaddr $fdtfile;"                                       \
 579         "bootm $loadaddr - $fdtaddr"
 580
 581 #define CONFIG_RAMBOOTCOMMAND                                           \
 582         "setenv bootargs root=/dev/ram rw "                             \
 583         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 584         "tftp $ramdiskaddr $ramdiskfile;"                               \
 585         "tftp $loadaddr $bootfile;"                                     \
 586         "tftp $fdtaddr $fdtfile;"                                       \
 587         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 588
 589 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 590
 591 #endif