include/configs/P1022DS.h

   1 /*
   2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #ifdef CONFIG_SDCARD
  17 #define CONFIG_SPL_SERIAL_SUPPORT
  18 #define CONFIG_SPL_MMC_MINIMAL
  19 #define CONFIG_SPL_FLUSH_IMAGE
  20 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  21 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  22 #define CONFIG_SYS_TEXT_BASE            0x11001000
  23 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  24 #define CONFIG_SPL_PAD_TO               0x20000
  25 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  26 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  27 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  28 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  29 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
  30 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  31 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  32 #define CONFIG_SPL_MMC_BOOT
  33 #ifdef CONFIG_SPL_BUILD
  34 #define CONFIG_SPL_COMMON_INIT_DDR
  35 #endif
  36 #endif
  37
  38 #ifdef CONFIG_SPIFLASH
  39 #define CONFIG_SPL_SERIAL_SUPPORT
  40 #define CONFIG_SPL_SPI_SUPPORT
  41 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  42 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  43 #define CONFIG_SPL_FLUSH_IMAGE
  44 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  45 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  46 #define CONFIG_SYS_TEXT_BASE            0x11001000
  47 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  48 #define CONFIG_SPL_PAD_TO               0x20000
  49 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
  54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  55 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  56 #define CONFIG_SPL_SPI_BOOT
  57 #ifdef CONFIG_SPL_BUILD
  58 #define CONFIG_SPL_COMMON_INIT_DDR
  59 #endif
  60 #endif
  61
  62 #define CONFIG_NAND_FSL_ELBC
  63 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  64 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
  65
  66 #ifdef CONFIG_NAND
  67 #ifdef CONFIG_TPL_BUILD
  68 #define CONFIG_SPL_NAND_BOOT
  69 #define CONFIG_SPL_FLUSH_IMAGE
  70 #define CONFIG_SPL_NAND_INIT
  71 #define CONFIG_TPL_SERIAL_SUPPORT
  72 #define CONFIG_SPL_COMMON_INIT_DDR
  73 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  74 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  75 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  76 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  77 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  78 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  79 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  80 #elif defined(CONFIG_SPL_BUILD)
  81 #define CONFIG_SPL_INIT_MINIMAL
  82 #define CONFIG_SPL_SERIAL_SUPPORT
  83 #define CONFIG_SPL_FLUSH_IMAGE
  84 #define CONFIG_SPL_TEXT_BASE            0xff800000
  85 #define CONFIG_SPL_MAX_SIZE             4096
  86 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  87 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
  88 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
  89 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  90 #endif
  91 #define CONFIG_SPL_PAD_TO               0x20000
  92 #define CONFIG_TPL_PAD_TO               0x20000
  93 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  94 #define CONFIG_SYS_TEXT_BASE            0x11001000
  95 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  96 #endif
  97
  98 /* High Level Configuration Options */
  99 #define CONFIG_BOOKE                    /* BOOKE */
 100 #define CONFIG_E500                     /* BOOKE e500 family */
 101 #define CONFIG_P1022
 102 #define CONFIG_P1022DS
 103 #define CONFIG_MP                       /* support multiple processors */
 104
 105 #ifndef CONFIG_SYS_TEXT_BASE
 106 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 107 #endif
 108
 109 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 110 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 111 #endif
 112
 113 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
 114 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 115 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 116 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 117 #define CONFIG_PCIE3                    /* PCIE controller 3 (ULI bridge) */
 118 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 119 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 120 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 121
 122 #define CONFIG_ENABLE_36BIT_PHYS
 123
 124 #ifdef CONFIG_PHYS_64BIT
 125 #define CONFIG_ADDR_MAP
 126 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 127 #endif
 128
 129 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 130
 131 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 132 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 133 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
 134
 135 /*
 136  * These can be toggled for performance analysis, otherwise use default.
 137  */
 138 #define CONFIG_L2_CACHE
 139 #define CONFIG_BTB
 140
 141 #define CONFIG_SYS_MEMTEST_START        0x00000000
 142 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
 143
 144 #define CONFIG_SYS_CCSRBAR              0xffe00000
 145 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 146
 147 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 148        SPL code*/
 149 #ifdef CONFIG_SPL_BUILD
 150 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 151 #endif
 152
 153 /* DDR Setup */
 154 #define CONFIG_DDR_SPD
 155 #define CONFIG_VERY_BIG_RAM
 156 #define CONFIG_SYS_FSL_DDR3
 157
 158 #ifdef CONFIG_DDR_ECC
 159 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 160 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 161 #endif
 162
 163 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 164 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 165
 166 #define CONFIG_NUM_DDR_CONTROLLERS      1
 167 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 168 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 169
 170 /* I2C addresses of SPD EEPROMs */
 171 #define CONFIG_SYS_SPD_BUS_NUM          1
 172 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
 173
 174 /* These are used when DDR doesn't use SPD.  */
 175 #define CONFIG_SYS_SDRAM_SIZE           2048
 176 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 177 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 178 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 179 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 180 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
 181 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
 182 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 183 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
 184 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
 185 #define CONFIG_SYS_DDR_MODE_1           0x00441221
 186 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 187 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
 188 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 189 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
 190 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
 191 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
 192 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 193 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 194 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 195 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
 196
 197 /*
 198  * Memory map
 199  *
 200  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 201  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
 202  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
 203  *
 204  * Localbus cacheable (TBD)
 205  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 206  *
 207  * Localbus non-cacheable
 208  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 209  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 210  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
 211  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 212  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 213  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 214  */
 215
 216 /*
 217  * Local Bus Definitions
 218  */
 219 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
 220 #ifdef CONFIG_PHYS_64BIT
 221 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 222 #else
 223 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 224 #endif
 225
 226 #define CONFIG_FLASH_BR_PRELIM  \
 227         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 228 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 229
 230 #ifdef CONFIG_NAND
 231 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 232 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 233 #else
 234 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 235 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 236 #endif
 237
 238 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 239 #define CONFIG_SYS_FLASH_QUIET_TEST
 240 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 241
 242 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 243 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 244
 245 #ifndef CONFIG_SYS_MONITOR_BASE
 246 #ifdef CONFIG_SPL_BUILD
 247 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 248 #else
 249 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 250 #endif
 251 #endif
 252
 253 #define CONFIG_FLASH_CFI_DRIVER
 254 #define CONFIG_SYS_FLASH_CFI
 255 #define CONFIG_SYS_FLASH_EMPTY_INFO
 256
 257 /* Nand Flash */
 258 #if defined(CONFIG_NAND_FSL_ELBC)
 259 #define CONFIG_SYS_NAND_BASE            0xff800000
 260 #ifdef CONFIG_PHYS_64BIT
 261 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 262 #else
 263 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 264 #endif
 265
 266 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 267 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 268 #define CONFIG_CMD_NAND                 1
 269 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 270 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 271
 272 /* NAND flash config */
 273 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 274                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 275                                | BR_PS_8               /* Port Size = 8 bit */ \
 276                                | BR_MS_FCM             /* MSEL = FCM */ \
 277                                | BR_V)                 /* valid */
 278 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
 279                                | OR_FCM_PGS            /* Large Page*/ \
 280                                | OR_FCM_CSCT \
 281                                | OR_FCM_CST \
 282                                | OR_FCM_CHT \
 283                                | OR_FCM_SCY_1 \
 284                                | OR_FCM_TRLX \
 285                                | OR_FCM_EHTR)
 286 #ifdef CONFIG_NAND
 287 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 288 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 289 #else
 290 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 291 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 292 #endif
 293
 294 #endif /* CONFIG_NAND_FSL_ELBC */
 295
 296 #define CONFIG_BOARD_EARLY_INIT_F
 297 #define CONFIG_BOARD_EARLY_INIT_R
 298 #define CONFIG_MISC_INIT_R
 299 #define CONFIG_HWCONFIG
 300
 301 #define CONFIG_FSL_NGPIXIS
 302 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 303 #ifdef CONFIG_PHYS_64BIT
 304 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 305 #else
 306 #define PIXIS_BASE_PHYS         PIXIS_BASE
 307 #endif
 308
 309 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 310 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 311
 312 #define PIXIS_LBMAP_SWITCH      7
 313 #define PIXIS_LBMAP_MASK        0xF0
 314 #define PIXIS_LBMAP_ALTBANK     0x20
 315 #define PIXIS_SPD               0x07
 316 #define PIXIS_SPD_SYSCLK_MASK   0x07
 317 #define PIXIS_ELBC_SPI_MASK     0xc0
 318 #define PIXIS_SPI               0x80
 319
 320 #define CONFIG_SYS_INIT_RAM_LOCK
 321 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 322 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
 323
 324 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 325         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 326 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 327
 328 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 329 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 330
 331 /*
 332  * Config the L2 Cache as L2 SRAM
 333 */
 334 #if defined(CONFIG_SPL_BUILD)
 335 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 336 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
 337 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 338 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 339 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 340 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 341 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 342 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 343 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 344 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 345 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 346 #elif defined(CONFIG_NAND)
 347 #ifdef CONFIG_TPL_BUILD
 348 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 349 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 350 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 351 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 352 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 353 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 354 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 355 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 356 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 357 #else
 358 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 359 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 360 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 361 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 362 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 363 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 364 #endif
 365 #endif
 366 #endif
 367
 368 /*
 369  * Serial Port
 370  */
 371 #define CONFIG_CONS_INDEX               1
 372 #define CONFIG_SYS_NS16550_SERIAL
 373 #define CONFIG_SYS_NS16550_REG_SIZE     1
 374 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 375 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 376 #define CONFIG_NS16550_MIN_FUNCTIONS
 377 #endif
 378
 379 #define CONFIG_SYS_BAUDRATE_TABLE       \
 380         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 381
 382 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 383 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 384
 385 /* Video */
 386
 387 #ifdef CONFIG_FSL_DIU_FB
 388 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 389 #define CONFIG_VIDEO
 390 #define CONFIG_CMD_BMP
 391 #define CONFIG_CFB_CONSOLE
 392 #define CONFIG_VIDEO_SW_CURSOR
 393 #define CONFIG_VGA_AS_SINGLE_DEVICE
 394 #define CONFIG_VIDEO_LOGO
 395 #define CONFIG_VIDEO_BMP_LOGO
 396 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 397 /*
 398  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 399  * disable empty flash sector detection, which is I/O-intensive.
 400  */
 401 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 402 #endif
 403
 404 #ifndef CONFIG_FSL_DIU_FB
 405 #endif
 406
 407 #ifdef CONFIG_ATI
 408 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 409 #define CONFIG_VIDEO
 410 #define CONFIG_BIOSEMU
 411 #define CONFIG_VIDEO_SW_CURSOR
 412 #define CONFIG_ATI_RADEON_FB
 413 #define CONFIG_VIDEO_LOGO
 414 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 415 #define CONFIG_CFB_CONSOLE
 416 #define CONFIG_VGA_AS_SINGLE_DEVICE
 417 #endif
 418
 419 /* I2C */
 420 #define CONFIG_SYS_I2C
 421 #define CONFIG_SYS_I2C_FSL
 422 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 423 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 424 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 425 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 426 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 427 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 428 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 429
 430 /*
 431  * I2C2 EEPROM
 432  */
 433 #define CONFIG_ID_EEPROM
 434 #define CONFIG_SYS_I2C_EEPROM_NXID
 435 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 436 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 437 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 438
 439 /*
 440  * eSPI - Enhanced SPI
 441  */
 442
 443 #define CONFIG_HARD_SPI
 444
 445 #define CONFIG_SF_DEFAULT_SPEED         10000000
 446 #define CONFIG_SF_DEFAULT_MODE          0
 447
 448 /*
 449  * General PCI
 450  * Memory space is mapped 1-1, but I/O space must start from 0.
 451  */
 452
 453 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 454 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 455 #ifdef CONFIG_PHYS_64BIT
 456 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 457 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 458 #else
 459 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 460 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 461 #endif
 462 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 463 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 464 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 465 #ifdef CONFIG_PHYS_64BIT
 466 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 467 #else
 468 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 469 #endif
 470 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 471
 472 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 473 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 474 #ifdef CONFIG_PHYS_64BIT
 475 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 476 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 477 #else
 478 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 479 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 480 #endif
 481 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 482 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 483 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 484 #ifdef CONFIG_PHYS_64BIT
 485 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 486 #else
 487 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 488 #endif
 489 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 490
 491 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 492 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 493 #ifdef CONFIG_PHYS_64BIT
 494 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 495 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 496 #else
 497 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 498 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 499 #endif
 500 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 501 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 502 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 503 #ifdef CONFIG_PHYS_64BIT
 504 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 505 #else
 506 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 507 #endif
 508 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 509
 510 #ifdef CONFIG_PCI
 511 #define CONFIG_PCI_INDIRECT_BRIDGE
 512 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 513 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 514 #endif
 515
 516 /* SATA */
 517 #define CONFIG_LIBATA
 518 #define CONFIG_FSL_SATA
 519 #define CONFIG_FSL_SATA_V2
 520
 521 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 522 #define CONFIG_SATA1
 523 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 524 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 525 #define CONFIG_SATA2
 526 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 527 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 528
 529 #ifdef CONFIG_FSL_SATA
 530 #define CONFIG_LBA48
 531 #define CONFIG_CMD_SATA
 532 #define CONFIG_DOS_PARTITION
 533 #endif
 534
 535 #define CONFIG_MMC
 536 #ifdef CONFIG_MMC
 537 #define CONFIG_FSL_ESDHC
 538 #define CONFIG_GENERIC_MMC
 539 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 540 #endif
 541
 542 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 543 #define CONFIG_DOS_PARTITION
 544 #endif
 545
 546 #define CONFIG_TSEC_ENET
 547 #ifdef CONFIG_TSEC_ENET
 548
 549 #define CONFIG_TSECV2
 550
 551 #define CONFIG_MII                      /* MII PHY management */
 552 #define CONFIG_TSEC1            1
 553 #define CONFIG_TSEC1_NAME       "eTSEC1"
 554 #define CONFIG_TSEC2            1
 555 #define CONFIG_TSEC2_NAME       "eTSEC2"
 556
 557 #define TSEC1_PHY_ADDR          1
 558 #define TSEC2_PHY_ADDR          2
 559
 560 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 561 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 562
 563 #define TSEC1_PHYIDX            0
 564 #define TSEC2_PHYIDX            0
 565
 566 #define CONFIG_ETHPRIME         "eTSEC1"
 567
 568 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 569 #endif
 570
 571 /*
 572  * Dynamic MTD Partition support with mtdparts
 573  */
 574 #define CONFIG_MTD_DEVICE
 575 #define CONFIG_MTD_PARTITIONS
 576 #define CONFIG_CMD_MTDPARTS
 577 #define CONFIG_FLASH_CFI_MTD
 578 #ifdef CONFIG_PHYS_64BIT
 579 #define MTDIDS_DEFAULT "nor0=fe8000000.nor"
 580 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
 581                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
 582                         "512k(dtb),768k(u-boot)"
 583 #else
 584 #define MTDIDS_DEFAULT "nor0=e8000000.nor"
 585 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
 586                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
 587                         "512k(dtb),768k(u-boot)"
 588 #endif
 589
 590 /*
 591  * Environment
 592  */
 593 #ifdef CONFIG_SPIFLASH
 594 #define CONFIG_ENV_IS_IN_SPI_FLASH
 595 #define CONFIG_ENV_SPI_BUS      0
 596 #define CONFIG_ENV_SPI_CS       0
 597 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 598 #define CONFIG_ENV_SPI_MODE     0
 599 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 600 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 601 #define CONFIG_ENV_SECT_SIZE    0x10000
 602 #elif defined(CONFIG_SDCARD)
 603 #define CONFIG_ENV_IS_IN_MMC
 604 #define CONFIG_FSL_FIXED_MMC_LOCATION
 605 #define CONFIG_ENV_SIZE         0x2000
 606 #define CONFIG_SYS_MMC_ENV_DEV  0
 607 #elif defined(CONFIG_NAND)
 608 #ifdef CONFIG_TPL_BUILD
 609 #define CONFIG_ENV_SIZE         0x2000
 610 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 611 #else
 612 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 613 #endif
 614 #define CONFIG_ENV_IS_IN_NAND
 615 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 616 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 617 #elif defined(CONFIG_SYS_RAMBOOT)
 618 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 619 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 620 #define CONFIG_ENV_SIZE         0x2000
 621 #else
 622 #define CONFIG_ENV_IS_IN_FLASH
 623 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 624 #define CONFIG_ENV_SIZE         0x2000
 625 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 626 #endif
 627
 628 #define CONFIG_LOADS_ECHO
 629 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 630
 631 /*
 632  * Command line configuration.
 633  */
 634 #define CONFIG_CMD_ERRATA
 635 #define CONFIG_CMD_IRQ
 636 #define CONFIG_CMD_REGINFO
 637
 638 #ifdef CONFIG_PCI
 639 #define CONFIG_CMD_PCI
 640 #endif
 641
 642 /*
 643  * USB
 644  */
 645 #define CONFIG_HAS_FSL_DR_USB
 646 #ifdef CONFIG_HAS_FSL_DR_USB
 647 #define CONFIG_USB_EHCI
 648
 649 #ifdef CONFIG_USB_EHCI
 650 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 651 #define CONFIG_USB_EHCI_FSL
 652 #endif
 653 #endif
 654
 655 /*
 656  * Miscellaneous configurable options
 657  */
 658 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 659 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 660 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 661 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 662 #ifdef CONFIG_CMD_KGDB
 663 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 664 #else
 665 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 666 #endif
 667 /* Print Buffer Size */
 668 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 669 #define CONFIG_SYS_MAXARGS      16
 670 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 671
 672 /*
 673  * For booting Linux, the board info and command line data
 674  * have to be in the first 64 MB of memory, since this is
 675  * the maximum mapped by the Linux kernel during initialization.
 676  */
 677 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 678 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 679
 680 #ifdef CONFIG_CMD_KGDB
 681 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 682 #endif
 683
 684 /*
 685  * Environment Configuration
 686  */
 687
 688 #define CONFIG_HOSTNAME         p1022ds
 689 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 690 #define CONFIG_BOOTFILE         "uImage"
 691 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 692
 693 #define CONFIG_LOADADDR         1000000
 694
 695
 696 #define CONFIG_BAUDRATE 115200
 697
 698 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 699         "netdev=eth0\0"                                         \
 700         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 701         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 702         "tftpflash=tftpboot $loadaddr $uboot && "               \
 703                 "protect off $ubootaddr +$filesize && "         \
 704                 "erase $ubootaddr +$filesize && "               \
 705                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 706                 "protect on $ubootaddr +$filesize && "          \
 707                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 708         "consoledev=ttyS0\0"                                    \
 709         "ramdiskaddr=2000000\0"                                 \
 710         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 711         "fdtaddr=1e00000\0"                                     \
 712         "fdtfile=p1022ds.dtb\0"                                 \
 713         "bdev=sda3\0"                                           \
 714         "hwconfig=esdhc;audclk:12\0"
 715
 716 #define CONFIG_HDBOOT                                   \
 717         "setenv bootargs root=/dev/$bdev rw "           \
 718         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 719         "tftp $loadaddr $bootfile;"                     \
 720         "tftp $fdtaddr $fdtfile;"                       \
 721         "bootm $loadaddr - $fdtaddr"
 722
 723 #define CONFIG_NFSBOOTCOMMAND                                           \
 724         "setenv bootargs root=/dev/nfs rw "                             \
 725         "nfsroot=$serverip:$rootpath "                                  \
 726         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 727         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 728         "tftp $loadaddr $bootfile;"                                     \
 729         "tftp $fdtaddr $fdtfile;"                                       \
 730         "bootm $loadaddr - $fdtaddr"
 731
 732 #define CONFIG_RAMBOOTCOMMAND                                           \
 733         "setenv bootargs root=/dev/ram rw "                             \
 734         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 735         "tftp $ramdiskaddr $ramdiskfile;"                               \
 736         "tftp $loadaddr $bootfile;"                                     \
 737         "tftp $fdtaddr $fdtfile;"                                       \
 738         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 739
 740 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 741
 742 #endif