include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10)
  20 #define CFG_SYS_MMC_U_BOOT_DST  (0x11000000)
  21 #define CFG_SYS_MMC_U_BOOT_START        (0x11000000)
  22 #define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10)
  23 #endif
  24
  25 #ifdef CONFIG_SPIFLASH
  26 #ifdef CONFIG_NXP_ESBC
  27 #define CONFIG_RAMBOOT_SPIFLASH
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  29 #else
  30 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE   (512 << 10)
  31 #define CFG_SYS_SPI_FLASH_U_BOOT_DST            (0x11000000)
  32 #define CFG_SYS_SPI_FLASH_U_BOOT_START  (0x11000000)
  33 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS   (96 << 10)
  34 #endif
  35 #endif
  36
  37 #ifdef CONFIG_MTD_RAW_NAND
  38 #ifdef CONFIG_NXP_ESBC
  39 #define CFG_SYS_NAND_U_BOOT_SIZE        ((768 << 10) - 0x2000)
  40 #define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
  41 #define CFG_SYS_NAND_U_BOOT_START       0x00200000
  42 #else
  43 #ifdef CONFIG_TPL_BUILD
  44 #define CFG_SYS_NAND_U_BOOT_SIZE        (576 << 10)
  45 #define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
  46 #define CFG_SYS_NAND_U_BOOT_START       (0x11000000)
  47 #elif defined(CONFIG_SPL_BUILD)
  48 #define CFG_SYS_NAND_U_BOOT_SIZE        (128 << 10)
  49 #define CFG_SYS_NAND_U_BOOT_DST 0xD0000000
  50 #define CFG_SYS_NAND_U_BOOT_START       0xD0000000
  51 #endif
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  56 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  57 #endif
  58
  59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  61 #endif
  62
  63 /* High Level Configuration Options */
  64
  65 #if defined(CONFIG_PCI)
  66 /*
  67  * PCI Windows
  68  * Memory space is mapped 1-1, but I/O space must start from 0.
  69  */
  70 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  71 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
  72 #ifdef CONFIG_PHYS_64BIT
  73 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
  74 #else
  75 #define CFG_SYS_PCIE1_MEM_PHYS  0x80000000
  76 #endif
  77 #define CFG_SYS_PCIE1_IO_VIRT   0xffc00000
  78 #ifdef CONFIG_PHYS_64BIT
  79 #define CFG_SYS_PCIE1_IO_PHYS   0xfffc00000ull
  80 #else
  81 #define CFG_SYS_PCIE1_IO_PHYS   0xffc00000
  82 #endif
  83
  84 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  85 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
  86 #ifdef CONFIG_PHYS_64BIT
  87 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
  88 #else
  89 #define CFG_SYS_PCIE2_MEM_PHYS  0xa0000000
  90 #endif
  91 #define CFG_SYS_PCIE2_IO_VIRT   0xffc10000
  92 #ifdef CONFIG_PHYS_64BIT
  93 #define CFG_SYS_PCIE2_IO_PHYS   0xfffc10000ull
  94 #else
  95 #define CFG_SYS_PCIE2_IO_PHYS   0xffc10000
  96 #endif
  97 #endif
  98
  99 /*
 100  * These can be toggled for performance analysis, otherwise use default.
 101  */
 102 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 103
 104 /* DDR Setup */
 105 #define SPD_EEPROM_ADDRESS              0x52
 106
 107 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 108
 109 #ifndef __ASSEMBLY__
 110 extern unsigned long get_sdram_size(void);
 111 #endif
 112 #define CFG_SYS_SDRAM_SIZE              get_sdram_size() /* DDR size */
 113 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
 114 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
 115
 116 #define CFG_SYS_CCSRBAR                 0xffe00000
 117 #define CFG_SYS_CCSRBAR_PHYS_LOW                CFG_SYS_CCSRBAR
 118
 119 /*
 120  * Memory map
 121  *
 122  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 123  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 124  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 125  *
 126  * Localbus non-cacheable
 127  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 128  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 129  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 130  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 131  */
 132
 133 /*
 134  * IFC Definitions
 135  */
 136 /* NOR Flash on IFC */
 137
 138 #define CFG_SYS_FLASH_BASE              0xee000000
 139
 140 #ifdef CONFIG_PHYS_64BIT
 141 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
 142 #else
 143 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
 144 #endif
 145
 146 #define CFG_SYS_NOR_CSPR        (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 147                                 CSPR_PORT_SIZE_16 | \
 148                                 CSPR_MSEL_NOR | \
 149                                 CSPR_V)
 150 #define CFG_SYS_NOR_AMASK       IFC_AMASK(32*1024*1024)
 151 #define CFG_SYS_NOR_CSOR        CSOR_NOR_ADM_SHIFT(7)
 152 /* NOR Flash Timing Params */
 153 #define CFG_SYS_NOR_FTIM0       FTIM0_NOR_TACSE(0x4) | \
 154                                 FTIM0_NOR_TEADC(0x5) | \
 155                                 FTIM0_NOR_TEAHC(0x5)
 156 #define CFG_SYS_NOR_FTIM1       FTIM1_NOR_TACO(0x1e) | \
 157                                 FTIM1_NOR_TRAD_NOR(0x0f)
 158 #define CFG_SYS_NOR_FTIM2       FTIM2_NOR_TCS(0x4) | \
 159                                 FTIM2_NOR_TCH(0x4) | \
 160                                 FTIM2_NOR_TWP(0x1c)
 161 #define CFG_SYS_NOR_FTIM3       0x0
 162
 163 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS}
 164
 165 /* CFI for NOR Flash */
 166
 167 /* NAND Flash on IFC */
 168 #define CFG_SYS_NAND_BASE               0xff800000
 169 #ifdef CONFIG_PHYS_64BIT
 170 #define CFG_SYS_NAND_BASE_PHYS  0xfff800000ull
 171 #else
 172 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
 173 #endif
 174
 175 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 176                                 | CSPR_PORT_SIZE_8      \
 177                                 | CSPR_MSEL_NAND        \
 178                                 | CSPR_V)
 179 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 180
 181 #if defined(CONFIG_TARGET_P1010RDB_PA)
 182 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 183                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 184                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 185                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 186                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 187                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 188                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 189
 190 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 191 #define CFG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 192                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 193                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 194                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 195                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 196                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 197                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 198 #endif
 199
 200 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 201
 202 #if defined(CONFIG_TARGET_P1010RDB_PA)
 203 /* NAND Flash Timing Params */
 204 #define CFG_SYS_NAND_FTIM0              FTIM0_NAND_TCCST(0x01) | \
 205                                         FTIM0_NAND_TWP(0x0C)   | \
 206                                         FTIM0_NAND_TWCHT(0x04) | \
 207                                         FTIM0_NAND_TWH(0x05)
 208 #define CFG_SYS_NAND_FTIM1              FTIM1_NAND_TADLE(0x1d) | \
 209                                         FTIM1_NAND_TWBE(0x1d)  | \
 210                                         FTIM1_NAND_TRR(0x07)   | \
 211                                         FTIM1_NAND_TRP(0x0c)
 212 #define CFG_SYS_NAND_FTIM2              FTIM2_NAND_TRAD(0x0c) | \
 213                                         FTIM2_NAND_TREH(0x05) | \
 214                                         FTIM2_NAND_TWHRE(0x0f)
 215 #define CFG_SYS_NAND_FTIM3              FTIM3_NAND_TWW(0x04)
 216
 217 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 218 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 219 /* ONFI NAND Flash mode0 Timing Params */
 220 #define CFG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 221                                         FTIM0_NAND_TWP(0x18)   | \
 222                                         FTIM0_NAND_TWCHT(0x07) | \
 223                                         FTIM0_NAND_TWH(0x0a))
 224 #define CFG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 225                                         FTIM1_NAND_TWBE(0x39)  | \
 226                                         FTIM1_NAND_TRR(0x0e)   | \
 227                                         FTIM1_NAND_TRP(0x18))
 228 #define CFG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 229                                         FTIM2_NAND_TREH(0x0a)  | \
 230                                         FTIM2_NAND_TWHRE(0x1e))
 231 #define CFG_SYS_NAND_FTIM3      0x0
 232 #endif
 233
 234 /* Set up IFC registers for boot location NOR/NAND */
 235 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 236 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 237 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 238 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 239 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 240 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 241 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 242 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 243 #define CFG_SYS_CSPR1           CFG_SYS_NOR_CSPR
 244 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 245 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 246 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 247 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 248 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 249 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 250 #else
 251 #define CFG_SYS_CSPR0           CFG_SYS_NOR_CSPR
 252 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 253 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 254 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 255 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 256 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 257 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 258 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 259 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 260 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 261 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 262 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 263 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 264 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 265 #endif
 266
 267 /* CPLD on IFC */
 268 #define CFG_SYS_CPLD_BASE               0xffb00000
 269
 270 #ifdef CONFIG_PHYS_64BIT
 271 #define CFG_SYS_CPLD_BASE_PHYS  0xfffb00000ull
 272 #else
 273 #define CFG_SYS_CPLD_BASE_PHYS  CFG_SYS_CPLD_BASE
 274 #endif
 275
 276 #define CFG_SYS_CSPR3   (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 277                                 | CSPR_PORT_SIZE_8 \
 278                                 | CSPR_MSEL_GPCM \
 279                                 | CSPR_V)
 280 #define CFG_SYS_AMASK3          IFC_AMASK(64*1024)
 281 #define CFG_SYS_CSOR3           0x0
 282 /* CPLD Timing parameters for IFC CS3 */
 283 #define CFG_SYS_CS3_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 284                                         FTIM0_GPCM_TEADC(0x0e) | \
 285                                         FTIM0_GPCM_TEAHC(0x0e))
 286 #define CFG_SYS_CS3_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 287                                         FTIM1_GPCM_TRAD(0x1f))
 288 #define CFG_SYS_CS3_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 289                                         FTIM2_GPCM_TCH(0x8) | \
 290                                         FTIM2_GPCM_TWP(0x1f))
 291 #define CFG_SYS_CS3_FTIM3               0x0
 292
 293 #define CFG_SYS_INIT_RAM_ADDR   0xffd00000 /* stack in RAM */
 294 #define CFG_SYS_INIT_RAM_SIZE   0x00004000 /* End of used area in RAM */
 295
 296 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 297
 298 /*
 299  * Config the L2 Cache as L2 SRAM
 300  */
 301 #if defined(CONFIG_SPL_BUILD)
 302 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 303 #define CFG_SYS_INIT_L2_ADDR            0xD0000000
 304 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 305 #define CFG_SYS_INIT_L2_END     (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 306 #elif defined(CONFIG_MTD_RAW_NAND)
 307 #ifdef CONFIG_TPL_BUILD
 308 #define CFG_SYS_INIT_L2_ADDR            0xD0000000
 309 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 310 #define CFG_SYS_INIT_L2_END     (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 311 #else
 312 #define CFG_SYS_INIT_L2_ADDR            0xD0000000
 313 #define CFG_SYS_INIT_L2_ADDR_PHYS       CFG_SYS_INIT_L2_ADDR
 314 #define CFG_SYS_INIT_L2_END     (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 315 #endif
 316 #endif
 317 #endif
 318
 319 /* Serial Port */
 320 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 321 #define CFG_SYS_NS16550_CLK             get_bus_freq(0)
 322
 323 #define CFG_SYS_BAUDRATE_TABLE  \
 324         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 325
 326 #define CFG_SYS_NS16550_COM1    (CFG_SYS_CCSRBAR+0x4500)
 327 #define CFG_SYS_NS16550_COM2    (CFG_SYS_CCSRBAR+0x4600)
 328
 329 /* I2C */
 330 #define I2C_PCA9557_ADDR1               0x18
 331 #define I2C_PCA9557_ADDR2               0x19
 332 #define I2C_PCA9557_BUS_NUM             0
 333
 334 /* I2C EEPROM */
 335 #if defined(CONFIG_TARGET_P1010RDB_PB)
 336 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 337 #endif
 338 /* enable read and write access to EEPROM */
 339
 340 /* RTC */
 341 #define CFG_SYS_I2C_RTC_ADDR    0x68
 342
 343 /*
 344  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 345  * used for SLIC
 346  */
 347 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 348 /* eSPI - Enhanced SPI */
 349 #endif
 350
 351 #ifdef CONFIG_MMC
 352 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 353 #endif
 354
 355 /*
 356  * Environment
 357  */
 358 #if defined(CONFIG_MTD_RAW_NAND)
 359 #ifdef CONFIG_TPL_BUILD
 360 #define SPL_ENV_ADDR            (CFG_SYS_INIT_L2_ADDR + (160 << 10))
 361 #endif
 362 #endif
 363
 364 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 365                  || defined(CONFIG_FSL_SATA)
 366 #endif
 367
 368 /*
 369  * Miscellaneous configurable options
 370  */
 371
 372 /*
 373  * For booting Linux, the board info and command line data
 374  * have to be in the first 64 MB of memory, since this is
 375  * the maximum mapped by the Linux kernel during initialization.
 376  */
 377 #define CFG_SYS_BOOTMAPSZ       (64 << 20) /* Initial Memory map for Linux */
 378
 379 /*
 380  * Environment Configuration
 381  */
 382
 383 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 384 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 385
 386 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 387         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 388         "netdev=eth0\0"                                         \
 389         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 390         "loadaddr=1000000\0"                    \
 391         "consoledev=ttyS0\0"                            \
 392         "ramdiskaddr=2000000\0"                 \
 393         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 394         "fdtaddr=1e00000\0"                             \
 395         "fdtfile=p1010rdb.dtb\0"                \
 396         "bdev=sda1\0"   \
 397         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 398         "othbootargs=ramdisk_size=600000\0" \
 399         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 400         "console=$consoledev,$baudrate $othbootargs; "  \
 401         "usb start;"                    \
 402         "fatload usb 0:2 $loadaddr $bootfile;"          \
 403         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 404         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 405         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 406         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 407         "console=$consoledev,$baudrate $othbootargs; "  \
 408         "usb start;"                    \
 409         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 410         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 411         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 412         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 413         BOOTMODE
 414
 415 #if defined(CONFIG_TARGET_P1010RDB_PA)
 416 #define BOOTMODE \
 417         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 418         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 419         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 420         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 421         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 422         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 423
 424 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 425 #define BOOTMODE \
 426         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 427         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 428         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 429         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 430         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 431         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 432         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 433         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 434         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 435         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 436 #endif
 437
 438 #include <asm/fsl_secure_boot.h>
 439
 440 #endif  /* __CONFIG_H */