1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
20 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
25 #ifdef CONFIG_SPIFLASH
26 #ifdef CONFIG_NXP_ESBC
27 #define CONFIG_RAMBOOT_SPIFLASH
28 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
30 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
31 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
32 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
37 #ifdef CONFIG_MTD_RAW_NAND
38 #ifdef CONFIG_NXP_ESBC
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
41 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
43 #ifdef CONFIG_TPL_BUILD
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
45 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
46 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
47 #elif defined(CONFIG_SPL_BUILD)
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
55 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
56 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
63 /* High Level Configuration Options */
65 #if defined(CONFIG_PCI)
68 * Memory space is mapped 1-1, but I/O space must start from 0.
70 /* controller 1, Slot 1, tgtid 1, Base address a000 */
71 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
72 #ifdef CONFIG_PHYS_64BIT
73 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
75 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
77 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
78 #ifdef CONFIG_PHYS_64BIT
79 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
81 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
84 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
85 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
86 #ifdef CONFIG_PHYS_64BIT
87 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
89 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
91 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
92 #ifdef CONFIG_PHYS_64BIT
93 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
95 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
99 #define CONFIG_HWCONFIG
101 * These can be toggled for performance analysis, otherwise use default.
103 #define CONFIG_L2_CACHE /* toggle L2 cache */
106 #define SPD_EEPROM_ADDRESS 0x52
108 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
111 extern unsigned long get_sdram_size(void);
113 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
117 #define CONFIG_SYS_CCSRBAR 0xffe00000
118 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
123 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
124 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
125 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
127 * Localbus non-cacheable
128 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
129 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
130 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
131 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
137 /* NOR Flash on IFC */
139 #define CONFIG_SYS_FLASH_BASE 0xee000000
140 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
142 #ifdef CONFIG_PHYS_64BIT
143 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
145 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
148 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
149 CSPR_PORT_SIZE_16 | \
152 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
153 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
154 /* NOR Flash Timing Params */
155 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
156 FTIM0_NOR_TEADC(0x5) | \
158 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
159 FTIM1_NOR_TRAD_NOR(0x0f)
160 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
161 FTIM2_NOR_TCH(0x4) | \
163 #define CONFIG_SYS_NOR_FTIM3 0x0
165 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
166 #define CONFIG_SYS_FLASH_QUIET_TEST
167 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
169 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
170 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
172 /* CFI for NOR Flash */
174 /* NAND Flash on IFC */
175 #define CONFIG_SYS_NAND_BASE 0xff800000
176 #ifdef CONFIG_PHYS_64BIT
177 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
179 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
182 #define CONFIG_MTD_PARTITION
184 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
188 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
190 #if defined(CONFIG_TARGET_P1010RDB_PA)
191 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
192 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
193 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
194 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
195 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
196 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
197 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
199 #elif defined(CONFIG_TARGET_P1010RDB_PB)
200 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
201 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
202 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
203 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
204 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
205 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
206 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
209 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
210 #define CONFIG_SYS_MAX_NAND_DEVICE 1
212 #if defined(CONFIG_TARGET_P1010RDB_PA)
213 /* NAND Flash Timing Params */
214 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
215 FTIM0_NAND_TWP(0x0C) | \
216 FTIM0_NAND_TWCHT(0x04) | \
218 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
219 FTIM1_NAND_TWBE(0x1d) | \
220 FTIM1_NAND_TRR(0x07) | \
222 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
223 FTIM2_NAND_TREH(0x05) | \
224 FTIM2_NAND_TWHRE(0x0f)
225 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
227 #elif defined(CONFIG_TARGET_P1010RDB_PB)
228 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
229 /* ONFI NAND Flash mode0 Timing Params */
230 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
231 FTIM0_NAND_TWP(0x18) | \
232 FTIM0_NAND_TWCHT(0x07) | \
233 FTIM0_NAND_TWH(0x0a))
234 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
235 FTIM1_NAND_TWBE(0x39) | \
236 FTIM1_NAND_TRR(0x0e) | \
237 FTIM1_NAND_TRP(0x18))
238 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
239 FTIM2_NAND_TREH(0x0a) | \
240 FTIM2_NAND_TWHRE(0x1e))
241 #define CONFIG_SYS_NAND_FTIM3 0x0
244 #define CONFIG_SYS_NAND_DDR_LAW 11
246 /* Set up IFC registers for boot location NOR/NAND */
247 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
248 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
249 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
250 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
251 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
252 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
253 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
254 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
255 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
256 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
257 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
258 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
259 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
260 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
261 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
263 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
264 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
265 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
266 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
267 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
268 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
269 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
270 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
271 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
272 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
273 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
274 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
275 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
276 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
280 #define CONFIG_SYS_CPLD_BASE 0xffb00000
282 #ifdef CONFIG_PHYS_64BIT
283 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
285 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
288 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
292 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
293 #define CONFIG_SYS_CSOR3 0x0
294 /* CPLD Timing parameters for IFC CS3 */
295 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
296 FTIM0_GPCM_TEADC(0x0e) | \
297 FTIM0_GPCM_TEAHC(0x0e))
298 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
299 FTIM1_GPCM_TRAD(0x1f))
300 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
301 FTIM2_GPCM_TCH(0x8) | \
302 FTIM2_GPCM_TWP(0x1f))
303 #define CONFIG_SYS_CS3_FTIM3 0x0
305 #define CONFIG_SYS_INIT_RAM_LOCK
306 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
307 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
309 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
311 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
314 * Config the L2 Cache as L2 SRAM
316 #if defined(CONFIG_SPL_BUILD)
317 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
318 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
319 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
320 #define CONFIG_SYS_L2_SIZE (256 << 10)
321 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
322 #elif defined(CONFIG_MTD_RAW_NAND)
323 #ifdef CONFIG_TPL_BUILD
324 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
325 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
326 #define CONFIG_SYS_L2_SIZE (256 << 10)
327 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
329 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
330 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
331 #define CONFIG_SYS_L2_SIZE (256 << 10)
332 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
338 #undef CONFIG_SERIAL_SOFTWARE_FIFO
339 #define CONFIG_SYS_NS16550_SERIAL
340 #define CONFIG_SYS_NS16550_REG_SIZE 1
341 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
342 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
343 #define CONFIG_NS16550_MIN_FUNCTIONS
346 #define CONFIG_SYS_BAUDRATE_TABLE \
347 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
349 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
350 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
353 #define I2C_PCA9557_ADDR1 0x18
354 #define I2C_PCA9557_ADDR2 0x19
355 #define I2C_PCA9557_BUS_NUM 0
358 #if defined(CONFIG_TARGET_P1010RDB_PB)
359 #ifdef CONFIG_ID_EEPROM
360 #define CONFIG_SYS_I2C_EEPROM_NXID
362 #define CONFIG_SYS_EEPROM_BUS_NUM 0
363 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
365 /* enable read and write access to EEPROM */
368 #define CONFIG_RTC_PT7C4338
369 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
372 * SPI interface will not be available in case of NAND boot SPI CS0 will be
375 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
376 /* eSPI - Enhanced SPI */
379 #if defined(CONFIG_TSEC_ENET)
380 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
381 #define CONFIG_TSEC1 1
382 #define CONFIG_TSEC1_NAME "eTSEC1"
383 #define CONFIG_TSEC2 1
384 #define CONFIG_TSEC2_NAME "eTSEC2"
385 #define CONFIG_TSEC3 1
386 #define CONFIG_TSEC3_NAME "eTSEC3"
388 #define TSEC1_PHY_ADDR 1
389 #define TSEC2_PHY_ADDR 0
390 #define TSEC3_PHY_ADDR 2
392 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
393 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
394 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
396 #define TSEC1_PHYIDX 0
397 #define TSEC2_PHYIDX 0
398 #define TSEC3_PHYIDX 0
400 /* TBI PHY configuration for SGMII mode */
401 #define CONFIG_TSEC_TBICR_SETTINGS ( \
403 | TBICR_ANEG_ENABLE \
404 | TBICR_FULL_DUPLEX \
408 #endif /* CONFIG_TSEC_ENET */
411 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
417 #if defined(CONFIG_MTD_RAW_NAND)
418 #ifdef CONFIG_TPL_BUILD
419 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
423 #define CONFIG_LOADS_ECHO /* echo on for serial download */
424 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
426 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
427 || defined(CONFIG_FSL_SATA)
431 * Miscellaneous configurable options
435 * For booting Linux, the board info and command line data
436 * have to be in the first 64 MB of memory, since this is
437 * the maximum mapped by the Linux kernel during initialization.
439 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
442 * Environment Configuration
445 #define CONFIG_ROOTPATH "/opt/nfsroot"
446 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
448 #define CONFIG_EXTRA_ENV_SETTINGS \
449 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
451 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
452 "loadaddr=1000000\0" \
453 "consoledev=ttyS0\0" \
454 "ramdiskaddr=2000000\0" \
455 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
456 "fdtaddr=1e00000\0" \
457 "fdtfile=p1010rdb.dtb\0" \
459 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
460 "othbootargs=ramdisk_size=600000\0" \
461 "usbfatboot=setenv bootargs root=/dev/ram rw " \
462 "console=$consoledev,$baudrate $othbootargs; " \
464 "fatload usb 0:2 $loadaddr $bootfile;" \
465 "fatload usb 0:2 $fdtaddr $fdtfile;" \
466 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
467 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
468 "usbext2boot=setenv bootargs root=/dev/ram rw " \
469 "console=$consoledev,$baudrate $othbootargs; " \
471 "ext2load usb 0:4 $loadaddr $bootfile;" \
472 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
473 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
474 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
477 #if defined(CONFIG_TARGET_P1010RDB_PA)
479 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
480 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
481 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
482 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
483 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
484 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
486 #elif defined(CONFIG_TARGET_P1010RDB_PB)
488 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
489 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
490 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
491 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
492 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
493 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
494 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
495 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
496 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
497 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
500 #include <asm/fsl_secure_boot.h>
502 #endif /* __CONFIG_H */