include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  20 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  21 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  22 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  23 #endif
  24
  25 #ifdef CONFIG_SPIFLASH
  26 #ifdef CONFIG_NXP_ESBC
  27 #define CONFIG_RAMBOOT_SPIFLASH
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  29 #else
  30 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  31 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  32 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  34 #endif
  35 #endif
  36
  37 #ifdef CONFIG_MTD_RAW_NAND
  38 #ifdef CONFIG_NXP_ESBC
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  41 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  42 #else
  43 #ifdef CONFIG_TPL_BUILD
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  46 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  47 #elif defined(CONFIG_SPL_BUILD)
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  49 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  50 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  51 #endif
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  56 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  57 #endif
  58
  59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  61 #endif
  62
  63 /* High Level Configuration Options */
  64
  65 #if defined(CONFIG_PCI)
  66 /*
  67  * PCI Windows
  68  * Memory space is mapped 1-1, but I/O space must start from 0.
  69  */
  70 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  71 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
  72 #ifdef CONFIG_PHYS_64BIT
  73 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
  74 #else
  75 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
  76 #endif
  77 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
  78 #ifdef CONFIG_PHYS_64BIT
  79 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
  80 #else
  81 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
  82 #endif
  83
  84 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  85 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
  86 #ifdef CONFIG_PHYS_64BIT
  87 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
  88 #else
  89 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
  90 #endif
  91 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
  92 #ifdef CONFIG_PHYS_64BIT
  93 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
  94 #else
  95 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
  96 #endif
  97
  98 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
  99 #endif
 100
 101 #define CONFIG_HWCONFIG
 102 /*
 103  * These can be toggled for performance analysis, otherwise use default.
 104  */
 105 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 106
 107 /* DDR Setup */
 108 #define SPD_EEPROM_ADDRESS              0x52
 109
 110 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 111
 112 #ifndef __ASSEMBLY__
 113 extern unsigned long get_sdram_size(void);
 114 #endif
 115 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 116 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 118
 119 /* DDR3 Controller Settings */
 120 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 121 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 122 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 123 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 124 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 125 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 126 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 127 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 128 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 129 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 130 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 131 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 132 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 133 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 134 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 135
 136 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 137 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 138 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 139 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 140 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 141 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 142 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 143 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 144 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 145
 146 /* settings for DDR3 at 667MT/s */
 147 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 148 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 149 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 150 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 151 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 152 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 153 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 154 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 155 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 156
 157 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 158 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 159
 160 /*
 161  * Memory map
 162  *
 163  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 164  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 165  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 166  *
 167  * Localbus non-cacheable
 168  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 169  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 170  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 171  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 172  */
 173
 174 /*
 175  * IFC Definitions
 176  */
 177 /* NOR Flash on IFC */
 178
 179 #define CONFIG_SYS_FLASH_BASE           0xee000000
 180 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 181
 182 #ifdef CONFIG_PHYS_64BIT
 183 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 184 #else
 185 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 186 #endif
 187
 188 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 189                                 CSPR_PORT_SIZE_16 | \
 190                                 CSPR_MSEL_NOR | \
 191                                 CSPR_V)
 192 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 193 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 194 /* NOR Flash Timing Params */
 195 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 196                                 FTIM0_NOR_TEADC(0x5) | \
 197                                 FTIM0_NOR_TEAHC(0x5)
 198 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 199                                 FTIM1_NOR_TRAD_NOR(0x0f)
 200 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 201                                 FTIM2_NOR_TCH(0x4) | \
 202                                 FTIM2_NOR_TWP(0x1c)
 203 #define CONFIG_SYS_NOR_FTIM3    0x0
 204
 205 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 206 #define CONFIG_SYS_FLASH_QUIET_TEST
 207 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 208
 209 #undef CONFIG_SYS_FLASH_CHECKSUM
 210 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 211 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 212
 213 /* CFI for NOR Flash */
 214 #define CONFIG_SYS_FLASH_EMPTY_INFO
 215
 216 /* NAND Flash on IFC */
 217 #define CONFIG_SYS_NAND_BASE            0xff800000
 218 #ifdef CONFIG_PHYS_64BIT
 219 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 220 #else
 221 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 222 #endif
 223
 224 #define CONFIG_MTD_PARTITION
 225
 226 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 227                                 | CSPR_PORT_SIZE_8      \
 228                                 | CSPR_MSEL_NAND        \
 229                                 | CSPR_V)
 230 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 231
 232 #if defined(CONFIG_TARGET_P1010RDB_PA)
 233 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 234                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 235                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 236                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 237                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 238                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 239                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 240
 241 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 242 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 243                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 244                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 245                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 246                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 247                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 248                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 249 #endif
 250
 251 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 252 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 253
 254 #if defined(CONFIG_TARGET_P1010RDB_PA)
 255 /* NAND Flash Timing Params */
 256 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 257                                         FTIM0_NAND_TWP(0x0C)   | \
 258                                         FTIM0_NAND_TWCHT(0x04) | \
 259                                         FTIM0_NAND_TWH(0x05)
 260 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 261                                         FTIM1_NAND_TWBE(0x1d)  | \
 262                                         FTIM1_NAND_TRR(0x07)   | \
 263                                         FTIM1_NAND_TRP(0x0c)
 264 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 265                                         FTIM2_NAND_TREH(0x05) | \
 266                                         FTIM2_NAND_TWHRE(0x0f)
 267 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 268
 269 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 270 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 271 /* ONFI NAND Flash mode0 Timing Params */
 272 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 273                                         FTIM0_NAND_TWP(0x18)   | \
 274                                         FTIM0_NAND_TWCHT(0x07) | \
 275                                         FTIM0_NAND_TWH(0x0a))
 276 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 277                                         FTIM1_NAND_TWBE(0x39)  | \
 278                                         FTIM1_NAND_TRR(0x0e)   | \
 279                                         FTIM1_NAND_TRP(0x18))
 280 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 281                                         FTIM2_NAND_TREH(0x0a)  | \
 282                                         FTIM2_NAND_TWHRE(0x1e))
 283 #define CONFIG_SYS_NAND_FTIM3   0x0
 284 #endif
 285
 286 #define CONFIG_SYS_NAND_DDR_LAW         11
 287
 288 /* Set up IFC registers for boot location NOR/NAND */
 289 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 290 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 291 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 292 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 293 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 294 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 295 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 296 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 297 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 298 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 299 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 300 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 301 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 302 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 303 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 304 #else
 305 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 306 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 307 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 308 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 309 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 310 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 311 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 312 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 313 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 314 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 315 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 316 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 317 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 318 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 319 #endif
 320
 321 /* CPLD on IFC */
 322 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 323
 324 #ifdef CONFIG_PHYS_64BIT
 325 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 326 #else
 327 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 328 #endif
 329
 330 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 331                                 | CSPR_PORT_SIZE_8 \
 332                                 | CSPR_MSEL_GPCM \
 333                                 | CSPR_V)
 334 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 335 #define CONFIG_SYS_CSOR3                0x0
 336 /* CPLD Timing parameters for IFC CS3 */
 337 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 338                                         FTIM0_GPCM_TEADC(0x0e) | \
 339                                         FTIM0_GPCM_TEAHC(0x0e))
 340 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 341                                         FTIM1_GPCM_TRAD(0x1f))
 342 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 343                                         FTIM2_GPCM_TCH(0x8) | \
 344                                         FTIM2_GPCM_TWP(0x1f))
 345 #define CONFIG_SYS_CS3_FTIM3            0x0
 346
 347 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 348 #define CONFIG_SYS_RAMBOOT
 349 #else
 350 #undef CONFIG_SYS_RAMBOOT
 351 #endif
 352
 353 #define CONFIG_SYS_INIT_RAM_LOCK
 354 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 355 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 356
 357 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 358
 359 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 360
 361 /*
 362  * Config the L2 Cache as L2 SRAM
 363  */
 364 #if defined(CONFIG_SPL_BUILD)
 365 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 366 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 367 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 368 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 369 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 370 #elif defined(CONFIG_MTD_RAW_NAND)
 371 #ifdef CONFIG_TPL_BUILD
 372 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 373 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 374 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 375 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 376 #else
 377 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 378 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 379 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 380 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 381 #endif
 382 #endif
 383 #endif
 384
 385 /* Serial Port */
 386 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 387 #define CONFIG_SYS_NS16550_SERIAL
 388 #define CONFIG_SYS_NS16550_REG_SIZE     1
 389 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 390 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
 391 #define CONFIG_NS16550_MIN_FUNCTIONS
 392 #endif
 393
 394 #define CONFIG_SYS_BAUDRATE_TABLE       \
 395         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 396
 397 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 398 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 399
 400 /* I2C */
 401 #define I2C_PCA9557_ADDR1               0x18
 402 #define I2C_PCA9557_ADDR2               0x19
 403 #define I2C_PCA9557_BUS_NUM             0
 404
 405 /* I2C EEPROM */
 406 #if defined(CONFIG_TARGET_P1010RDB_PB)
 407 #ifdef CONFIG_ID_EEPROM
 408 #define CONFIG_SYS_I2C_EEPROM_NXID
 409 #endif
 410 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 411 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 412 #endif
 413 /* enable read and write access to EEPROM */
 414
 415 /* RTC */
 416 #define CONFIG_RTC_PT7C4338
 417 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 418
 419 /*
 420  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 421  * used for SLIC
 422  */
 423 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 424 /* eSPI - Enhanced SPI */
 425 #endif
 426
 427 #if defined(CONFIG_TSEC_ENET)
 428 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 429 #define CONFIG_TSEC1    1
 430 #define CONFIG_TSEC1_NAME       "eTSEC1"
 431 #define CONFIG_TSEC2    1
 432 #define CONFIG_TSEC2_NAME       "eTSEC2"
 433 #define CONFIG_TSEC3    1
 434 #define CONFIG_TSEC3_NAME       "eTSEC3"
 435
 436 #define TSEC1_PHY_ADDR          1
 437 #define TSEC2_PHY_ADDR          0
 438 #define TSEC3_PHY_ADDR          2
 439
 440 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 441 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 442 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 443
 444 #define TSEC1_PHYIDX            0
 445 #define TSEC2_PHYIDX            0
 446 #define TSEC3_PHYIDX            0
 447
 448 /* TBI PHY configuration for SGMII mode */
 449 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 450                 TBICR_PHY_RESET \
 451                 | TBICR_ANEG_ENABLE \
 452                 | TBICR_FULL_DUPLEX \
 453                 | TBICR_SPEED1_SET \
 454                 )
 455
 456 #endif  /* CONFIG_TSEC_ENET */
 457
 458 #ifdef CONFIG_MMC
 459 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 460 #endif
 461
 462 /*
 463  * Environment
 464  */
 465 #if defined(CONFIG_MTD_RAW_NAND)
 466 #ifdef CONFIG_TPL_BUILD
 467 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 468 #endif
 469 #endif
 470
 471 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 472 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 473
 474 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 475                  || defined(CONFIG_FSL_SATA)
 476 #endif
 477
 478 /*
 479  * Miscellaneous configurable options
 480  */
 481
 482 /*
 483  * For booting Linux, the board info and command line data
 484  * have to be in the first 64 MB of memory, since this is
 485  * the maximum mapped by the Linux kernel during initialization.
 486  */
 487 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 488 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 489
 490 /*
 491  * Environment Configuration
 492  */
 493
 494 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 495 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 496
 497 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 498         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 499         "netdev=eth0\0"                                         \
 500         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 501         "loadaddr=1000000\0"                    \
 502         "consoledev=ttyS0\0"                            \
 503         "ramdiskaddr=2000000\0"                 \
 504         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 505         "fdtaddr=1e00000\0"                             \
 506         "fdtfile=p1010rdb.dtb\0"                \
 507         "bdev=sda1\0"   \
 508         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 509         "othbootargs=ramdisk_size=600000\0" \
 510         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 511         "console=$consoledev,$baudrate $othbootargs; "  \
 512         "usb start;"                    \
 513         "fatload usb 0:2 $loadaddr $bootfile;"          \
 514         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 515         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 516         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 517         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 518         "console=$consoledev,$baudrate $othbootargs; "  \
 519         "usb start;"                    \
 520         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 521         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 522         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 523         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 524         BOOTMODE
 525
 526 #if defined(CONFIG_TARGET_P1010RDB_PA)
 527 #define BOOTMODE \
 528         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 529         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 530         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 531         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 532         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 533         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 534
 535 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 536 #define BOOTMODE \
 537         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 538         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 539         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 540         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 541         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 542         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 543         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 544         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 545         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 546         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 547 #endif
 548
 549 #include <asm/fsl_secure_boot.h>
 550
 551 #endif  /* __CONFIG_H */