1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * P010 RDB board configuration file
14 #include <linux/stringify.h>
16 #include <asm/config_mpc85xx.h>
19 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
20 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
22 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
25 #ifdef CONFIG_SPIFLASH
26 #ifdef CONFIG_NXP_ESBC
27 #define CONFIG_RAMBOOT_SPIFLASH
28 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
30 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
31 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
32 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
33 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
37 #ifdef CONFIG_MTD_RAW_NAND
38 #ifdef CONFIG_NXP_ESBC
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
41 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
43 #ifdef CONFIG_TPL_BUILD
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
45 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
46 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
47 #elif defined(CONFIG_SPL_BUILD)
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
55 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
56 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
63 /* High Level Configuration Options */
65 #if defined(CONFIG_PCI)
68 * Memory space is mapped 1-1, but I/O space must start from 0.
70 /* controller 1, Slot 1, tgtid 1, Base address a000 */
71 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
72 #ifdef CONFIG_PHYS_64BIT
73 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
75 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
77 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
78 #ifdef CONFIG_PHYS_64BIT
79 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
81 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
84 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
85 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
86 #ifdef CONFIG_PHYS_64BIT
87 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
89 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
91 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
92 #ifdef CONFIG_PHYS_64BIT
93 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
95 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
99 #define CONFIG_HWCONFIG
101 * These can be toggled for performance analysis, otherwise use default.
103 #define CONFIG_L2_CACHE /* toggle L2 cache */
106 #define SPD_EEPROM_ADDRESS 0x52
108 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
111 extern unsigned long get_sdram_size(void);
113 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
117 /* DDR3 Controller Settings */
118 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
119 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
120 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
121 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
122 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
123 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
124 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
125 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
126 #define CONFIG_SYS_DDR_RCW_1 0x00000000
127 #define CONFIG_SYS_DDR_RCW_2 0x00000000
128 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
129 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
130 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
131 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
133 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
134 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
135 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
136 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
137 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
138 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
139 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
140 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
141 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
143 /* settings for DDR3 at 667MT/s */
144 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
145 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
146 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
147 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
148 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
149 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
150 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
151 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
152 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
154 #define CONFIG_SYS_CCSRBAR 0xffe00000
155 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
160 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
161 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
162 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
164 * Localbus non-cacheable
165 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
166 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
167 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
168 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
174 /* NOR Flash on IFC */
176 #define CONFIG_SYS_FLASH_BASE 0xee000000
177 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
179 #ifdef CONFIG_PHYS_64BIT
180 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
182 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
185 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
186 CSPR_PORT_SIZE_16 | \
189 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
190 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
191 /* NOR Flash Timing Params */
192 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
193 FTIM0_NOR_TEADC(0x5) | \
195 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
196 FTIM1_NOR_TRAD_NOR(0x0f)
197 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
198 FTIM2_NOR_TCH(0x4) | \
200 #define CONFIG_SYS_NOR_FTIM3 0x0
202 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
203 #define CONFIG_SYS_FLASH_QUIET_TEST
204 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
206 #undef CONFIG_SYS_FLASH_CHECKSUM
207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
210 /* CFI for NOR Flash */
211 #define CONFIG_SYS_FLASH_EMPTY_INFO
213 /* NAND Flash on IFC */
214 #define CONFIG_SYS_NAND_BASE 0xff800000
215 #ifdef CONFIG_PHYS_64BIT
216 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
218 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
221 #define CONFIG_MTD_PARTITION
223 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
227 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
229 #if defined(CONFIG_TARGET_P1010RDB_PA)
230 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
231 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
232 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
233 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
234 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
235 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
236 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
238 #elif defined(CONFIG_TARGET_P1010RDB_PB)
239 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
240 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
241 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
242 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
243 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
244 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
245 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
248 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
249 #define CONFIG_SYS_MAX_NAND_DEVICE 1
251 #if defined(CONFIG_TARGET_P1010RDB_PA)
252 /* NAND Flash Timing Params */
253 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
254 FTIM0_NAND_TWP(0x0C) | \
255 FTIM0_NAND_TWCHT(0x04) | \
257 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
258 FTIM1_NAND_TWBE(0x1d) | \
259 FTIM1_NAND_TRR(0x07) | \
261 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
262 FTIM2_NAND_TREH(0x05) | \
263 FTIM2_NAND_TWHRE(0x0f)
264 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
266 #elif defined(CONFIG_TARGET_P1010RDB_PB)
267 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
268 /* ONFI NAND Flash mode0 Timing Params */
269 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
270 FTIM0_NAND_TWP(0x18) | \
271 FTIM0_NAND_TWCHT(0x07) | \
272 FTIM0_NAND_TWH(0x0a))
273 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
274 FTIM1_NAND_TWBE(0x39) | \
275 FTIM1_NAND_TRR(0x0e) | \
276 FTIM1_NAND_TRP(0x18))
277 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
278 FTIM2_NAND_TREH(0x0a) | \
279 FTIM2_NAND_TWHRE(0x1e))
280 #define CONFIG_SYS_NAND_FTIM3 0x0
283 #define CONFIG_SYS_NAND_DDR_LAW 11
285 /* Set up IFC registers for boot location NOR/NAND */
286 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
287 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
288 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
289 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
290 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
291 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
292 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
293 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
294 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
295 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
296 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
297 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
298 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
299 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
300 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
302 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
303 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
304 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
305 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
306 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
307 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
308 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
309 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
310 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
311 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
312 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
313 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
314 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
315 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
319 #define CONFIG_SYS_CPLD_BASE 0xffb00000
321 #ifdef CONFIG_PHYS_64BIT
322 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
324 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
327 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
331 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
332 #define CONFIG_SYS_CSOR3 0x0
333 /* CPLD Timing parameters for IFC CS3 */
334 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
335 FTIM0_GPCM_TEADC(0x0e) | \
336 FTIM0_GPCM_TEAHC(0x0e))
337 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
338 FTIM1_GPCM_TRAD(0x1f))
339 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
340 FTIM2_GPCM_TCH(0x8) | \
341 FTIM2_GPCM_TWP(0x1f))
342 #define CONFIG_SYS_CS3_FTIM3 0x0
344 #define CONFIG_SYS_INIT_RAM_LOCK
345 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
346 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
348 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
350 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
353 * Config the L2 Cache as L2 SRAM
355 #if defined(CONFIG_SPL_BUILD)
356 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
357 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
358 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
359 #define CONFIG_SYS_L2_SIZE (256 << 10)
360 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
361 #elif defined(CONFIG_MTD_RAW_NAND)
362 #ifdef CONFIG_TPL_BUILD
363 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
364 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
365 #define CONFIG_SYS_L2_SIZE (256 << 10)
366 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
368 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
369 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
370 #define CONFIG_SYS_L2_SIZE (256 << 10)
371 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
377 #undef CONFIG_SERIAL_SOFTWARE_FIFO
378 #define CONFIG_SYS_NS16550_SERIAL
379 #define CONFIG_SYS_NS16550_REG_SIZE 1
380 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
381 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
382 #define CONFIG_NS16550_MIN_FUNCTIONS
385 #define CONFIG_SYS_BAUDRATE_TABLE \
386 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
388 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
389 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
392 #define I2C_PCA9557_ADDR1 0x18
393 #define I2C_PCA9557_ADDR2 0x19
394 #define I2C_PCA9557_BUS_NUM 0
397 #if defined(CONFIG_TARGET_P1010RDB_PB)
398 #ifdef CONFIG_ID_EEPROM
399 #define CONFIG_SYS_I2C_EEPROM_NXID
401 #define CONFIG_SYS_EEPROM_BUS_NUM 0
402 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
404 /* enable read and write access to EEPROM */
407 #define CONFIG_RTC_PT7C4338
408 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
411 * SPI interface will not be available in case of NAND boot SPI CS0 will be
414 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
415 /* eSPI - Enhanced SPI */
418 #if defined(CONFIG_TSEC_ENET)
419 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
420 #define CONFIG_TSEC1 1
421 #define CONFIG_TSEC1_NAME "eTSEC1"
422 #define CONFIG_TSEC2 1
423 #define CONFIG_TSEC2_NAME "eTSEC2"
424 #define CONFIG_TSEC3 1
425 #define CONFIG_TSEC3_NAME "eTSEC3"
427 #define TSEC1_PHY_ADDR 1
428 #define TSEC2_PHY_ADDR 0
429 #define TSEC3_PHY_ADDR 2
431 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
432 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
433 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
435 #define TSEC1_PHYIDX 0
436 #define TSEC2_PHYIDX 0
437 #define TSEC3_PHYIDX 0
439 /* TBI PHY configuration for SGMII mode */
440 #define CONFIG_TSEC_TBICR_SETTINGS ( \
442 | TBICR_ANEG_ENABLE \
443 | TBICR_FULL_DUPLEX \
447 #endif /* CONFIG_TSEC_ENET */
450 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
456 #if defined(CONFIG_MTD_RAW_NAND)
457 #ifdef CONFIG_TPL_BUILD
458 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
462 #define CONFIG_LOADS_ECHO /* echo on for serial download */
463 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
465 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
466 || defined(CONFIG_FSL_SATA)
470 * Miscellaneous configurable options
474 * For booting Linux, the board info and command line data
475 * have to be in the first 64 MB of memory, since this is
476 * the maximum mapped by the Linux kernel during initialization.
478 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
481 * Environment Configuration
484 #define CONFIG_ROOTPATH "/opt/nfsroot"
485 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
487 #define CONFIG_EXTRA_ENV_SETTINGS \
488 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
490 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
491 "loadaddr=1000000\0" \
492 "consoledev=ttyS0\0" \
493 "ramdiskaddr=2000000\0" \
494 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
495 "fdtaddr=1e00000\0" \
496 "fdtfile=p1010rdb.dtb\0" \
498 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
499 "othbootargs=ramdisk_size=600000\0" \
500 "usbfatboot=setenv bootargs root=/dev/ram rw " \
501 "console=$consoledev,$baudrate $othbootargs; " \
503 "fatload usb 0:2 $loadaddr $bootfile;" \
504 "fatload usb 0:2 $fdtaddr $fdtfile;" \
505 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
506 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
507 "usbext2boot=setenv bootargs root=/dev/ram rw " \
508 "console=$consoledev,$baudrate $othbootargs; " \
510 "ext2load usb 0:4 $loadaddr $bootfile;" \
511 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
512 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
513 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
516 #if defined(CONFIG_TARGET_P1010RDB_PA)
518 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
519 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
520 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
521 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
522 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
523 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
525 #elif defined(CONFIG_TARGET_P1010RDB_PB)
527 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
528 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
529 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
530 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
531 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
532 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
533 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
534 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
535 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
536 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
539 #include <asm/fsl_secure_boot.h>
541 #endif /* __CONFIG_H */