include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17 #define CONFIG_NAND_FSL_IFC
  18
  19 #ifdef CONFIG_SDCARD
  20 #define CONFIG_SPL_FLUSH_IMAGE
  21 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  22 #define CONFIG_SPL_PAD_TO               0x18000
  23 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  24 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  25 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  26 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  27 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  28 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  29 #ifdef CONFIG_SPL_BUILD
  30 #define CONFIG_SPL_COMMON_INIT_DDR
  31 #endif
  32 #endif
  33
  34 #ifdef CONFIG_SPIFLASH
  35 #ifdef CONFIG_NXP_ESBC
  36 #define CONFIG_RAMBOOT_SPIFLASH
  37 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  38 #else
  39 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  40 #define CONFIG_SPL_FLUSH_IMAGE
  41 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  42 #define CONFIG_SPL_PAD_TO                       0x18000
  43 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  49 #ifdef CONFIG_SPL_BUILD
  50 #define CONFIG_SPL_COMMON_INIT_DDR
  51 #endif
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_MTD_RAW_NAND
  56 #ifdef CONFIG_NXP_ESBC
  57 #define CONFIG_SPL_INIT_MINIMAL
  58 #define CONFIG_SPL_FLUSH_IMAGE
  59 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  60
  61 #define CONFIG_SPL_MAX_SIZE             8192
  62 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  63 #define CONFIG_SPL_RELOC_STACK          0x00100000
  64 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  65 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  66 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  67 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  68 #else
  69 #ifdef CONFIG_TPL_BUILD
  70 #define CONFIG_SPL_FLUSH_IMAGE
  71 #define CONFIG_SPL_NAND_INIT
  72 #define CONFIG_SPL_COMMON_INIT_DDR
  73 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  74 #define CONFIG_TPL_TEXT_BASE            0xD0001000
  75 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  76 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  77 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  78 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  79 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  80 #elif defined(CONFIG_SPL_BUILD)
  81 #define CONFIG_SPL_INIT_MINIMAL
  82 #define CONFIG_SPL_NAND_MINIMAL
  83 #define CONFIG_SPL_FLUSH_IMAGE
  84 #define CONFIG_SPL_MAX_SIZE             8192
  85 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  86 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  87 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  88 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  89 #endif
  90 #define CONFIG_SPL_PAD_TO       0x20000
  91 #define CONFIG_TPL_PAD_TO       0x20000
  92 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  93 #endif
  94 #endif
  95
  96 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  97 #define CONFIG_RAMBOOT_NAND
  98 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  99 #endif
 100
 101 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 102 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 103 #endif
 104
 105 #ifdef CONFIG_TPL_BUILD
 106 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
 107 #elif defined(CONFIG_SPL_BUILD)
 108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 109 #else
 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 111 #endif
 112
 113 /* High Level Configuration Options */
 114 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 115
 116 #if defined(CONFIG_PCI)
 117 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 118 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 119 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 120
 121 /*
 122  * PCI Windows
 123  * Memory space is mapped 1-1, but I/O space must start from 0.
 124  */
 125 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 126 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 127 #ifdef CONFIG_PHYS_64BIT
 128 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 129 #else
 130 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 131 #endif
 132 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 133 #ifdef CONFIG_PHYS_64BIT
 134 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 135 #else
 136 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 137 #endif
 138
 139 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 140 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 141 #ifdef CONFIG_PHYS_64BIT
 142 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 143 #else
 144 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 145 #endif
 146 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 147 #ifdef CONFIG_PHYS_64BIT
 148 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 149 #else
 150 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 151 #endif
 152
 153 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 154 #endif
 155
 156 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 157 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 158
 159 #define CONFIG_HWCONFIG
 160 /*
 161  * These can be toggled for performance analysis, otherwise use default.
 162  */
 163 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 164 #define CONFIG_BTB                      /* toggle branch predition */
 165
 166
 167 #define CONFIG_ENABLE_36BIT_PHYS
 168
 169 /* DDR Setup */
 170 #define CONFIG_SYS_DDR_RAW_TIMING
 171 #define CONFIG_DDR_SPD
 172 #define CONFIG_SYS_SPD_BUS_NUM          1
 173 #define SPD_EEPROM_ADDRESS              0x52
 174
 175 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 176
 177 #ifndef __ASSEMBLY__
 178 extern unsigned long get_sdram_size(void);
 179 #endif
 180 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 181 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 182 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 183
 184 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 185 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 186
 187 /* DDR3 Controller Settings */
 188 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 189 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 190 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 191 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 192 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 193 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 194 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 195 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 196 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 197 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 198 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 199 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 200 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 201 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 202 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 203
 204 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 205 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 206 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 207 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 208 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 209 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 210 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 211 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 212 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 213
 214 /* settings for DDR3 at 667MT/s */
 215 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 216 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 217 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 218 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 219 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 220 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 221 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 222 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 223 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 224
 225 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 226 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 227
 228 /* Don't relocate CCSRBAR while in NAND_SPL */
 229 #ifdef CONFIG_SPL_BUILD
 230 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 231 #endif
 232
 233 /*
 234  * Memory map
 235  *
 236  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 237  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 238  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 239  *
 240  * Localbus non-cacheable
 241  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 242  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 243  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 244  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 245  */
 246
 247 /*
 248  * IFC Definitions
 249  */
 250 /* NOR Flash on IFC */
 251
 252 #define CONFIG_SYS_FLASH_BASE           0xee000000
 253 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 254
 255 #ifdef CONFIG_PHYS_64BIT
 256 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 257 #else
 258 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 259 #endif
 260
 261 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 262                                 CSPR_PORT_SIZE_16 | \
 263                                 CSPR_MSEL_NOR | \
 264                                 CSPR_V)
 265 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 266 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 267 /* NOR Flash Timing Params */
 268 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 269                                 FTIM0_NOR_TEADC(0x5) | \
 270                                 FTIM0_NOR_TEAHC(0x5)
 271 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 272                                 FTIM1_NOR_TRAD_NOR(0x0f)
 273 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 274                                 FTIM2_NOR_TCH(0x4) | \
 275                                 FTIM2_NOR_TWP(0x1c)
 276 #define CONFIG_SYS_NOR_FTIM3    0x0
 277
 278 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 279 #define CONFIG_SYS_FLASH_QUIET_TEST
 280 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 281 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 282
 283 #undef CONFIG_SYS_FLASH_CHECKSUM
 284 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 285 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 286
 287 /* CFI for NOR Flash */
 288 #define CONFIG_SYS_FLASH_EMPTY_INFO
 289
 290 /* NAND Flash on IFC */
 291 #define CONFIG_SYS_NAND_BASE            0xff800000
 292 #ifdef CONFIG_PHYS_64BIT
 293 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 294 #else
 295 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 296 #endif
 297
 298 #define CONFIG_MTD_PARTITION
 299
 300 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 301                                 | CSPR_PORT_SIZE_8      \
 302                                 | CSPR_MSEL_NAND        \
 303                                 | CSPR_V)
 304 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 305
 306 #if defined(CONFIG_TARGET_P1010RDB_PA)
 307 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 308                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 309                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 310                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 311                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 312                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 313                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 314 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 315
 316 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 317 #define CONFIG_SYS_NAND_ONFI_DETECTION
 318 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 319                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 320                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 321                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 322                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 323                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 324                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 325 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 326 #endif
 327
 328 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 329 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 330
 331 #if defined(CONFIG_TARGET_P1010RDB_PA)
 332 /* NAND Flash Timing Params */
 333 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 334                                         FTIM0_NAND_TWP(0x0C)   | \
 335                                         FTIM0_NAND_TWCHT(0x04) | \
 336                                         FTIM0_NAND_TWH(0x05)
 337 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 338                                         FTIM1_NAND_TWBE(0x1d)  | \
 339                                         FTIM1_NAND_TRR(0x07)   | \
 340                                         FTIM1_NAND_TRP(0x0c)
 341 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 342                                         FTIM2_NAND_TREH(0x05) | \
 343                                         FTIM2_NAND_TWHRE(0x0f)
 344 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 345
 346 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 347 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 348 /* ONFI NAND Flash mode0 Timing Params */
 349 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 350                                         FTIM0_NAND_TWP(0x18)   | \
 351                                         FTIM0_NAND_TWCHT(0x07) | \
 352                                         FTIM0_NAND_TWH(0x0a))
 353 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 354                                         FTIM1_NAND_TWBE(0x39)  | \
 355                                         FTIM1_NAND_TRR(0x0e)   | \
 356                                         FTIM1_NAND_TRP(0x18))
 357 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 358                                         FTIM2_NAND_TREH(0x0a)  | \
 359                                         FTIM2_NAND_TWHRE(0x1e))
 360 #define CONFIG_SYS_NAND_FTIM3   0x0
 361 #endif
 362
 363 #define CONFIG_SYS_NAND_DDR_LAW         11
 364
 365 /* Set up IFC registers for boot location NOR/NAND */
 366 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 367 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 368 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 369 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 370 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 371 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 372 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 373 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 374 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 375 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 376 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 377 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 378 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 379 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 380 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 381 #else
 382 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 383 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 384 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 385 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 386 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 387 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 388 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 389 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 390 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 391 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 392 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 393 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 394 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 395 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 396 #endif
 397
 398 /* CPLD on IFC */
 399 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 400
 401 #ifdef CONFIG_PHYS_64BIT
 402 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 403 #else
 404 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 405 #endif
 406
 407 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 408                                 | CSPR_PORT_SIZE_8 \
 409                                 | CSPR_MSEL_GPCM \
 410                                 | CSPR_V)
 411 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 412 #define CONFIG_SYS_CSOR3                0x0
 413 /* CPLD Timing parameters for IFC CS3 */
 414 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 415                                         FTIM0_GPCM_TEADC(0x0e) | \
 416                                         FTIM0_GPCM_TEAHC(0x0e))
 417 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 418                                         FTIM1_GPCM_TRAD(0x1f))
 419 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 420                                         FTIM2_GPCM_TCH(0x8) | \
 421                                         FTIM2_GPCM_TWP(0x1f))
 422 #define CONFIG_SYS_CS3_FTIM3            0x0
 423
 424 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 425         defined(CONFIG_RAMBOOT_NAND)
 426 #define CONFIG_SYS_RAMBOOT
 427 #else
 428 #undef CONFIG_SYS_RAMBOOT
 429 #endif
 430
 431 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 432 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 433 #define CONFIG_A003399_NOR_WORKAROUND
 434 #endif
 435 #endif
 436
 437 #define CONFIG_SYS_INIT_RAM_LOCK
 438 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 439 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 440
 441 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 442                                                 - GENERATED_GBL_DATA_SIZE)
 443 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 444
 445 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 446 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 447
 448 /*
 449  * Config the L2 Cache as L2 SRAM
 450  */
 451 #if defined(CONFIG_SPL_BUILD)
 452 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 453 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 454 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 455 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 456 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 457 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 458 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 459 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 460 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 461 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 462 #elif defined(CONFIG_MTD_RAW_NAND)
 463 #ifdef CONFIG_TPL_BUILD
 464 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 465 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 466 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 467 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 468 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 469 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 470 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 471 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 472 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 473 #else
 474 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 475 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 476 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 477 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 478 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 479 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 480 #endif
 481 #endif
 482 #endif
 483
 484 /* Serial Port */
 485 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 486 #define CONFIG_SYS_NS16550_SERIAL
 487 #define CONFIG_SYS_NS16550_REG_SIZE     1
 488 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 489 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 490 #define CONFIG_NS16550_MIN_FUNCTIONS
 491 #endif
 492
 493 #define CONFIG_SYS_BAUDRATE_TABLE       \
 494         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 495
 496 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 497 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 498
 499 /* I2C */
 500 #if !CONFIG_IS_ENABLED(DM_I2C)
 501 #define CONFIG_SYS_I2C_LEGACY
 502 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 503 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 504 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 505 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 506 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 507 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 508 #else
 509 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 510 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 511 #endif
 512 #define I2C_PCA9557_ADDR1               0x18
 513 #define I2C_PCA9557_ADDR2               0x19
 514 #define I2C_PCA9557_BUS_NUM             0
 515 #define CONFIG_SYS_I2C_FSL
 516
 517 /* I2C EEPROM */
 518 #if defined(CONFIG_TARGET_P1010RDB_PB)
 519 #ifdef CONFIG_ID_EEPROM
 520 #define CONFIG_SYS_I2C_EEPROM_NXID
 521 #endif
 522 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 523 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 524 #endif
 525 /* enable read and write access to EEPROM */
 526
 527 /* RTC */
 528 #define CONFIG_RTC_PT7C4338
 529 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 530
 531 /*
 532  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 533  * used for SLIC
 534  */
 535 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 536 /* eSPI - Enhanced SPI */
 537 #endif
 538
 539 #if defined(CONFIG_TSEC_ENET)
 540 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 541 #define CONFIG_TSEC1    1
 542 #define CONFIG_TSEC1_NAME       "eTSEC1"
 543 #define CONFIG_TSEC2    1
 544 #define CONFIG_TSEC2_NAME       "eTSEC2"
 545 #define CONFIG_TSEC3    1
 546 #define CONFIG_TSEC3_NAME       "eTSEC3"
 547
 548 #define TSEC1_PHY_ADDR          1
 549 #define TSEC2_PHY_ADDR          0
 550 #define TSEC3_PHY_ADDR          2
 551
 552 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 553 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 554 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 555
 556 #define TSEC1_PHYIDX            0
 557 #define TSEC2_PHYIDX            0
 558 #define TSEC3_PHYIDX            0
 559
 560 #define CONFIG_ETHPRIME         "eTSEC1"
 561
 562 /* TBI PHY configuration for SGMII mode */
 563 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 564                 TBICR_PHY_RESET \
 565                 | TBICR_ANEG_ENABLE \
 566                 | TBICR_FULL_DUPLEX \
 567                 | TBICR_SPEED1_SET \
 568                 )
 569
 570 #endif  /* CONFIG_TSEC_ENET */
 571
 572 /* SATA */
 573 #define CONFIG_FSL_SATA_V2
 574
 575 #ifdef CONFIG_FSL_SATA
 576 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 577 #define CONFIG_SATA1
 578 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 579 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 580 #define CONFIG_SATA2
 581 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 582 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 583
 584 #define CONFIG_LBA48
 585 #endif /* #ifdef CONFIG_FSL_SATA  */
 586
 587 #ifdef CONFIG_MMC
 588 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 589 #endif
 590
 591 #define CONFIG_HAS_FSL_DR_USB
 592
 593 #if defined(CONFIG_HAS_FSL_DR_USB)
 594 #ifdef CONFIG_USB_EHCI_HCD
 595 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 596 #define CONFIG_USB_EHCI_FSL
 597 #endif
 598 #endif
 599
 600 /*
 601  * Environment
 602  */
 603 #if defined(CONFIG_SDCARD)
 604 #define CONFIG_FSL_FIXED_MMC_LOCATION
 605 #elif defined(CONFIG_MTD_RAW_NAND)
 606 #ifdef CONFIG_TPL_BUILD
 607 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 608 #else
 609 #if defined(CONFIG_TARGET_P1010RDB_PA)
 610 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 611 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 612 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 613 #endif
 614 #endif
 615 #endif
 616
 617 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 618 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 619
 620 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 621
 622 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 623                  || defined(CONFIG_FSL_SATA)
 624 #endif
 625
 626 /*
 627  * Miscellaneous configurable options
 628  */
 629 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 630
 631 /*
 632  * For booting Linux, the board info and command line data
 633  * have to be in the first 64 MB of memory, since this is
 634  * the maximum mapped by the Linux kernel during initialization.
 635  */
 636 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 637 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 638
 639 #if defined(CONFIG_CMD_KGDB)
 640 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 641 #endif
 642
 643 /*
 644  * Environment Configuration
 645  */
 646
 647 #if defined(CONFIG_TSEC_ENET)
 648 #define CONFIG_HAS_ETH0
 649 #define CONFIG_HAS_ETH1
 650 #define CONFIG_HAS_ETH2
 651 #endif
 652
 653 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 654 #define CONFIG_BOOTFILE         "uImage"
 655 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 656
 657 /* default location for tftp and bootm */
 658 #define CONFIG_LOADADDR         1000000
 659
 660 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 661         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 662         "netdev=eth0\0"                                         \
 663         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 664         "loadaddr=1000000\0"                    \
 665         "consoledev=ttyS0\0"                            \
 666         "ramdiskaddr=2000000\0"                 \
 667         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 668         "fdtaddr=1e00000\0"                             \
 669         "fdtfile=p1010rdb.dtb\0"                \
 670         "bdev=sda1\0"   \
 671         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 672         "othbootargs=ramdisk_size=600000\0" \
 673         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 674         "console=$consoledev,$baudrate $othbootargs; "  \
 675         "usb start;"                    \
 676         "fatload usb 0:2 $loadaddr $bootfile;"          \
 677         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 678         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 679         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 680         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 681         "console=$consoledev,$baudrate $othbootargs; "  \
 682         "usb start;"                    \
 683         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 684         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 685         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 686         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 687         CONFIG_BOOTMODE
 688
 689 #if defined(CONFIG_TARGET_P1010RDB_PA)
 690 #define CONFIG_BOOTMODE \
 691         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 692         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 693         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 694         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 695         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 696         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 697
 698 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 699 #define CONFIG_BOOTMODE \
 700         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 701         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 702         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 703         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 704         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 705         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 706         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 707         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 708         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 709         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 710 #endif
 711
 712 #define CONFIG_RAMBOOTCOMMAND           \
 713         "setenv bootargs root=/dev/ram rw "     \
 714         "console=$consoledev,$baudrate $othbootargs; "  \
 715         "tftp $ramdiskaddr $ramdiskfile;"       \
 716         "tftp $loadaddr $bootfile;"             \
 717         "tftp $fdtaddr $fdtfile;"               \
 718         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 719
 720 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 721
 722 #include <asm/fsl_secure_boot.h>
 723
 724 #endif  /* __CONFIG_H */