include/configs/P1010RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  20 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  21 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  22 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  23 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  24 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  25 #ifdef CONFIG_SPL_BUILD
  26 #define CONFIG_SPL_COMMON_INIT_DDR
  27 #endif
  28 #endif
  29
  30 #ifdef CONFIG_SPIFLASH
  31 #ifdef CONFIG_NXP_ESBC
  32 #define CONFIG_RAMBOOT_SPIFLASH
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  34 #else
  35 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  36 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  42 #ifdef CONFIG_SPL_BUILD
  43 #define CONFIG_SPL_COMMON_INIT_DDR
  44 #endif
  45 #endif
  46 #endif
  47
  48 #ifdef CONFIG_MTD_RAW_NAND
  49 #ifdef CONFIG_NXP_ESBC
  50 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  51
  52 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  53 #define CONFIG_SPL_RELOC_STACK          0x00100000
  54 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  55 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  56 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  57 #else
  58 #ifdef CONFIG_TPL_BUILD
  59 #define CONFIG_SPL_NAND_INIT
  60 #define CONFIG_SPL_COMMON_INIT_DDR
  61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  62 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
  63 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  64 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  65 #elif defined(CONFIG_SPL_BUILD)
  66 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  67 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
  68 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
  69 #else
  70 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  72 #endif
  73 #endif
  74 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  75 #endif
  76 #endif
  77
  78 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
  79 #define CONFIG_RAMBOOT_NAND
  80 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  81 #endif
  82
  83 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  84 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  85 #endif
  86
  87 /* High Level Configuration Options */
  88
  89 #if defined(CONFIG_PCI)
  90 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  91 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
  92
  93 /*
  94  * PCI Windows
  95  * Memory space is mapped 1-1, but I/O space must start from 0.
  96  */
  97 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  98 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
  99 #ifdef CONFIG_PHYS_64BIT
 100 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 101 #else
 102 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 103 #endif
 104 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 105 #ifdef CONFIG_PHYS_64BIT
 106 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 107 #else
 108 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 109 #endif
 110
 111 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 112 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 113 #ifdef CONFIG_PHYS_64BIT
 114 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 115 #else
 116 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 117 #endif
 118 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 119 #ifdef CONFIG_PHYS_64BIT
 120 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 121 #else
 122 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 123 #endif
 124
 125 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 126 #endif
 127
 128 #define CONFIG_HWCONFIG
 129 /*
 130  * These can be toggled for performance analysis, otherwise use default.
 131  */
 132 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 133
 134
 135 #define CONFIG_ENABLE_36BIT_PHYS
 136
 137 /* DDR Setup */
 138 #define CONFIG_SYS_DDR_RAW_TIMING
 139 #define CONFIG_SYS_SPD_BUS_NUM          1
 140 #define SPD_EEPROM_ADDRESS              0x52
 141
 142 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 143
 144 #ifndef __ASSEMBLY__
 145 extern unsigned long get_sdram_size(void);
 146 #endif
 147 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 148 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 149 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 150
 151 /* DDR3 Controller Settings */
 152 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 153 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 154 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 155 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 156 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 157 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 158 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 159 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 160 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 161 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 162 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 163 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 164 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 165 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 166 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 167
 168 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 169 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 170 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 171 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 172 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 173 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 174 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 175 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 176 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 177
 178 /* settings for DDR3 at 667MT/s */
 179 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 180 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 181 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 182 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 183 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 184 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 185 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 186 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 187 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 188
 189 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 190 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 191
 192 /* Don't relocate CCSRBAR while in NAND_SPL */
 193 #ifdef CONFIG_SPL_BUILD
 194 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 195 #endif
 196
 197 /*
 198  * Memory map
 199  *
 200  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 201  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 202  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 203  *
 204  * Localbus non-cacheable
 205  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 206  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 207  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 208  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 209  */
 210
 211 /*
 212  * IFC Definitions
 213  */
 214 /* NOR Flash on IFC */
 215
 216 #define CONFIG_SYS_FLASH_BASE           0xee000000
 217 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 218
 219 #ifdef CONFIG_PHYS_64BIT
 220 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 221 #else
 222 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 223 #endif
 224
 225 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 226                                 CSPR_PORT_SIZE_16 | \
 227                                 CSPR_MSEL_NOR | \
 228                                 CSPR_V)
 229 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 230 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 231 /* NOR Flash Timing Params */
 232 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 233                                 FTIM0_NOR_TEADC(0x5) | \
 234                                 FTIM0_NOR_TEAHC(0x5)
 235 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 236                                 FTIM1_NOR_TRAD_NOR(0x0f)
 237 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 238                                 FTIM2_NOR_TCH(0x4) | \
 239                                 FTIM2_NOR_TWP(0x1c)
 240 #define CONFIG_SYS_NOR_FTIM3    0x0
 241
 242 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 243 #define CONFIG_SYS_FLASH_QUIET_TEST
 244 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 245
 246 #undef CONFIG_SYS_FLASH_CHECKSUM
 247 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 248 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 249
 250 /* CFI for NOR Flash */
 251 #define CONFIG_SYS_FLASH_EMPTY_INFO
 252
 253 /* NAND Flash on IFC */
 254 #define CONFIG_SYS_NAND_BASE            0xff800000
 255 #ifdef CONFIG_PHYS_64BIT
 256 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 257 #else
 258 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 259 #endif
 260
 261 #define CONFIG_MTD_PARTITION
 262
 263 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 264                                 | CSPR_PORT_SIZE_8      \
 265                                 | CSPR_MSEL_NAND        \
 266                                 | CSPR_V)
 267 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 268
 269 #if defined(CONFIG_TARGET_P1010RDB_PA)
 270 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 271                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 272                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 273                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 274                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 275                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 276                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 277
 278 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 279 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 280                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 281                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 282                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 283                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 284                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 285                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 286 #endif
 287
 288 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 289 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 290
 291 #if defined(CONFIG_TARGET_P1010RDB_PA)
 292 /* NAND Flash Timing Params */
 293 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 294                                         FTIM0_NAND_TWP(0x0C)   | \
 295                                         FTIM0_NAND_TWCHT(0x04) | \
 296                                         FTIM0_NAND_TWH(0x05)
 297 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 298                                         FTIM1_NAND_TWBE(0x1d)  | \
 299                                         FTIM1_NAND_TRR(0x07)   | \
 300                                         FTIM1_NAND_TRP(0x0c)
 301 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 302                                         FTIM2_NAND_TREH(0x05) | \
 303                                         FTIM2_NAND_TWHRE(0x0f)
 304 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 305
 306 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 307 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 308 /* ONFI NAND Flash mode0 Timing Params */
 309 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 310                                         FTIM0_NAND_TWP(0x18)   | \
 311                                         FTIM0_NAND_TWCHT(0x07) | \
 312                                         FTIM0_NAND_TWH(0x0a))
 313 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 314                                         FTIM1_NAND_TWBE(0x39)  | \
 315                                         FTIM1_NAND_TRR(0x0e)   | \
 316                                         FTIM1_NAND_TRP(0x18))
 317 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 318                                         FTIM2_NAND_TREH(0x0a)  | \
 319                                         FTIM2_NAND_TWHRE(0x1e))
 320 #define CONFIG_SYS_NAND_FTIM3   0x0
 321 #endif
 322
 323 #define CONFIG_SYS_NAND_DDR_LAW         11
 324
 325 /* Set up IFC registers for boot location NOR/NAND */
 326 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 327 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 328 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 329 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 330 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 331 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 332 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 333 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 334 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 335 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 336 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 337 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 338 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 339 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 340 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 341 #else
 342 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 343 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 344 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 345 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 346 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 347 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 348 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 349 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 350 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 351 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 352 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 353 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 354 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 355 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 356 #endif
 357
 358 /* CPLD on IFC */
 359 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 360
 361 #ifdef CONFIG_PHYS_64BIT
 362 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 363 #else
 364 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 365 #endif
 366
 367 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 368                                 | CSPR_PORT_SIZE_8 \
 369                                 | CSPR_MSEL_GPCM \
 370                                 | CSPR_V)
 371 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 372 #define CONFIG_SYS_CSOR3                0x0
 373 /* CPLD Timing parameters for IFC CS3 */
 374 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 375                                         FTIM0_GPCM_TEADC(0x0e) | \
 376                                         FTIM0_GPCM_TEAHC(0x0e))
 377 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 378                                         FTIM1_GPCM_TRAD(0x1f))
 379 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 380                                         FTIM2_GPCM_TCH(0x8) | \
 381                                         FTIM2_GPCM_TWP(0x1f))
 382 #define CONFIG_SYS_CS3_FTIM3            0x0
 383
 384 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 385         defined(CONFIG_RAMBOOT_NAND)
 386 #define CONFIG_SYS_RAMBOOT
 387 #else
 388 #undef CONFIG_SYS_RAMBOOT
 389 #endif
 390
 391 #define CONFIG_SYS_INIT_RAM_LOCK
 392 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 393 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 394
 395 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 396                                                 - GENERATED_GBL_DATA_SIZE)
 397 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 398
 399 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 400
 401 /*
 402  * Config the L2 Cache as L2 SRAM
 403  */
 404 #if defined(CONFIG_SPL_BUILD)
 405 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 406 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 407 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 408 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 409 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 410 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 411 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 412 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 413 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 414 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 415 #elif defined(CONFIG_MTD_RAW_NAND)
 416 #ifdef CONFIG_TPL_BUILD
 417 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 418 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 419 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 420 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 421 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 422 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 423 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 424 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 425 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 426 #else
 427 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 428 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 429 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 430 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 431 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 432 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 433 #endif
 434 #endif
 435 #endif
 436
 437 /* Serial Port */
 438 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 439 #define CONFIG_SYS_NS16550_SERIAL
 440 #define CONFIG_SYS_NS16550_REG_SIZE     1
 441 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 442 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
 443 #define CONFIG_NS16550_MIN_FUNCTIONS
 444 #endif
 445
 446 #define CONFIG_SYS_BAUDRATE_TABLE       \
 447         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 448
 449 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 450 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 451
 452 /* I2C */
 453 #define I2C_PCA9557_ADDR1               0x18
 454 #define I2C_PCA9557_ADDR2               0x19
 455 #define I2C_PCA9557_BUS_NUM             0
 456
 457 /* I2C EEPROM */
 458 #if defined(CONFIG_TARGET_P1010RDB_PB)
 459 #ifdef CONFIG_ID_EEPROM
 460 #define CONFIG_SYS_I2C_EEPROM_NXID
 461 #endif
 462 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 463 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 464 #endif
 465 /* enable read and write access to EEPROM */
 466
 467 /* RTC */
 468 #define CONFIG_RTC_PT7C4338
 469 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 470
 471 /*
 472  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 473  * used for SLIC
 474  */
 475 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 476 /* eSPI - Enhanced SPI */
 477 #endif
 478
 479 #if defined(CONFIG_TSEC_ENET)
 480 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 481 #define CONFIG_TSEC1    1
 482 #define CONFIG_TSEC1_NAME       "eTSEC1"
 483 #define CONFIG_TSEC2    1
 484 #define CONFIG_TSEC2_NAME       "eTSEC2"
 485 #define CONFIG_TSEC3    1
 486 #define CONFIG_TSEC3_NAME       "eTSEC3"
 487
 488 #define TSEC1_PHY_ADDR          1
 489 #define TSEC2_PHY_ADDR          0
 490 #define TSEC3_PHY_ADDR          2
 491
 492 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 493 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 494 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 495
 496 #define TSEC1_PHYIDX            0
 497 #define TSEC2_PHYIDX            0
 498 #define TSEC3_PHYIDX            0
 499
 500 /* TBI PHY configuration for SGMII mode */
 501 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 502                 TBICR_PHY_RESET \
 503                 | TBICR_ANEG_ENABLE \
 504                 | TBICR_FULL_DUPLEX \
 505                 | TBICR_SPEED1_SET \
 506                 )
 507
 508 #endif  /* CONFIG_TSEC_ENET */
 509
 510 /* SATA */
 511 #define CONFIG_FSL_SATA_V2
 512
 513 #ifdef CONFIG_FSL_SATA
 514 #define CONFIG_SATA1
 515 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 516 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 517 #define CONFIG_SATA2
 518 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 519 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 520
 521 #define CONFIG_LBA48
 522 #endif /* #ifdef CONFIG_FSL_SATA  */
 523
 524 #ifdef CONFIG_MMC
 525 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 526 #endif
 527
 528 #define CONFIG_HAS_FSL_DR_USB
 529
 530 #if defined(CONFIG_HAS_FSL_DR_USB)
 531 #ifdef CONFIG_USB_EHCI_HCD
 532 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 533 #endif
 534 #endif
 535
 536 /*
 537  * Environment
 538  */
 539 #if defined(CONFIG_SDCARD)
 540 #define CONFIG_FSL_FIXED_MMC_LOCATION
 541 #elif defined(CONFIG_MTD_RAW_NAND)
 542 #ifdef CONFIG_TPL_BUILD
 543 #define SPL_ENV_ADDR            (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 544 #else
 545 #if defined(CONFIG_TARGET_P1010RDB_PA)
 546 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 547 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 548 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 549 #endif
 550 #endif
 551 #endif
 552
 553 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 554 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 555
 556 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
 557                  || defined(CONFIG_FSL_SATA)
 558 #endif
 559
 560 /*
 561  * Miscellaneous configurable options
 562  */
 563
 564 /*
 565  * For booting Linux, the board info and command line data
 566  * have to be in the first 64 MB of memory, since this is
 567  * the maximum mapped by the Linux kernel during initialization.
 568  */
 569 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 570 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 571
 572 /*
 573  * Environment Configuration
 574  */
 575
 576 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 577 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 578
 579 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 580         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 581         "netdev=eth0\0"                                         \
 582         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 583         "loadaddr=1000000\0"                    \
 584         "consoledev=ttyS0\0"                            \
 585         "ramdiskaddr=2000000\0"                 \
 586         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 587         "fdtaddr=1e00000\0"                             \
 588         "fdtfile=p1010rdb.dtb\0"                \
 589         "bdev=sda1\0"   \
 590         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 591         "othbootargs=ramdisk_size=600000\0" \
 592         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 593         "console=$consoledev,$baudrate $othbootargs; "  \
 594         "usb start;"                    \
 595         "fatload usb 0:2 $loadaddr $bootfile;"          \
 596         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 597         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 598         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 599         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 600         "console=$consoledev,$baudrate $othbootargs; "  \
 601         "usb start;"                    \
 602         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 603         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 604         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 605         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 606         BOOTMODE
 607
 608 #if defined(CONFIG_TARGET_P1010RDB_PA)
 609 #define BOOTMODE \
 610         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 611         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 612         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 613         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 614         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 615         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 616
 617 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 618 #define BOOTMODE \
 619         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 620         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 621         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 622         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 623         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 624         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 625         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 626         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 627         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 628         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 629 #endif
 630
 631 #include <asm/fsl_secure_boot.h>
 632
 633 #endif  /* __CONFIG_H */