configs: Finish migration of PHY_GIGE
[platform/kernel/u-boot.git] / include / configs / P1010RDB.h
1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * P010 RDB board configuration file
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #include <asm/config_mpc85xx.h>
15 #define CONFIG_NAND_FSL_IFC
16
17 #ifdef CONFIG_SDCARD
18 #define CONFIG_SPL_MMC_MINIMAL
19 #define CONFIG_SPL_FLUSH_IMAGE
20 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
21 #define CONFIG_SYS_TEXT_BASE            0x11001000
22 #define CONFIG_SPL_TEXT_BASE            0xD0001000
23 #define CONFIG_SPL_PAD_TO               0x18000
24 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
25 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
26 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
27 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
28 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
30 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
31 #define CONFIG_SPL_MMC_BOOT
32 #ifdef CONFIG_SPL_BUILD
33 #define CONFIG_SPL_COMMON_INIT_DDR
34 #endif
35 #endif
36
37 #ifdef CONFIG_SPIFLASH
38 #ifdef CONFIG_SECURE_BOOT
39 #define CONFIG_RAMBOOT_SPIFLASH
40 #define CONFIG_SYS_TEXT_BASE            0x11000000
41 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
42 #else
43 #define CONFIG_SPL_SPI_FLASH_MINIMAL
44 #define CONFIG_SPL_FLUSH_IMAGE
45 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
46 #define CONFIG_SYS_TEXT_BASE                    0x11001000
47 #define CONFIG_SPL_TEXT_BASE                    0xD0001000
48 #define CONFIG_SPL_PAD_TO                       0x18000
49 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
55 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
56 #define CONFIG_SPL_SPI_BOOT
57 #ifdef CONFIG_SPL_BUILD
58 #define CONFIG_SPL_COMMON_INIT_DDR
59 #endif
60 #endif
61 #endif
62
63 #ifdef CONFIG_NAND
64 #ifdef CONFIG_SECURE_BOOT
65 #define CONFIG_SPL_INIT_MINIMAL
66 #define CONFIG_SPL_NAND_BOOT
67 #define CONFIG_SPL_FLUSH_IMAGE
68 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
69
70 #define CONFIG_SYS_TEXT_BASE            0x00201000
71 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
72 #define CONFIG_SPL_MAX_SIZE             8192
73 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
74 #define CONFIG_SPL_RELOC_STACK          0x00100000
75 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
76 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
77 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
78 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
79 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
80 #else
81 #ifdef CONFIG_TPL_BUILD
82 #define CONFIG_SPL_NAND_BOOT
83 #define CONFIG_SPL_FLUSH_IMAGE
84 #define CONFIG_SPL_NAND_INIT
85 #define CONFIG_SPL_COMMON_INIT_DDR
86 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
87 #define CONFIG_SPL_TEXT_BASE            0xD0001000
88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
89 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
90 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
91 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
92 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
93 #elif defined(CONFIG_SPL_BUILD)
94 #define CONFIG_SPL_INIT_MINIMAL
95 #define CONFIG_SPL_NAND_MINIMAL
96 #define CONFIG_SPL_FLUSH_IMAGE
97 #define CONFIG_SPL_TEXT_BASE            0xff800000
98 #define CONFIG_SPL_MAX_SIZE             8192
99 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
100 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
101 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
102 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
103 #endif
104 #define CONFIG_SPL_PAD_TO       0x20000
105 #define CONFIG_TPL_PAD_TO       0x20000
106 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
107 #define CONFIG_SYS_TEXT_BASE    0x11001000
108 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
109 #endif
110 #endif
111
112 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
113 #define CONFIG_RAMBOOT_NAND
114 #define CONFIG_SYS_TEXT_BASE            0x11000000
115 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
116 #endif
117
118 #ifndef CONFIG_SYS_TEXT_BASE
119 #define CONFIG_SYS_TEXT_BASE            0xeff40000
120 #endif
121
122 #ifndef CONFIG_RESET_VECTOR_ADDRESS
123 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
124 #endif
125
126 #ifdef CONFIG_SPL_BUILD
127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
128 #else
129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
130 #endif
131
132 /* High Level Configuration Options */
133 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
134
135 #if defined(CONFIG_PCI)
136 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
137 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
138 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
139 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
140 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
141 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
142
143 #define CONFIG_CMD_PCI
144
145 /*
146  * PCI Windows
147  * Memory space is mapped 1-1, but I/O space must start from 0.
148  */
149 /* controller 1, Slot 1, tgtid 1, Base address a000 */
150 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
151 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
152 #ifdef CONFIG_PHYS_64BIT
153 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
154 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
155 #else
156 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
157 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
158 #endif
159 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
160 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
161 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
162 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
163 #ifdef CONFIG_PHYS_64BIT
164 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
165 #else
166 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
167 #endif
168
169 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
170 #if defined(CONFIG_TARGET_P1010RDB_PA)
171 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
172 #elif defined(CONFIG_TARGET_P1010RDB_PB)
173 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
174 #endif
175 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
176 #ifdef CONFIG_PHYS_64BIT
177 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
178 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
179 #else
180 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
181 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
182 #endif
183 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
184 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
185 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
186 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
187 #ifdef CONFIG_PHYS_64BIT
188 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
189 #else
190 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
191 #endif
192
193 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
194 #endif
195
196 #define CONFIG_TSEC_ENET
197 #define CONFIG_ENV_OVERWRITE
198
199 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
200 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
201
202 #define CONFIG_MISC_INIT_R
203 #define CONFIG_HWCONFIG
204 /*
205  * These can be toggled for performance analysis, otherwise use default.
206  */
207 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
208 #define CONFIG_BTB                      /* toggle branch predition */
209
210 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
211
212 #define CONFIG_ENABLE_36BIT_PHYS
213
214 #ifdef CONFIG_PHYS_64BIT
215 #define CONFIG_ADDR_MAP                 1
216 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
217 #endif
218
219 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
220 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
221 #define CONFIG_PANIC_HANG               /* do not reset board on panic */
222
223 /* DDR Setup */
224 #define CONFIG_SYS_DDR_RAW_TIMING
225 #define CONFIG_DDR_SPD
226 #define CONFIG_SYS_SPD_BUS_NUM          1
227 #define SPD_EEPROM_ADDRESS              0x52
228
229 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
230
231 #ifndef __ASSEMBLY__
232 extern unsigned long get_sdram_size(void);
233 #endif
234 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
235 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
236 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
237
238 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
239 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
240
241 /* DDR3 Controller Settings */
242 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
243 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
244 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
245 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
246 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
247 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
248 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
249 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
250 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
251 #define CONFIG_SYS_DDR_RCW_1            0x00000000
252 #define CONFIG_SYS_DDR_RCW_2            0x00000000
253 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
254 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
255 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
256 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
257
258 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
259 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
260 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
261 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
262 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
263 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
264 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
265 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
266 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
267
268 /* settings for DDR3 at 667MT/s */
269 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
270 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
271 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
272 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
273 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
274 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
275 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
276 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
277 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
278
279 #define CONFIG_SYS_CCSRBAR                      0xffe00000
280 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
281
282 /* Don't relocate CCSRBAR while in NAND_SPL */
283 #ifdef CONFIG_SPL_BUILD
284 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
285 #endif
286
287 /*
288  * Memory map
289  *
290  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
291  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
292  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
293  *
294  * Localbus non-cacheable
295  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
296  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
297  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
298  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
299  */
300
301 /*
302  * IFC Definitions
303  */
304 /* NOR Flash on IFC */
305
306 #define CONFIG_SYS_FLASH_BASE           0xee000000
307 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
308
309 #ifdef CONFIG_PHYS_64BIT
310 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
311 #else
312 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
313 #endif
314
315 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
316                                 CSPR_PORT_SIZE_16 | \
317                                 CSPR_MSEL_NOR | \
318                                 CSPR_V)
319 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
320 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
321 /* NOR Flash Timing Params */
322 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
323                                 FTIM0_NOR_TEADC(0x5) | \
324                                 FTIM0_NOR_TEAHC(0x5)
325 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
326                                 FTIM1_NOR_TRAD_NOR(0x0f)
327 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
328                                 FTIM2_NOR_TCH(0x4) | \
329                                 FTIM2_NOR_TWP(0x1c)
330 #define CONFIG_SYS_NOR_FTIM3    0x0
331
332 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
333 #define CONFIG_SYS_FLASH_QUIET_TEST
334 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
335 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
336
337 #undef CONFIG_SYS_FLASH_CHECKSUM
338 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
339 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
340
341 /* CFI for NOR Flash */
342 #define CONFIG_FLASH_CFI_DRIVER
343 #define CONFIG_SYS_FLASH_CFI
344 #define CONFIG_SYS_FLASH_EMPTY_INFO
345 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
346
347 /* NAND Flash on IFC */
348 #define CONFIG_SYS_NAND_BASE            0xff800000
349 #ifdef CONFIG_PHYS_64BIT
350 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
351 #else
352 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
353 #endif
354
355 #define CONFIG_MTD_DEVICE
356 #define CONFIG_MTD_PARTITION
357 #define MTDIDS_DEFAULT                  "nand0=ff800000.flash"
358 #define MTDPARTS_DEFAULT                \
359         "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
360
361 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
362                                 | CSPR_PORT_SIZE_8      \
363                                 | CSPR_MSEL_NAND        \
364                                 | CSPR_V)
365 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
366
367 #if defined(CONFIG_TARGET_P1010RDB_PA)
368 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
369                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
370                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
371                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
372                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
373                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
374                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
375 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
376
377 #elif defined(CONFIG_TARGET_P1010RDB_PB)
378 #define CONFIG_SYS_NAND_ONFI_DETECTION
379 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
380                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
381                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
382                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
383                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
384                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
385                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
386 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
387 #endif
388
389 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
390 #define CONFIG_SYS_MAX_NAND_DEVICE      1
391
392 #if defined(CONFIG_TARGET_P1010RDB_PA)
393 /* NAND Flash Timing Params */
394 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
395                                         FTIM0_NAND_TWP(0x0C)   | \
396                                         FTIM0_NAND_TWCHT(0x04) | \
397                                         FTIM0_NAND_TWH(0x05)
398 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
399                                         FTIM1_NAND_TWBE(0x1d)  | \
400                                         FTIM1_NAND_TRR(0x07)   | \
401                                         FTIM1_NAND_TRP(0x0c)
402 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
403                                         FTIM2_NAND_TREH(0x05) | \
404                                         FTIM2_NAND_TWHRE(0x0f)
405 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
406
407 #elif defined(CONFIG_TARGET_P1010RDB_PB)
408 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
409 /* ONFI NAND Flash mode0 Timing Params */
410 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
411                                         FTIM0_NAND_TWP(0x18)   | \
412                                         FTIM0_NAND_TWCHT(0x07) | \
413                                         FTIM0_NAND_TWH(0x0a))
414 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
415                                         FTIM1_NAND_TWBE(0x39)  | \
416                                         FTIM1_NAND_TRR(0x0e)   | \
417                                         FTIM1_NAND_TRP(0x18))
418 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
419                                         FTIM2_NAND_TREH(0x0a)  | \
420                                         FTIM2_NAND_TWHRE(0x1e))
421 #define CONFIG_SYS_NAND_FTIM3   0x0
422 #endif
423
424 #define CONFIG_SYS_NAND_DDR_LAW         11
425
426 /* Set up IFC registers for boot location NOR/NAND */
427 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
428 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
429 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
430 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
431 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
432 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
433 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
434 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
435 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
436 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
437 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
438 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
439 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
440 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
441 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
442 #else
443 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
444 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
445 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
446 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
447 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
448 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
449 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
450 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
451 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
452 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
453 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
454 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
455 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
456 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
457 #endif
458
459 /* CPLD on IFC */
460 #define CONFIG_SYS_CPLD_BASE            0xffb00000
461
462 #ifdef CONFIG_PHYS_64BIT
463 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
464 #else
465 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
466 #endif
467
468 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
469                                 | CSPR_PORT_SIZE_8 \
470                                 | CSPR_MSEL_GPCM \
471                                 | CSPR_V)
472 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
473 #define CONFIG_SYS_CSOR3                0x0
474 /* CPLD Timing parameters for IFC CS3 */
475 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
476                                         FTIM0_GPCM_TEADC(0x0e) | \
477                                         FTIM0_GPCM_TEAHC(0x0e))
478 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
479                                         FTIM1_GPCM_TRAD(0x1f))
480 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
481                                         FTIM2_GPCM_TCH(0x8) | \
482                                         FTIM2_GPCM_TWP(0x1f))
483 #define CONFIG_SYS_CS3_FTIM3            0x0
484
485 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
486         defined(CONFIG_RAMBOOT_NAND)
487 #define CONFIG_SYS_RAMBOOT
488 #define CONFIG_SYS_EXTRA_ENV_RELOC
489 #else
490 #undef CONFIG_SYS_RAMBOOT
491 #endif
492
493 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
494 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
495 #define CONFIG_A003399_NOR_WORKAROUND
496 #endif
497 #endif
498
499 #define CONFIG_BOARD_EARLY_INIT_R
500
501 #define CONFIG_SYS_INIT_RAM_LOCK
502 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
503 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
504
505 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
506                                                 - GENERATED_GBL_DATA_SIZE)
507 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
508
509 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
510 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
511
512 /*
513  * Config the L2 Cache as L2 SRAM
514  */
515 #if defined(CONFIG_SPL_BUILD)
516 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
517 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
518 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
519 #define CONFIG_SYS_L2_SIZE              (256 << 10)
520 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
521 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
522 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
523 #define CONFIG_SPL_RELOC_STACK_SIZE     (16 << 10)
524 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
525 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
526 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
527 #elif defined(CONFIG_NAND)
528 #ifdef CONFIG_TPL_BUILD
529 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
530 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
531 #define CONFIG_SYS_L2_SIZE              (256 << 10)
532 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
533 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
534 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
535 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
536 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
537 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
538 #else
539 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
540 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
541 #define CONFIG_SYS_L2_SIZE              (256 << 10)
542 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
543 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
544 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
545 #endif
546 #endif
547 #endif
548
549 /* Serial Port */
550 #define CONFIG_CONS_INDEX       1
551 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
552 #define CONFIG_SYS_NS16550_SERIAL
553 #define CONFIG_SYS_NS16550_REG_SIZE     1
554 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
555 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
556 #define CONFIG_NS16550_MIN_FUNCTIONS
557 #endif
558
559 #define CONFIG_SYS_BAUDRATE_TABLE       \
560         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
561
562 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
563 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
564
565 /* I2C */
566 #define CONFIG_SYS_I2C
567 #define CONFIG_SYS_I2C_FSL
568 #define CONFIG_SYS_FSL_I2C_SPEED        400000
569 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
570 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
571 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
572 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
573 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
574 #define I2C_PCA9557_ADDR1               0x18
575 #define I2C_PCA9557_ADDR2               0x19
576 #define I2C_PCA9557_BUS_NUM             0
577
578 /* I2C EEPROM */
579 #if defined(CONFIG_TARGET_P1010RDB_PB)
580 #define CONFIG_ID_EEPROM
581 #ifdef CONFIG_ID_EEPROM
582 #define CONFIG_SYS_I2C_EEPROM_NXID
583 #endif
584 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
585 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
586 #define CONFIG_SYS_EEPROM_BUS_NUM       0
587 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
588 #endif
589 /* enable read and write access to EEPROM */
590 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
591 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
592 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
593
594 /* RTC */
595 #define CONFIG_RTC_PT7C4338
596 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
597
598 /*
599  * SPI interface will not be available in case of NAND boot SPI CS0 will be
600  * used for SLIC
601  */
602 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
603 /* eSPI - Enhanced SPI */
604 #define CONFIG_SF_DEFAULT_SPEED         10000000
605 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
606 #endif
607
608 #if defined(CONFIG_TSEC_ENET)
609 #define CONFIG_MII                      /* MII PHY management */
610 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
611 #define CONFIG_TSEC1    1
612 #define CONFIG_TSEC1_NAME       "eTSEC1"
613 #define CONFIG_TSEC2    1
614 #define CONFIG_TSEC2_NAME       "eTSEC2"
615 #define CONFIG_TSEC3    1
616 #define CONFIG_TSEC3_NAME       "eTSEC3"
617
618 #define TSEC1_PHY_ADDR          1
619 #define TSEC2_PHY_ADDR          0
620 #define TSEC3_PHY_ADDR          2
621
622 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
623 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
624 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
625
626 #define TSEC1_PHYIDX            0
627 #define TSEC2_PHYIDX            0
628 #define TSEC3_PHYIDX            0
629
630 #define CONFIG_ETHPRIME         "eTSEC1"
631
632 /* TBI PHY configuration for SGMII mode */
633 #define CONFIG_TSEC_TBICR_SETTINGS ( \
634                 TBICR_PHY_RESET \
635                 | TBICR_ANEG_ENABLE \
636                 | TBICR_FULL_DUPLEX \
637                 | TBICR_SPEED1_SET \
638                 )
639
640 #endif  /* CONFIG_TSEC_ENET */
641
642 /* SATA */
643 #define CONFIG_FSL_SATA
644 #define CONFIG_FSL_SATA_V2
645 #define CONFIG_LIBATA
646
647 #ifdef CONFIG_FSL_SATA
648 #define CONFIG_SYS_SATA_MAX_DEVICE      2
649 #define CONFIG_SATA1
650 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
651 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
652 #define CONFIG_SATA2
653 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
654 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
655
656 #define CONFIG_LBA48
657 #endif /* #ifdef CONFIG_FSL_SATA  */
658
659 #ifdef CONFIG_MMC
660 #define CONFIG_FSL_ESDHC
661 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
662 #endif
663
664 #define CONFIG_HAS_FSL_DR_USB
665
666 #if defined(CONFIG_HAS_FSL_DR_USB)
667 #ifdef CONFIG_USB_EHCI_HCD
668 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
669 #define CONFIG_USB_EHCI_FSL
670 #endif
671 #endif
672
673 /*
674  * Environment
675  */
676 #if defined(CONFIG_SDCARD)
677 #define CONFIG_FSL_FIXED_MMC_LOCATION
678 #define CONFIG_SYS_MMC_ENV_DEV          0
679 #define CONFIG_ENV_SIZE                 0x2000
680 #elif defined(CONFIG_SPIFLASH)
681 #define CONFIG_ENV_SPI_BUS      0
682 #define CONFIG_ENV_SPI_CS       0
683 #define CONFIG_ENV_SPI_MAX_HZ   10000000
684 #define CONFIG_ENV_SPI_MODE     0
685 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
686 #define CONFIG_ENV_SECT_SIZE    0x10000
687 #define CONFIG_ENV_SIZE         0x2000
688 #elif defined(CONFIG_NAND)
689 #ifdef CONFIG_TPL_BUILD
690 #define CONFIG_ENV_SIZE         0x2000
691 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
692 #else
693 #if defined(CONFIG_TARGET_P1010RDB_PA)
694 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
695 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
696 #elif defined(CONFIG_TARGET_P1010RDB_PB)
697 #define CONFIG_ENV_SIZE         (16 * 1024)
698 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
699 #endif
700 #endif
701 #define CONFIG_ENV_OFFSET       (1024 * 1024)
702 #elif defined(CONFIG_SYS_RAMBOOT)
703 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
704 #define CONFIG_ENV_SIZE                 0x2000
705 #else
706 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
707 #define CONFIG_ENV_SIZE         0x2000
708 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
709 #endif
710
711 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
712 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
713
714 /*
715  * Command line configuration.
716  */
717 #define CONFIG_CMD_REGINFO
718
719 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
720
721 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
722                  || defined(CONFIG_FSL_SATA)
723 #endif
724
725 /*
726  * Miscellaneous configurable options
727  */
728 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
729 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
730 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
731 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
732
733 #if defined(CONFIG_CMD_KGDB)
734 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
735 #else
736 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
737 #endif
738 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
739                                                 /* Print Buffer Size */
740 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
741 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
742
743 /*
744  * For booting Linux, the board info and command line data
745  * have to be in the first 64 MB of memory, since this is
746  * the maximum mapped by the Linux kernel during initialization.
747  */
748 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
749 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
750
751 #if defined(CONFIG_CMD_KGDB)
752 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
753 #endif
754
755 /*
756  * Environment Configuration
757  */
758
759 #if defined(CONFIG_TSEC_ENET)
760 #define CONFIG_HAS_ETH0
761 #define CONFIG_HAS_ETH1
762 #define CONFIG_HAS_ETH2
763 #endif
764
765 #define CONFIG_ROOTPATH         "/opt/nfsroot"
766 #define CONFIG_BOOTFILE         "uImage"
767 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
768
769 /* default location for tftp and bootm */
770 #define CONFIG_LOADADDR         1000000
771
772 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
773
774 #define CONFIG_EXTRA_ENV_SETTINGS                               \
775         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
776         "netdev=eth0\0"                                         \
777         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
778         "loadaddr=1000000\0"                    \
779         "consoledev=ttyS0\0"                            \
780         "ramdiskaddr=2000000\0"                 \
781         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
782         "fdtaddr=1e00000\0"                             \
783         "fdtfile=p1010rdb.dtb\0"                \
784         "bdev=sda1\0"   \
785         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
786         "othbootargs=ramdisk_size=600000\0" \
787         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
788         "console=$consoledev,$baudrate $othbootargs; "  \
789         "usb start;"                    \
790         "fatload usb 0:2 $loadaddr $bootfile;"          \
791         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
792         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
793         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
794         "usbext2boot=setenv bootargs root=/dev/ram rw " \
795         "console=$consoledev,$baudrate $othbootargs; "  \
796         "usb start;"                    \
797         "ext2load usb 0:4 $loadaddr $bootfile;"         \
798         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
799         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
800         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
801         CONFIG_BOOTMODE
802
803 #if defined(CONFIG_TARGET_P1010RDB_PA)
804 #define CONFIG_BOOTMODE \
805         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
806         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
807         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
808         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
809         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
810         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
811
812 #elif defined(CONFIG_TARGET_P1010RDB_PB)
813 #define CONFIG_BOOTMODE \
814         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
815         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
816         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
817         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
818         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
819         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
820         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
821         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
822         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
823         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
824 #endif
825
826 #define CONFIG_RAMBOOTCOMMAND           \
827         "setenv bootargs root=/dev/ram rw "     \
828         "console=$consoledev,$baudrate $othbootargs; "  \
829         "tftp $ramdiskaddr $ramdiskfile;"       \
830         "tftp $loadaddr $bootfile;"             \
831         "tftp $fdtaddr $fdtfile;"               \
832         "bootm $loadaddr $ramdiskaddr $fdtaddr"
833
834 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
835
836 #include <asm/fsl_secure_boot.h>
837
838 #endif  /* __CONFIG_H */