include/configs/MPC8641HPCN.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2006, 2010-2011 Freescale Semiconductor.
   4  *
   5  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   6  */
   7
   8 /*
   9  * MPC8641HPCN board configuration file
  10  *
  11  * Make sure you change the MAC address and other network params first,
  12  * search for CONFIG_SERVERIP, etc. in this file.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 #include <linux/stringify.h>
  19
  20 /* High Level Configuration Options */
  21 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  22
  23 /*
  24  * default CCSRBAR is at 0xff700000
  25  * assume U-Boot is less than 0.5MB
  26  */
  27
  28 #ifdef RUN_DIAG
  29 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  30 #endif
  31
  32 /*
  33  * virtual address to be used for temporary mappings.  There
  34  * should be 128k free at this VA.
  35  */
  36 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  37
  38 #define CONFIG_SYS_SRIO
  39 #define CONFIG_SRIO1                    /* SRIO port 1 */
  40
  41 #define CONFIG_PCIE1            1       /* PCIE controller 1 (ULI bridge) */
  42 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot) */
  43 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  44 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  45
  46 #define CONFIG_ENV_OVERWRITE
  47
  48 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  49
  50 #define CONFIG_ALTIVEC          1
  51
  52 /*
  53  * L2CR setup -- make sure this is right for your board!
  54  */
  55 #define CONFIG_SYS_L2
  56 #define L2_INIT         0
  57 #define L2_ENABLE       (L2CR_L2E)
  58
  59 #ifndef CONFIG_SYS_CLK_FREQ
  60 #ifndef __ASSEMBLY__
  61 extern unsigned long get_board_sys_clk(unsigned long dummy);
  62 #endif
  63 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  64 #endif
  65
  66 /*
  67  * With the exception of PCI Memory and Rapid IO, most devices will simply
  68  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  69  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  70  */
  71 #ifdef CONFIG_PHYS_64BIT
  72 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  73 #else
  74 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  75 #endif
  76
  77 /*
  78  * Base addresses -- Note these are effective addresses where the
  79  * actual resources get mapped (not physical addresses)
  80  */
  81 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  82 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  83
  84 /* Physical addresses */
  85 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  86 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    CONFIG_SYS_PHYS_ADDR_HIGH
  87 #define CONFIG_SYS_CCSRBAR_PHYS \
  88         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  89                             CONFIG_SYS_CCSRBAR_PHYS_HIGH)
  90
  91 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
  92
  93 /*
  94  * DDR Setup
  95  */
  96 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  97 #define CONFIG_DDR_SPD
  98
  99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 100 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 101
 102 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 103 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 104 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 105 #define CONFIG_VERY_BIG_RAM
 106
 107 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 108 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 109
 110 /*
 111  * I2C addresses of SPD EEPROMs
 112  */
 113 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 114 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 115 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 116 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 117
 118 /*
 119  * These are used when DDR doesn't use SPD.
 120  */
 121 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 122 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 123 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 124 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 125 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 126 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 127 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 128 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 129 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 130 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 131 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 132 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 133 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 134 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 135 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 136 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 137
 138 #define CONFIG_ID_EEPROM
 139 #define CONFIG_SYS_I2C_EEPROM_NXID
 140 #define CONFIG_ID_EEPROM
 141 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 142 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 143
 144 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 145 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW  CONFIG_SYS_FLASH_BASE
 146 #define CONFIG_SYS_FLASH_BASE_PHYS \
 147         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 148                             CONFIG_SYS_PHYS_ADDR_HIGH)
 149
 150 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 151
 152 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 153                                  | 0x00001001)  /* port size 16bit */
 154 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 155
 156 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 157                                  | 0x00001001)  /* port size 16bit */
 158 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 159
 160 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 161                                  | 0x00000801) /* port size 8bit */
 162 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 163
 164 /*
 165  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 166  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 167  * required for the smallest BAT mapping, so there's a 64k hole.
 168  */
 169 #define CONFIG_SYS_LBC_BASE             0xffde0000
 170 #define CONFIG_SYS_LBC_BASE_PHYS_LOW    CONFIG_SYS_LBC_BASE
 171
 172 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 173 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 174 #define PIXIS_BASE_PHYS_LOW     (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
 175 #define PIXIS_BASE_PHYS         PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
 176                                                     CONFIG_SYS_PHYS_ADDR_HIGH)
 177 #define PIXIS_SIZE              0x00008000      /* 32k */
 178 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 179 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 180 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 181 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 182 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 183 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 184 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 185 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 186 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 187 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 188 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 189 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 190 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 191 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 192 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 193 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 194 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 195
 196 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 197 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 198 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 199
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 201 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 202
 203 #undef  CONFIG_SYS_FLASH_CHECKSUM
 204 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 205 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 206 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 207 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 208
 209 #define CONFIG_SYS_FLASH_EMPTY_INFO
 210
 211 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 212 #define CONFIG_SYS_RAMBOOT
 213 #else
 214 #undef  CONFIG_SYS_RAMBOOT
 215 #endif
 216
 217 #if defined(CONFIG_SYS_RAMBOOT)
 218 #undef CONFIG_SPD_EEPROM
 219 #define CONFIG_SYS_SDRAM_SIZE   256
 220 #endif
 221
 222 #define CONFIG_SYS_INIT_RAM_LOCK        1
 223 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 224 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 225 #else
 226 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 227 #endif
 228 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 229
 230 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 231 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 232
 233 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Mon */
 234 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 235
 236 /* Serial Port */
 237 #define CONFIG_SYS_NS16550_SERIAL
 238 #define CONFIG_SYS_NS16550_REG_SIZE     1
 239 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 240
 241 #define CONFIG_SYS_BAUDRATE_TABLE  \
 242         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 243
 244 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 245 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 246
 247 /*
 248  * I2C
 249  */
 250 #define CONFIG_SYS_I2C
 251 #define CONFIG_SYS_I2C_FSL
 252 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 253 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 254 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 255 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 256
 257 /*
 258  * RapidIO MMU
 259  */
 260 #define CONFIG_SYS_SRIO1_MEM_BASE       0x80000000      /* base address */
 261 #ifdef CONFIG_PHYS_64BIT
 262 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   0x00000000
 263 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
 264 #else
 265 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   CONFIG_SYS_SRIO1_MEM_BASE
 266 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
 267 #endif
 268 #define CONFIG_SYS_SRIO1_MEM_PHYS \
 269         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 270                             CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
 271 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 128M */
 272
 273 /*
 274  * General PCI
 275  * Addresses are mapped 1-1.
 276  */
 277
 278 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 279 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 280 #ifdef CONFIG_PHYS_64BIT
 281 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 282 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   0x00000000
 283 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x0000000c
 284 #else
 285 #define CONFIG_SYS_PCIE1_MEM_BUS        CONFIG_SYS_PCIE1_MEM_VIRT
 286 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   CONFIG_SYS_PCIE1_MEM_VIRT
 287 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x00000000
 288 #endif
 289 #define CONFIG_SYS_PCIE1_MEM_PHYS \
 290         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 291                             CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
 292 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 293 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 294 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 295 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW    CONFIG_SYS_PCIE1_IO_VIRT
 296 #define CONFIG_SYS_PCIE1_IO_PHYS \
 297         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 298                             CONFIG_SYS_PHYS_ADDR_HIGH)
 299 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64K */
 300
 301 #ifdef CONFIG_PHYS_64BIT
 302 /*
 303  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
 304  * This will increase the amount of PCI address space available for
 305  * for mapping RAM.
 306  */
 307 #define CONFIG_SYS_PCIE2_MEM_BUS        CONFIG_SYS_PCIE1_MEM_BUS
 308 #else
 309 #define CONFIG_SYS_PCIE2_MEM_BUS        (CONFIG_SYS_PCIE1_MEM_BUS \
 310                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 311 #endif
 312 #define CONFIG_SYS_PCIE2_MEM_VIRT       (CONFIG_SYS_PCIE1_MEM_VIRT \
 313                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 314 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW   (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
 315                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 316 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH  CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 317 #define CONFIG_SYS_PCIE2_MEM_PHYS       (CONFIG_SYS_PCIE1_MEM_PHYS \
 318                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 319 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 320 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 321 #define CONFIG_SYS_PCIE2_IO_VIRT        (CONFIG_SYS_PCIE1_IO_VIRT \
 322                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 323 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW    (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
 324                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 325 #define CONFIG_SYS_PCIE2_IO_PHYS        (CONFIG_SYS_PCIE1_IO_PHYS \
 326                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 327 #define CONFIG_SYS_PCIE2_IO_SIZE        CONFIG_SYS_PCIE1_IO_SIZE
 328
 329 #if defined(CONFIG_PCI)
 330
 331 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 332
 333
 334 /************************************************************
 335  * USB support
 336  ************************************************************/
 337 #define CONFIG_PCI_OHCI                 1
 338 #define CONFIG_USB_OHCI_NEW             1
 339 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 340 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 341 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 342
 343 /*PCIE video card used*/
 344 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 345
 346 /*PCI video card used*/
 347 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCIE1_IO_VIRT*/
 348
 349 /* video */
 350
 351 #if defined(CONFIG_VIDEO)
 352 #define CONFIG_BIOSEMU
 353 #define CONFIG_ATI_RADEON_FB
 354 #define CONFIG_VIDEO_LOGO
 355 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
 356 #endif
 357
 358 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 359
 360 #ifdef CONFIG_SCSI_AHCI
 361 #define CONFIG_SATA_ULI5288
 362 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 363 #define CONFIG_SYS_SCSI_MAX_LUN 1
 364 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 365 #endif
 366
 367 #endif  /* CONFIG_PCI */
 368
 369 #if defined(CONFIG_TSEC_ENET)
 370 #define CONFIG_TSEC1            1
 371 #define CONFIG_TSEC1_NAME       "eTSEC1"
 372 #define CONFIG_TSEC2            1
 373 #define CONFIG_TSEC2_NAME       "eTSEC2"
 374 #define CONFIG_TSEC3            1
 375 #define CONFIG_TSEC3_NAME       "eTSEC3"
 376 #define CONFIG_TSEC4            1
 377 #define CONFIG_TSEC4_NAME       "eTSEC4"
 378
 379 #define TSEC1_PHY_ADDR          0
 380 #define TSEC2_PHY_ADDR          1
 381 #define TSEC3_PHY_ADDR          2
 382 #define TSEC4_PHY_ADDR          3
 383 #define TSEC1_PHYIDX            0
 384 #define TSEC2_PHYIDX            0
 385 #define TSEC3_PHYIDX            0
 386 #define TSEC4_PHYIDX            0
 387 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 388 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 389 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 390 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 391
 392 #define CONFIG_ETHPRIME         "eTSEC1"
 393
 394 #endif  /* CONFIG_TSEC_ENET */
 395
 396 #ifdef CONFIG_PHYS_64BIT
 397 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 398 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 399
 400 /* Put physical address into the BAT format */
 401 #define BAT_PHYS_ADDR(low, high) \
 402         (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
 403 /* Convert high/low pairs to actual 64-bit value */
 404 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
 405 #else
 406 /* 32-bit systems just ignore the "high" bits */
 407 #define BAT_PHYS_ADDR(low, high)        (low)
 408 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
 409 #endif
 410
 411 /*
 412  * BAT0         DDR
 413  */
 414 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 415 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 416
 417 /*
 418  * BAT1         LBC (PIXIS/CF)
 419  */
 420 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 421                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 422                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 423                                  BATL_GUARDEDSTORAGE)
 424 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 425                                  | BATU_VS | BATU_VP)
 426 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 427                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 428                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 429 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 430
 431 /* if CONFIG_PCI:
 432  * BAT2         PCIE1 and PCIE1 MEM
 433  * if CONFIG_RIO
 434  * BAT2         Rapidio Memory
 435  */
 436 #ifdef CONFIG_PCI
 437 #define CONFIG_PCI_INDIRECT_BRIDGE
 438 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 439                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 440                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 441                                  | BATL_GUARDEDSTORAGE)
 442 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
 443                                  | BATU_VS | BATU_VP)
 444 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 445                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 446                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 447 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 448 #else /* CONFIG_RIO */
 449 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 450                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 451                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 452                                  BATL_GUARDEDSTORAGE)
 453 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
 454                                  | BATU_VS | BATU_VP)
 455 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 456                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 457                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 458 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 459 #endif
 460
 461 /*
 462  * BAT3         CCSR Space
 463  */
 464 #define CONFIG_SYS_DBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 465                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 466                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 467                                  | BATL_GUARDEDSTORAGE)
 468 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 469                                  | BATU_VP)
 470 #define CONFIG_SYS_IBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 471                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 472                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 473 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 474
 475 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 476 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 477                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 478                                        | BATL_GUARDEDSTORAGE)
 479 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 480                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 481 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 482                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 483 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 484 #endif
 485
 486 /*
 487  * BAT4         PCIE1_IO and PCIE2_IO
 488  */
 489 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 490                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 491                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 492                                  | BATL_GUARDEDSTORAGE)
 493 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
 494                                  | BATU_VS | BATU_VP)
 495 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 496                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 497                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 498 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 499
 500 /*
 501  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 502  */
 503 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 504 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 505 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 506 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 507
 508 /*
 509  * BAT6         FLASH
 510  */
 511 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 512                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 513                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 514                                  | BATL_GUARDEDSTORAGE)
 515 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 516                                  | BATU_VP)
 517 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 518                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 519                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 520 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 521
 522 /* Map the last 1M of flash where we're running from reset */
 523 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 524                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 525 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 526 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 527                                  | BATL_MEMCOHERENCE)
 528 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 529
 530 /*
 531  * BAT7         FREE - used later for tmp mappings
 532  */
 533 #define CONFIG_SYS_DBAT7L 0x00000000
 534 #define CONFIG_SYS_DBAT7U 0x00000000
 535 #define CONFIG_SYS_IBAT7L 0x00000000
 536 #define CONFIG_SYS_IBAT7U 0x00000000
 537
 538 /*
 539  * Environment
 540  */
 541
 542 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 543 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 544
 545 /*
 546  * BOOTP options
 547  */
 548 #define CONFIG_BOOTP_BOOTFILESIZE
 549
 550 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 551
 552 /*
 553  * Miscellaneous configurable options
 554  */
 555 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 556
 557 /*
 558  * For booting Linux, the board info and command line data
 559  * have to be in the first 8 MB of memory, since this is
 560  * the maximum mapped by the Linux kernel during initialization.
 561  */
 562 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 563 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 564
 565 #if defined(CONFIG_CMD_KGDB)
 566     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 567 #endif
 568
 569 /*
 570  * Environment Configuration
 571  */
 572
 573 #define CONFIG_HAS_ETH0         1
 574 #define CONFIG_HAS_ETH1         1
 575 #define CONFIG_HAS_ETH2         1
 576 #define CONFIG_HAS_ETH3         1
 577
 578 #define CONFIG_IPADDR           192.168.1.100
 579
 580 #define CONFIG_HOSTNAME         "unknown"
 581 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 582 #define CONFIG_BOOTFILE         "uImage"
 583 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 584
 585 #define CONFIG_SERVERIP         192.168.1.1
 586 #define CONFIG_GATEWAYIP        192.168.1.1
 587 #define CONFIG_NETMASK          255.255.255.0
 588
 589 /* default location for tftp and bootm */
 590 #define CONFIG_LOADADDR         0x10000000
 591
 592 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 593         "netdev=eth0\0"                                                 \
 594         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 595         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 596                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 597                         " +$filesize; " \
 598                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 599                         " +$filesize; " \
 600                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 601                         " $filesize; "  \
 602                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 603                         " +$filesize; " \
 604                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 605                         " $filesize\0"  \
 606         "consoledev=ttyS0\0"                                            \
 607         "ramdiskaddr=0x18000000\0"                                              \
 608         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 609         "fdtaddr=0x17c00000\0"                                          \
 610         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 611         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 612         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 613         "maxcpus=2"
 614
 615 #define CONFIG_NFSBOOTCOMMAND                                           \
 616         "setenv bootargs root=/dev/nfs rw "                             \
 617               "nfsroot=$serverip:$rootpath "                            \
 618               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 619               "console=$consoledev,$baudrate $othbootargs;"             \
 620         "tftp $loadaddr $bootfile;"                                     \
 621         "tftp $fdtaddr $fdtfile;"                                       \
 622         "bootm $loadaddr - $fdtaddr"
 623
 624 #define CONFIG_RAMBOOTCOMMAND                                           \
 625         "setenv bootargs root=/dev/ram rw "                             \
 626               "console=$consoledev,$baudrate $othbootargs;"             \
 627         "tftp $ramdiskaddr $ramdiskfile;"                               \
 628         "tftp $loadaddr $bootfile;"                                     \
 629         "tftp $fdtaddr $fdtfile;"                                       \
 630         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 631
 632 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 633
 634 #endif  /* __CONFIG_H */