include/configs/MPC8641HPCN.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2006, 2010-2011 Freescale Semiconductor.
   4  *
   5  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   6  */
   7
   8 /*
   9  * MPC8641HPCN board configuration file
  10  *
  11  * Make sure you change the MAC address and other network params first,
  12  * search for CONFIG_SERVERIP, etc. in this file.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 #include <linux/stringify.h>
  19
  20 /* High Level Configuration Options */
  21 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  22
  23 /*
  24  * default CCSRBAR is at 0xff700000
  25  * assume U-Boot is less than 0.5MB
  26  */
  27
  28 #ifdef RUN_DIAG
  29 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  30 #endif
  31
  32 /*
  33  * virtual address to be used for temporary mappings.  There
  34  * should be 128k free at this VA.
  35  */
  36 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  37
  38 #define CONFIG_SYS_SRIO
  39 #define CONFIG_SRIO1                    /* SRIO port 1 */
  40
  41 #define CONFIG_PCIE1            1       /* PCIE controller 1 (ULI bridge) */
  42 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot) */
  43 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  44 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  45
  46 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  47
  48 #define CONFIG_ALTIVEC          1
  49
  50 /*
  51  * L2CR setup -- make sure this is right for your board!
  52  */
  53 #define CONFIG_SYS_L2
  54 #define L2_INIT         0
  55 #define L2_ENABLE       (L2CR_L2E)
  56
  57 #ifndef CONFIG_SYS_CLK_FREQ
  58 #ifndef __ASSEMBLY__
  59 extern unsigned long get_board_sys_clk(unsigned long dummy);
  60 #endif
  61 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  62 #endif
  63
  64 /*
  65  * With the exception of PCI Memory and Rapid IO, most devices will simply
  66  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  67  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  68  */
  69 #ifdef CONFIG_PHYS_64BIT
  70 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  71 #else
  72 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  73 #endif
  74
  75 /*
  76  * Base addresses -- Note these are effective addresses where the
  77  * actual resources get mapped (not physical addresses)
  78  */
  79 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  80 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  81
  82 /* Physical addresses */
  83 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  84 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    CONFIG_SYS_PHYS_ADDR_HIGH
  85 #define CONFIG_SYS_CCSRBAR_PHYS \
  86         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  87                             CONFIG_SYS_CCSRBAR_PHYS_HIGH)
  88
  89 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
  90
  91 /*
  92  * DDR Setup
  93  */
  94 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  95 #define CONFIG_DDR_SPD
  96
  97 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  98 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  99
 100 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 101 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 102 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 103 #define CONFIG_VERY_BIG_RAM
 104
 105 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 106 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 107
 108 /*
 109  * I2C addresses of SPD EEPROMs
 110  */
 111 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 112 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 113 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 114 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 115
 116 /*
 117  * These are used when DDR doesn't use SPD.
 118  */
 119 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 120 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 121 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 122 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 123 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 124 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 125 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 126 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 127 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 128 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 129 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 130 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 131 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 132 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 133 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 134 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 135
 136 #define CONFIG_ID_EEPROM
 137 #define CONFIG_SYS_I2C_EEPROM_NXID
 138 #define CONFIG_ID_EEPROM
 139 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 140 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 141
 142 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 143 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW  CONFIG_SYS_FLASH_BASE
 144 #define CONFIG_SYS_FLASH_BASE_PHYS \
 145         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 146                             CONFIG_SYS_PHYS_ADDR_HIGH)
 147
 148 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 149
 150 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 151                                  | 0x00001001)  /* port size 16bit */
 152 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 153
 154 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 155                                  | 0x00001001)  /* port size 16bit */
 156 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 157
 158 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 159                                  | 0x00000801) /* port size 8bit */
 160 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 161
 162 /*
 163  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 164  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 165  * required for the smallest BAT mapping, so there's a 64k hole.
 166  */
 167 #define CONFIG_SYS_LBC_BASE             0xffde0000
 168 #define CONFIG_SYS_LBC_BASE_PHYS_LOW    CONFIG_SYS_LBC_BASE
 169
 170 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 171 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 172 #define PIXIS_BASE_PHYS_LOW     (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
 173 #define PIXIS_BASE_PHYS         PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
 174                                                     CONFIG_SYS_PHYS_ADDR_HIGH)
 175 #define PIXIS_SIZE              0x00008000      /* 32k */
 176 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 177 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 178 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 179 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 180 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 181 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 182 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 183 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 184 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 185 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 186 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 187 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 188 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 189 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 190 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 191 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 192 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 193
 194 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 195 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 196 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 197
 198 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 199 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 200
 201 #undef  CONFIG_SYS_FLASH_CHECKSUM
 202 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 203 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 204 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 205 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 206
 207 #define CONFIG_SYS_FLASH_EMPTY_INFO
 208
 209 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 210 #define CONFIG_SYS_RAMBOOT
 211 #else
 212 #undef  CONFIG_SYS_RAMBOOT
 213 #endif
 214
 215 #if defined(CONFIG_SYS_RAMBOOT)
 216 #undef CONFIG_SPD_EEPROM
 217 #define CONFIG_SYS_SDRAM_SIZE   256
 218 #endif
 219
 220 #define CONFIG_SYS_INIT_RAM_LOCK        1
 221 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 222 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 223 #else
 224 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 225 #endif
 226 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 227
 228 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 229 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 230
 231 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Mon */
 232 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 233
 234 /* Serial Port */
 235 #define CONFIG_SYS_NS16550_SERIAL
 236 #define CONFIG_SYS_NS16550_REG_SIZE     1
 237 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 238
 239 #define CONFIG_SYS_BAUDRATE_TABLE  \
 240         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 241
 242 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 243 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 244
 245 /*
 246  * I2C
 247  */
 248 #define CONFIG_SYS_I2C
 249 #define CONFIG_SYS_I2C_FSL
 250 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 251 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 252 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 253 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 254
 255 /*
 256  * RapidIO MMU
 257  */
 258 #define CONFIG_SYS_SRIO1_MEM_BASE       0x80000000      /* base address */
 259 #ifdef CONFIG_PHYS_64BIT
 260 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   0x00000000
 261 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
 262 #else
 263 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   CONFIG_SYS_SRIO1_MEM_BASE
 264 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
 265 #endif
 266 #define CONFIG_SYS_SRIO1_MEM_PHYS \
 267         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 268                             CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
 269 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 128M */
 270
 271 /*
 272  * General PCI
 273  * Addresses are mapped 1-1.
 274  */
 275
 276 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 277 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 278 #ifdef CONFIG_PHYS_64BIT
 279 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 280 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   0x00000000
 281 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x0000000c
 282 #else
 283 #define CONFIG_SYS_PCIE1_MEM_BUS        CONFIG_SYS_PCIE1_MEM_VIRT
 284 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   CONFIG_SYS_PCIE1_MEM_VIRT
 285 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x00000000
 286 #endif
 287 #define CONFIG_SYS_PCIE1_MEM_PHYS \
 288         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 289                             CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
 290 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 291 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 292 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 293 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW    CONFIG_SYS_PCIE1_IO_VIRT
 294 #define CONFIG_SYS_PCIE1_IO_PHYS \
 295         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 296                             CONFIG_SYS_PHYS_ADDR_HIGH)
 297 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64K */
 298
 299 #ifdef CONFIG_PHYS_64BIT
 300 /*
 301  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
 302  * This will increase the amount of PCI address space available for
 303  * for mapping RAM.
 304  */
 305 #define CONFIG_SYS_PCIE2_MEM_BUS        CONFIG_SYS_PCIE1_MEM_BUS
 306 #else
 307 #define CONFIG_SYS_PCIE2_MEM_BUS        (CONFIG_SYS_PCIE1_MEM_BUS \
 308                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 309 #endif
 310 #define CONFIG_SYS_PCIE2_MEM_VIRT       (CONFIG_SYS_PCIE1_MEM_VIRT \
 311                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 312 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW   (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
 313                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 314 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH  CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 315 #define CONFIG_SYS_PCIE2_MEM_PHYS       (CONFIG_SYS_PCIE1_MEM_PHYS \
 316                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 317 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 318 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 319 #define CONFIG_SYS_PCIE2_IO_VIRT        (CONFIG_SYS_PCIE1_IO_VIRT \
 320                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 321 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW    (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
 322                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 323 #define CONFIG_SYS_PCIE2_IO_PHYS        (CONFIG_SYS_PCIE1_IO_PHYS \
 324                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 325 #define CONFIG_SYS_PCIE2_IO_SIZE        CONFIG_SYS_PCIE1_IO_SIZE
 326
 327 #if defined(CONFIG_PCI)
 328
 329 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 330
 331
 332 /************************************************************
 333  * USB support
 334  ************************************************************/
 335 #define CONFIG_PCI_OHCI                 1
 336 #define CONFIG_USB_OHCI_NEW             1
 337 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 338 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 339 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 340
 341 /*PCIE video card used*/
 342 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 343
 344 /*PCI video card used*/
 345 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCIE1_IO_VIRT*/
 346
 347 /* video */
 348
 349 #if defined(CONFIG_VIDEO)
 350 #define CONFIG_BIOSEMU
 351 #define CONFIG_ATI_RADEON_FB
 352 #define CONFIG_VIDEO_LOGO
 353 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
 354 #endif
 355
 356 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 357
 358 #ifdef CONFIG_SCSI_AHCI
 359 #define CONFIG_SATA_ULI5288
 360 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 361 #define CONFIG_SYS_SCSI_MAX_LUN 1
 362 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 363 #endif
 364
 365 #endif  /* CONFIG_PCI */
 366
 367 #if defined(CONFIG_TSEC_ENET)
 368 #define CONFIG_TSEC1            1
 369 #define CONFIG_TSEC1_NAME       "eTSEC1"
 370 #define CONFIG_TSEC2            1
 371 #define CONFIG_TSEC2_NAME       "eTSEC2"
 372 #define CONFIG_TSEC3            1
 373 #define CONFIG_TSEC3_NAME       "eTSEC3"
 374 #define CONFIG_TSEC4            1
 375 #define CONFIG_TSEC4_NAME       "eTSEC4"
 376
 377 #define TSEC1_PHY_ADDR          0
 378 #define TSEC2_PHY_ADDR          1
 379 #define TSEC3_PHY_ADDR          2
 380 #define TSEC4_PHY_ADDR          3
 381 #define TSEC1_PHYIDX            0
 382 #define TSEC2_PHYIDX            0
 383 #define TSEC3_PHYIDX            0
 384 #define TSEC4_PHYIDX            0
 385 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 386 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 387 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 388 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 389
 390 #define CONFIG_ETHPRIME         "eTSEC1"
 391
 392 #endif  /* CONFIG_TSEC_ENET */
 393
 394 #ifdef CONFIG_PHYS_64BIT
 395 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 396 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 397
 398 /* Put physical address into the BAT format */
 399 #define BAT_PHYS_ADDR(low, high) \
 400         (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
 401 /* Convert high/low pairs to actual 64-bit value */
 402 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
 403 #else
 404 /* 32-bit systems just ignore the "high" bits */
 405 #define BAT_PHYS_ADDR(low, high)        (low)
 406 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
 407 #endif
 408
 409 /*
 410  * BAT0         DDR
 411  */
 412 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 413 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 414
 415 /*
 416  * BAT1         LBC (PIXIS/CF)
 417  */
 418 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 419                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 420                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 421                                  BATL_GUARDEDSTORAGE)
 422 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 423                                  | BATU_VS | BATU_VP)
 424 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 425                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 426                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 427 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 428
 429 /* if CONFIG_PCI:
 430  * BAT2         PCIE1 and PCIE1 MEM
 431  * if CONFIG_RIO
 432  * BAT2         Rapidio Memory
 433  */
 434 #ifdef CONFIG_PCI
 435 #define CONFIG_PCI_INDIRECT_BRIDGE
 436 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 437                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 438                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 439                                  | BATL_GUARDEDSTORAGE)
 440 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
 441                                  | BATU_VS | BATU_VP)
 442 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 443                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 444                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 445 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 446 #else /* CONFIG_RIO */
 447 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 448                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 449                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 450                                  BATL_GUARDEDSTORAGE)
 451 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
 452                                  | BATU_VS | BATU_VP)
 453 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 454                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 455                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 456 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 457 #endif
 458
 459 /*
 460  * BAT3         CCSR Space
 461  */
 462 #define CONFIG_SYS_DBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 463                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 464                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 465                                  | BATL_GUARDEDSTORAGE)
 466 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 467                                  | BATU_VP)
 468 #define CONFIG_SYS_IBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 469                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 470                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 471 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 472
 473 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 474 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 475                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 476                                        | BATL_GUARDEDSTORAGE)
 477 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 478                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 479 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 480                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 481 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 482 #endif
 483
 484 /*
 485  * BAT4         PCIE1_IO and PCIE2_IO
 486  */
 487 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 488                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 489                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 490                                  | BATL_GUARDEDSTORAGE)
 491 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
 492                                  | BATU_VS | BATU_VP)
 493 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 494                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 495                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 496 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 497
 498 /*
 499  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 500  */
 501 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 502 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 503 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 504 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 505
 506 /*
 507  * BAT6         FLASH
 508  */
 509 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 510                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 511                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 512                                  | BATL_GUARDEDSTORAGE)
 513 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 514                                  | BATU_VP)
 515 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 516                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 517                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 518 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 519
 520 /* Map the last 1M of flash where we're running from reset */
 521 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 522                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 523 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 524 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 525                                  | BATL_MEMCOHERENCE)
 526 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 527
 528 /*
 529  * BAT7         FREE - used later for tmp mappings
 530  */
 531 #define CONFIG_SYS_DBAT7L 0x00000000
 532 #define CONFIG_SYS_DBAT7U 0x00000000
 533 #define CONFIG_SYS_IBAT7L 0x00000000
 534 #define CONFIG_SYS_IBAT7U 0x00000000
 535
 536 /*
 537  * Environment
 538  */
 539
 540 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 541 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 542
 543 /*
 544  * BOOTP options
 545  */
 546 #define CONFIG_BOOTP_BOOTFILESIZE
 547
 548 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 549
 550 /*
 551  * Miscellaneous configurable options
 552  */
 553 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 554
 555 /*
 556  * For booting Linux, the board info and command line data
 557  * have to be in the first 8 MB of memory, since this is
 558  * the maximum mapped by the Linux kernel during initialization.
 559  */
 560 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 561 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 562
 563 #if defined(CONFIG_CMD_KGDB)
 564     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 565 #endif
 566
 567 /*
 568  * Environment Configuration
 569  */
 570
 571 #define CONFIG_HAS_ETH0         1
 572 #define CONFIG_HAS_ETH1         1
 573 #define CONFIG_HAS_ETH2         1
 574 #define CONFIG_HAS_ETH3         1
 575
 576 #define CONFIG_IPADDR           192.168.1.100
 577
 578 #define CONFIG_HOSTNAME         "unknown"
 579 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 580 #define CONFIG_BOOTFILE         "uImage"
 581 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 582
 583 #define CONFIG_SERVERIP         192.168.1.1
 584 #define CONFIG_GATEWAYIP        192.168.1.1
 585 #define CONFIG_NETMASK          255.255.255.0
 586
 587 /* default location for tftp and bootm */
 588 #define CONFIG_LOADADDR         0x10000000
 589
 590 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 591         "netdev=eth0\0"                                                 \
 592         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 593         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 594                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 595                         " +$filesize; " \
 596                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 597                         " +$filesize; " \
 598                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 599                         " $filesize; "  \
 600                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 601                         " +$filesize; " \
 602                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 603                         " $filesize\0"  \
 604         "consoledev=ttyS0\0"                                            \
 605         "ramdiskaddr=0x18000000\0"                                              \
 606         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 607         "fdtaddr=0x17c00000\0"                                          \
 608         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 609         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 610         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 611         "maxcpus=2"
 612
 613 #define CONFIG_NFSBOOTCOMMAND                                           \
 614         "setenv bootargs root=/dev/nfs rw "                             \
 615               "nfsroot=$serverip:$rootpath "                            \
 616               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 617               "console=$consoledev,$baudrate $othbootargs;"             \
 618         "tftp $loadaddr $bootfile;"                                     \
 619         "tftp $fdtaddr $fdtfile;"                                       \
 620         "bootm $loadaddr - $fdtaddr"
 621
 622 #define CONFIG_RAMBOOTCOMMAND                                           \
 623         "setenv bootargs root=/dev/ram rw "                             \
 624               "console=$consoledev,$baudrate $othbootargs;"             \
 625         "tftp $ramdiskaddr $ramdiskfile;"                               \
 626         "tftp $loadaddr $bootfile;"                                     \
 627         "tftp $fdtaddr $fdtfile;"                                       \
 628         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 629
 630 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 631
 632 #endif  /* __CONFIG_H */