1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
7 * mpc8572ds board configuration file
13 #include "../board/freescale/common/ics307_clk.h"
15 #ifndef CONFIG_RESET_VECTOR_ADDRESS
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
19 #ifndef CONFIG_SYS_MONITOR_BASE
20 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
23 /* High Level Configuration Options */
25 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
26 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
27 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
28 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
32 #define CONFIG_ENV_OVERWRITE
34 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
35 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
36 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
39 * These can be toggled for performance analysis, otherwise use default.
41 #define CONFIG_L2_CACHE /* toggle L2 cache */
42 #define CONFIG_BTB /* toggle branch predition */
44 #define CONFIG_ENABLE_36BIT_PHYS 1
46 #ifdef CONFIG_PHYS_64BIT
47 #define CONFIG_ADDR_MAP 1
48 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
52 * Config the L2 Cache as L2 SRAM
54 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
55 #ifdef CONFIG_PHYS_64BIT
56 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
58 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
60 #define CONFIG_SYS_L2_SIZE (512 << 10)
61 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
63 #define CONFIG_SYS_CCSRBAR 0xffe00000
64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
66 #if defined(CONFIG_NAND_SPL)
67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
71 #define CONFIG_VERY_BIG_RAM
72 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
73 #define CONFIG_DDR_SPD
75 #define CONFIG_DDR_ECC
76 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
77 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
79 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
82 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
83 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
85 /* I2C addresses of SPD EEPROMs */
86 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
87 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
88 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
90 /* These are used when DDR doesn't use SPD. */
91 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
92 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
93 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
94 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
95 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
96 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634
97 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf
98 #define CONFIG_SYS_DDR_MODE_1 0x00440462
99 #define CONFIG_SYS_DDR_MODE_2 0x00000000
100 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100
101 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
102 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
103 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
104 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
105 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
106 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
108 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
109 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
110 #define CONFIG_SYS_DDR_SBE 0x00010000
113 * Make sure required options are set
115 #ifndef CONFIG_SPD_EEPROM
116 #error ("CONFIG_SPD_EEPROM is required")
119 #undef CONFIG_CLOCKS_IN_MHZ
124 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
125 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
126 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
127 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
129 * Localbus cacheable (TBD)
130 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
132 * Localbus non-cacheable
133 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
134 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
135 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
136 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
137 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
138 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
142 * Local Bus Definitions
144 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
145 #ifdef CONFIG_PHYS_64BIT
146 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
148 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
151 #define CONFIG_FLASH_BR_PRELIM \
152 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
153 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
155 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
156 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
158 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
159 #define CONFIG_SYS_FLASH_QUIET_TEST
160 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
162 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
163 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
164 #undef CONFIG_SYS_FLASH_CHECKSUM
165 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
166 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
168 #undef CONFIG_SYS_RAMBOOT
170 #define CONFIG_SYS_FLASH_EMPTY_INFO
171 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
173 #define CONFIG_HWCONFIG /* enable hwconfig */
174 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
175 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
176 #ifdef CONFIG_PHYS_64BIT
177 #define PIXIS_BASE_PHYS 0xfffdf0000ull
179 #define PIXIS_BASE_PHYS PIXIS_BASE
182 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
183 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
185 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
186 #define PIXIS_VER 0x1 /* Board version at offset 1 */
187 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
188 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
189 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
190 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
191 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
192 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
193 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
194 #define PIXIS_VCTL 0x10 /* VELA Control Register */
195 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
196 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
197 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
198 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
199 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
200 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
201 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
202 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
203 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
204 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
205 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
206 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
207 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
208 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
209 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
210 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
211 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
212 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
213 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
214 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
215 #define PIXIS_LED 0x25 /* LED Register */
217 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
219 /* old pixis referenced names */
220 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
221 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
222 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
223 #define PIXIS_VSPEED2_TSEC1SER 0x8
224 #define PIXIS_VSPEED2_TSEC2SER 0x4
225 #define PIXIS_VSPEED2_TSEC3SER 0x2
226 #define PIXIS_VSPEED2_TSEC4SER 0x1
227 #define PIXIS_VCFGEN1_TSEC1SER 0x20
228 #define PIXIS_VCFGEN1_TSEC2SER 0x20
229 #define PIXIS_VCFGEN1_TSEC3SER 0x20
230 #define PIXIS_VCFGEN1_TSEC4SER 0x20
231 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
232 | PIXIS_VSPEED2_TSEC2SER \
233 | PIXIS_VSPEED2_TSEC3SER \
234 | PIXIS_VSPEED2_TSEC4SER)
235 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
236 | PIXIS_VCFGEN1_TSEC2SER \
237 | PIXIS_VCFGEN1_TSEC3SER \
238 | PIXIS_VCFGEN1_TSEC4SER)
240 #define CONFIG_SYS_INIT_RAM_LOCK 1
241 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
242 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
244 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
245 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
247 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
248 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
250 #ifndef CONFIG_NAND_SPL
251 #define CONFIG_SYS_NAND_BASE 0xffa00000
252 #ifdef CONFIG_PHYS_64BIT
253 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
255 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
258 #define CONFIG_SYS_NAND_BASE 0xfff00000
259 #ifdef CONFIG_PHYS_64BIT
260 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
262 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
266 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
267 CONFIG_SYS_NAND_BASE + 0x40000, \
268 CONFIG_SYS_NAND_BASE + 0x80000,\
269 CONFIG_SYS_NAND_BASE + 0xC0000}
270 #define CONFIG_SYS_MAX_NAND_DEVICE 4
271 #define CONFIG_NAND_FSL_ELBC 1
272 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
273 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
274 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
276 /* NAND boot: 4K NAND loader config */
277 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
278 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
279 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
280 #define CONFIG_SYS_NAND_U_BOOT_START \
281 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
282 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
283 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
284 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
286 /* NAND flash config */
287 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
288 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
289 | BR_PS_8 /* Port Size = 8 bit */ \
290 | BR_MS_FCM /* MSEL = FCM */ \
292 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
293 | OR_FCM_PGS /* Large Page*/ \
301 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
302 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
303 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
304 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
305 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
306 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
307 | BR_PS_8 /* Port Size = 8 bit */ \
308 | BR_MS_FCM /* MSEL = FCM */ \
310 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
311 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
312 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
313 | BR_PS_8 /* Port Size = 8 bit */ \
314 | BR_MS_FCM /* MSEL = FCM */ \
316 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
318 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
319 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
320 | BR_PS_8 /* Port Size = 8 bit */ \
321 | BR_MS_FCM /* MSEL = FCM */ \
323 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
325 /* Serial Port - controlled on board with jumper J8
329 #define CONFIG_SYS_NS16550_SERIAL
330 #define CONFIG_SYS_NS16550_REG_SIZE 1
331 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
332 #ifdef CONFIG_NAND_SPL
333 #define CONFIG_NS16550_MIN_FUNCTIONS
336 #define CONFIG_SYS_BAUDRATE_TABLE \
337 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
339 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
340 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
343 #define CONFIG_SYS_I2C
344 #define CONFIG_SYS_I2C_FSL
345 #define CONFIG_SYS_FSL_I2C_SPEED 400000
346 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
347 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
348 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
349 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
350 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
351 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
352 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
357 #define CONFIG_ID_EEPROM
358 #ifdef CONFIG_ID_EEPROM
359 #define CONFIG_SYS_I2C_EEPROM_NXID
361 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
362 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
363 #define CONFIG_SYS_EEPROM_BUS_NUM 1
367 * Memory space is mapped 1-1, but I/O space must start from 0.
370 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
371 #define CONFIG_SYS_PCIE3_NAME "ULI"
372 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
373 #ifdef CONFIG_PHYS_64BIT
374 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
375 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
377 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
378 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
380 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
381 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
382 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
383 #ifdef CONFIG_PHYS_64BIT
384 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
386 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
388 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
390 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
391 #define CONFIG_SYS_PCIE2_NAME "Slot 1"
392 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
393 #ifdef CONFIG_PHYS_64BIT
394 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
395 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
397 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
398 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
400 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
401 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
402 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
406 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
408 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
410 /* controller 1, Slot 1, tgtid 1, Base address a000 */
411 #define CONFIG_SYS_PCIE1_NAME "Slot 2"
412 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
413 #ifdef CONFIG_PHYS_64BIT
414 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
415 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
417 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
418 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
420 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
421 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
422 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
423 #ifdef CONFIG_PHYS_64BIT
424 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
426 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
428 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
430 #if defined(CONFIG_PCI)
432 /*PCIE video card used*/
433 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
437 #if defined(CONFIG_VIDEO)
438 #define CONFIG_BIOSEMU
439 #define CONFIG_ATI_RADEON_FB
440 #define CONFIG_VIDEO_LOGO
441 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
444 #undef CONFIG_EEPRO100
447 #ifndef CONFIG_PCI_PNP
448 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
449 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
450 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
453 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
455 #ifdef CONFIG_SCSI_AHCI
456 #define CONFIG_SATA_ULI5288
457 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
458 #define CONFIG_SYS_SCSI_MAX_LUN 1
459 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
462 #endif /* CONFIG_PCI */
464 #if defined(CONFIG_TSEC_ENET)
466 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
467 #define CONFIG_TSEC1 1
468 #define CONFIG_TSEC1_NAME "eTSEC1"
469 #define CONFIG_TSEC2 1
470 #define CONFIG_TSEC2_NAME "eTSEC2"
471 #define CONFIG_TSEC3 1
472 #define CONFIG_TSEC3_NAME "eTSEC3"
473 #define CONFIG_TSEC4 1
474 #define CONFIG_TSEC4_NAME "eTSEC4"
476 #define CONFIG_PIXIS_SGMII_CMD
477 #define CONFIG_FSL_SGMII_RISER 1
478 #define SGMII_RISER_PHY_OFFSET 0x1c
480 #ifdef CONFIG_FSL_SGMII_RISER
481 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
484 #define TSEC1_PHY_ADDR 0
485 #define TSEC2_PHY_ADDR 1
486 #define TSEC3_PHY_ADDR 2
487 #define TSEC4_PHY_ADDR 3
489 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
490 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
491 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
492 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
494 #define TSEC1_PHYIDX 0
495 #define TSEC2_PHYIDX 0
496 #define TSEC3_PHYIDX 0
497 #define TSEC4_PHYIDX 0
499 #define CONFIG_ETHPRIME "eTSEC1"
500 #endif /* CONFIG_TSEC_ENET */
506 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
507 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
513 #ifdef CONFIG_USB_EHCI_HCD
514 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
515 #define CONFIG_PCI_EHCI_DEVICE 0
518 #undef CONFIG_WATCHDOG /* watchdog disabled */
521 * Miscellaneous configurable options
523 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
526 * For booting Linux, the board info and command line data
527 * have to be in the first 64 MB of memory, since this is
528 * the maximum mapped by the Linux kernel during initialization.
530 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
531 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
533 #if defined(CONFIG_CMD_KGDB)
534 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
538 * Environment Configuration
540 #if defined(CONFIG_TSEC_ENET)
541 #define CONFIG_HAS_ETH0
542 #define CONFIG_HAS_ETH1
543 #define CONFIG_HAS_ETH2
544 #define CONFIG_HAS_ETH3
547 #define CONFIG_IPADDR 192.168.1.254
549 #define CONFIG_HOSTNAME "unknown"
550 #define CONFIG_ROOTPATH "/opt/nfsroot"
551 #define CONFIG_BOOTFILE "uImage"
552 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
554 #define CONFIG_SERVERIP 192.168.1.1
555 #define CONFIG_GATEWAYIP 192.168.1.1
556 #define CONFIG_NETMASK 255.255.255.0
558 /* default location for tftp and bootm */
559 #define CONFIG_LOADADDR 1000000
561 #define CONFIG_EXTRA_ENV_SETTINGS \
562 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
564 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
565 "tftpflash=tftpboot $loadaddr $uboot; " \
566 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
568 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
570 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
572 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
574 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
576 "consoledev=ttyS0\0" \
577 "ramdiskaddr=2000000\0" \
578 "ramdiskfile=8572ds/ramdisk.uboot\0" \
579 "fdtaddr=1e00000\0" \
580 "fdtfile=8572ds/mpc8572ds.dtb\0" \
583 #define CONFIG_HDBOOT \
584 "setenv bootargs root=/dev/$bdev rw " \
585 "console=$consoledev,$baudrate $othbootargs;" \
586 "tftp $loadaddr $bootfile;" \
587 "tftp $fdtaddr $fdtfile;" \
588 "bootm $loadaddr - $fdtaddr"
590 #define CONFIG_NFSBOOTCOMMAND \
591 "setenv bootargs root=/dev/nfs rw " \
592 "nfsroot=$serverip:$rootpath " \
593 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
594 "console=$consoledev,$baudrate $othbootargs;" \
595 "tftp $loadaddr $bootfile;" \
596 "tftp $fdtaddr $fdtfile;" \
597 "bootm $loadaddr - $fdtaddr"
599 #define CONFIG_RAMBOOTCOMMAND \
600 "setenv bootargs root=/dev/ram rw " \
601 "console=$consoledev,$baudrate $othbootargs;" \
602 "tftp $ramdiskaddr $ramdiskfile;" \
603 "tftp $loadaddr $bootfile;" \
604 "tftp $fdtaddr $fdtfile;" \
605 "bootm $loadaddr $ramdiskaddr $fdtaddr"
607 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
609 #endif /* __CONFIG_H */