include/configs/MPC8569MDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * mpc8569mds board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_SYS_SRIO
  13 #define CONFIG_SRIO1                    /* SRIO port 1 */
  14
  15 #define CONFIG_PCIE1            1       /* PCIE controller */
  16 #define CONFIG_FSL_PCI_INIT     1       /* use common fsl pci init code */
  17 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  18 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  19 #define CONFIG_ENV_OVERWRITE
  20
  21 #ifndef __ASSEMBLY__
  22 extern unsigned long get_clock_freq(void);
  23 #endif
  24 /* Replace a call to get_clock_freq (after it is implemented)*/
  25 #define CONFIG_SYS_CLK_FREQ     66666666
  26 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  27
  28 #ifdef CONFIG_ATM
  29 #define CONFIG_PQ_MDS_PIB
  30 #define CONFIG_PQ_MDS_PIB_ATM
  31 #endif
  32
  33 /*
  34  * These can be toggled for performance analysis, otherwise use default.
  35  */
  36 #define CONFIG_L2_CACHE                         /* toggle L2 cache      */
  37 #define CONFIG_BTB                              /* toggle branch predition */
  38
  39 #ifndef CONFIG_SYS_MONITOR_BASE
  40 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  41 #endif
  42
  43 /*
  44  * Only possible on E500 Version 2 or newer cores.
  45  */
  46 #define CONFIG_ENABLE_36BIT_PHYS        1
  47
  48 #define CONFIG_HWCONFIG
  49
  50 /*
  51  * Config the L2 Cache as L2 SRAM
  52  */
  53 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
  54 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
  55 #define CONFIG_SYS_L2_SIZE              (512 << 10)
  56 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  57
  58 #define CONFIG_SYS_CCSRBAR              0xe0000000
  59 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  60
  61 #if defined(CONFIG_NAND_SPL)
  62 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  63 #endif
  64
  65 /* DDR Setup */
  66 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  67 #define CONFIG_DDR_SPD
  68 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  69
  70 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  71
  72 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  73                                         /* DDR is system memory*/
  74 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  75
  76 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  77 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  78
  79 /* I2C addresses of SPD EEPROMs */
  80 #define SPD_EEPROM_ADDRESS    0x51    /* CTLR 0 DIMM 0 */
  81
  82 /* These are used when DDR doesn't use SPD.  */
  83 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1024MB */
  84 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
  85 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
  86 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
  87 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
  88 #define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
  89 #define CONFIG_SYS_DDR_TIMING_2         0x002888D0
  90 #define CONFIG_SYS_DDR_SDRAM_CFG        0x47000000
  91 #define CONFIG_SYS_DDR_SDRAM_CFG_2      0x04401040
  92 #define CONFIG_SYS_DDR_SDRAM_MODE       0x40401521
  93 #define CONFIG_SYS_DDR_SDRAM_MODE_2     0x8000C000
  94 #define CONFIG_SYS_DDR_SDRAM_INTERVAL   0x03E00000
  95 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
  96 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x01000000
  97 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
  98 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
  99 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 100 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x0655A604
 101 #define CONFIG_SYS_DDR_CDR_1            0x80040000
 102 #define CONFIG_SYS_DDR_CDR_2            0x00000000
 103 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 104 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 105 #define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
 106 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
 107
 108 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 109 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 110 #define CONFIG_SYS_DDR_SBE              0x00010000
 111
 112 /*
 113  * Local Bus Definitions
 114  */
 115
 116 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of FLASH 32M */
 117 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 118
 119 #define CONFIG_SYS_BCSR_BASE            0xf8000000
 120 #define CONFIG_SYS_BCSR_BASE_PHYS       CONFIG_SYS_BCSR_BASE
 121
 122 /*Chip select 0 - Flash*/
 123 #define CONFIG_FLASH_BR_PRELIM          0xfe000801
 124 #define CONFIG_FLASH_OR_PRELIM          0xfe000ff7
 125
 126 /*Chip select 1 - BCSR*/
 127 #define CONFIG_SYS_BR1_PRELIM           0xf8000801
 128 #define CONFIG_SYS_OR1_PRELIM           0xffffe9f7
 129
 130 /*Chip select 4 - PIB*/
 131 #define CONFIG_SYS_BR4_PRELIM           0xf8008801
 132 #define CONFIG_SYS_OR4_PRELIM           0xffffe9f7
 133
 134 /*Chip select 5 - PIB*/
 135 #define CONFIG_SYS_BR5_PRELIM           0xf8010801
 136 #define CONFIG_SYS_OR5_PRELIM           0xffffe9f7
 137
 138 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 139 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 140 #undef  CONFIG_SYS_FLASH_CHECKSUM
 141 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 142 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 143
 144 #undef CONFIG_SYS_RAMBOOT
 145
 146 #define CONFIG_SYS_FLASH_EMPTY_INFO
 147
 148 /* Chip select 3 - NAND */
 149 #ifndef CONFIG_NAND_SPL
 150 #define CONFIG_SYS_NAND_BASE            0xFC000000
 151 #else
 152 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 153 #endif
 154
 155 /* NAND boot: 4K NAND loader config */
 156 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 157 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 158 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 159 #define CONFIG_SYS_NAND_U_BOOT_START \
 160         (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 161 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 162 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 163 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 164
 165 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 166 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE, }
 167 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 168 #define CONFIG_NAND_FSL_ELBC            1
 169 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 170 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE_PHYS \
 171                                 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
 172                                 | BR_PS_8            /* Port Size = 8 bit */ \
 173                                 | BR_MS_FCM          /* MSEL = FCM */ \
 174                                 | BR_V)              /* valid */
 175 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFC0000          /* length 256K */ \
 176                                 | OR_FCM_CSCT \
 177                                 | OR_FCM_CST \
 178                                 | OR_FCM_CHT \
 179                                 | OR_FCM_SCY_1 \
 180                                 | OR_FCM_TRLX \
 181                                 | OR_FCM_EHTR)
 182
 183 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 184 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 185 #define CONFIG_SYS_BR3_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 186 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 187
 188 #define CONFIG_SYS_LBC_LCRR     0x00000004      /* LB clock ratio reg */
 189 #define CONFIG_SYS_LBC_LBCR     0x00040000      /* LB config reg */
 190 #define CONFIG_SYS_LBC_LSRT     0x20000000      /* LB sdram refresh timer */
 191 #define CONFIG_SYS_LBC_MRTPR    0x00000000      /* LB refresh timer prescal*/
 192
 193 #define CONFIG_SYS_INIT_RAM_LOCK        1
 194 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000  /* Initial RAM address */
 195 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 196
 197 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 198                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 199 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 200
 201 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 202 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 203
 204 /* Serial Port */
 205 #define CONFIG_SYS_NS16550_SERIAL
 206 #define CONFIG_SYS_NS16550_REG_SIZE    1
 207 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 208 #ifdef CONFIG_NAND_SPL
 209 #define CONFIG_NS16550_MIN_FUNCTIONS
 210 #endif
 211
 212 #define CONFIG_SYS_BAUDRATE_TABLE  \
 213         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 214
 215 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 216 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 217
 218 /*
 219  * I2C
 220  */
 221 #define CONFIG_SYS_I2C
 222 #define CONFIG_SYS_I2C_FSL
 223 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 224 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 225 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 226 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 227 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 228 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 229 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 230
 231 /*
 232  * I2C2 EEPROM
 233  */
 234 #define CONFIG_ID_EEPROM
 235 #ifdef CONFIG_ID_EEPROM
 236 #define CONFIG_SYS_I2C_EEPROM_NXID
 237 #endif
 238 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 239 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 240 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 241
 242 #define PLPPAR1_I2C_BIT_MASK            0x0000000F
 243 #define PLPPAR1_I2C2_VAL                0x00000000
 244 #define PLPPAR1_ESDHC_VAL               0x0000000A
 245 #define PLPDIR1_I2C_BIT_MASK            0x0000000F
 246 #define PLPDIR1_I2C2_VAL                0x0000000F
 247 #define PLPDIR1_ESDHC_VAL               0x00000006
 248 #define PLPPAR1_UART0_BIT_MASK          0x00000fc0
 249 #define PLPPAR1_ESDHC_4BITS_VAL         0x00000a80
 250 #define PLPDIR1_UART0_BIT_MASK          0x00000fc0
 251 #define PLPDIR1_ESDHC_4BITS_VAL         0x00000a80
 252
 253 /*
 254  * General PCI
 255  * Memory Addresses are mapped 1-1. I/O is mapped from 0
 256  */
 257 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 258 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 259 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 260 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 261 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 262 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 263 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 264 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 265 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 266
 267 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xC0000000
 268 #define CONFIG_SYS_SRIO1_MEM_BUS        0xC0000000
 269 #define CONFIG_SYS_SRIO1_MEM_PHYS       CONFIG_SYS_SRIO1_MEM_BUS
 270 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 271
 272 #ifdef CONFIG_QE
 273 /*
 274  * QE UEC ethernet configuration
 275  */
 276 #define CONFIG_SYS_UCC_RGMII_MODE       /* Set UCC work at RGMII by default */
 277 #undef CONFIG_SYS_UCC_RMII_MODE         /* Set UCC work at RMII mode */
 278
 279 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 280 #define CONFIG_UEC_ETH
 281 #define CONFIG_ETHPRIME         "UEC0"
 282 #define CONFIG_PHY_MODE_NEED_CHANGE
 283
 284 #define CONFIG_UEC_ETH1         /* GETH1 */
 285 #define CONFIG_HAS_ETH0
 286
 287 #ifdef CONFIG_UEC_ETH1
 288 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 289 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 290 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 291 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 292 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 293 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 294 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 295 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 296 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 297 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16 /* CLK16 for RMII */
 298 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
 299 #define CONFIG_SYS_UEC1_PHY_ADDR       8        /* 0x8 for RMII */
 300 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 301 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 302 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 303 #endif /* CONFIG_UEC_ETH1 */
 304
 305 #define CONFIG_UEC_ETH2         /* GETH2 */
 306 #define CONFIG_HAS_ETH1
 307
 308 #ifdef CONFIG_UEC_ETH2
 309 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 310 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 311 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 312 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 313 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 314 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 315 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 316 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 317 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 318 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16 /* CLK 16 for RMII */
 319 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
 320 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9      /* 0x9 for RMII */
 321 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 322 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 323 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 324 #endif /* CONFIG_UEC_ETH2 */
 325
 326 #define CONFIG_UEC_ETH3         /* GETH3 */
 327 #define CONFIG_HAS_ETH2
 328
 329 #ifdef CONFIG_UEC_ETH3
 330 #define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
 331 #define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
 332 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 333 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
 334 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
 335 #define CONFIG_SYS_UEC3_PHY_ADDR       2
 336 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 337 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
 338 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 339 #define CONFIG_SYS_UEC3_TX_CLK          QE_CLK16 /* CLK_16 for RMII */
 340 #define CONFIG_SYS_UEC3_ETH_TYPE        FAST_ETH
 341 #define CONFIG_SYS_UEC3_PHY_ADDR        0xA     /* 0xA for RMII */
 342 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 343 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
 344 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 345 #endif /* CONFIG_UEC_ETH3 */
 346
 347 #define CONFIG_UEC_ETH4         /* GETH4 */
 348 #define CONFIG_HAS_ETH3
 349
 350 #ifdef CONFIG_UEC_ETH4
 351 #define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
 352 #define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
 353 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 354 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
 355 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
 356 #define CONFIG_SYS_UEC4_PHY_ADDR       3
 357 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 358 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
 359 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 360 #define CONFIG_SYS_UEC4_TX_CLK          QE_CLK16 /* CLK16 for RMII */
 361 #define CONFIG_SYS_UEC4_ETH_TYPE        FAST_ETH
 362 #define CONFIG_SYS_UEC4_PHY_ADDR        0xB     /* 0xB for RMII */
 363 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 364 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
 365 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 366 #endif /* CONFIG_UEC_ETH4 */
 367
 368 #undef CONFIG_UEC_ETH6         /* GETH6 */
 369 #define CONFIG_HAS_ETH5
 370
 371 #ifdef CONFIG_UEC_ETH6
 372 #define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
 373 #define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
 374 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
 375 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
 376 #define CONFIG_SYS_UEC6_PHY_ADDR       4
 377 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
 378 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
 379 #endif /* CONFIG_UEC_ETH6 */
 380
 381 #undef CONFIG_UEC_ETH8         /* GETH8 */
 382 #define CONFIG_HAS_ETH7
 383
 384 #ifdef CONFIG_UEC_ETH8
 385 #define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
 386 #define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
 387 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
 388 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
 389 #define CONFIG_SYS_UEC8_PHY_ADDR       6
 390 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
 391 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
 392 #endif /* CONFIG_UEC_ETH8 */
 393
 394 #endif /* CONFIG_QE */
 395
 396 #if defined(CONFIG_PCI)
 397
 398 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 399
 400 #endif  /* CONFIG_PCI */
 401
 402 /*
 403  * Environment
 404  */
 405
 406 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 407 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 408
 409 /* QE microcode/firmware address */
 410 #define CONFIG_SYS_QE_FW_ADDR   0xfff00000
 411
 412 /*
 413  * BOOTP options
 414  */
 415 #define CONFIG_BOOTP_BOOTFILESIZE
 416
 417 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 418
 419 #ifdef CONFIG_MMC
 420 #define CONFIG_FSL_ESDHC_PIN_MUX
 421 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 422 #endif
 423
 424 /*
 425  * Miscellaneous configurable options
 426  */
 427 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 428 #if defined(CONFIG_CMD_KGDB)
 429 #define CONFIG_SYS_CBSIZE       2048            /* Console I/O Buffer Size */
 430 #else
 431 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
 432 #endif
 433 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
 434 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 435                                                 /* Boot Argument Buffer Size */
 436
 437 /*
 438  * For booting Linux, the board info and command line data
 439  * have to be in the first 64 MB of memory, since this is
 440  * the maximum mapped by the Linux kernel during initialization.
 441  */
 442 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux*/
 443 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 444
 445 #if defined(CONFIG_CMD_KGDB)
 446 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 447 #endif
 448
 449 /*
 450  * Environment Configuration
 451  */
 452 #define CONFIG_HOSTNAME "mpc8569mds"
 453 #define CONFIG_ROOTPATH  "/nfsroot"
 454 #define CONFIG_BOOTFILE  "your.uImage"
 455
 456 #define CONFIG_SERVERIP  192.168.1.1
 457 #define CONFIG_GATEWAYIP 192.168.1.1
 458 #define CONFIG_NETMASK   255.255.255.0
 459
 460 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 461
 462 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 463         "netdev=eth0\0"                                                 \
 464         "consoledev=ttyS0\0"                                            \
 465         "ramdiskaddr=600000\0"                                          \
 466         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 467         "fdtaddr=400000\0"                                              \
 468         "fdtfile=your.fdt.dtb\0"                                        \
 469         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 470         "nfsroot=$serverip:$rootpath "                                  \
 471         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 472         "console=$consoledev,$baudrate $othbootargs\0"                  \
 473         "ramargs=setenv bootargs root=/dev/ram rw "                     \
 474         "console=$consoledev,$baudrate $othbootargs\0"                  \
 475
 476 #define CONFIG_NFSBOOTCOMMAND                                           \
 477         "run nfsargs;"                                                  \
 478         "tftp $loadaddr $bootfile;"                                     \
 479         "tftp $fdtaddr $fdtfile;"                                       \
 480         "bootm $loadaddr - $fdtaddr"
 481
 482 #define CONFIG_RAMBOOTCOMMAND                                           \
 483         "run ramargs;"                                                  \
 484         "tftp $ramdiskaddr $ramdiskfile;"                               \
 485         "tftp $loadaddr $bootfile;"                                     \
 486         "bootm $loadaddr $ramdiskaddr"
 487
 488 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 489
 490 #endif  /* __CONFIG_H */