include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <linux/stringify.h>
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_E300             1 /* E300 family */
  17
  18 #define CONFIG_HWCONFIG
  19
  20 /*
  21  * On-board devices
  22  */
  23 #define CONFIG_VSC7385_ENET
  24
  25 /* System performance - define the value i.e. CONFIG_SYS_XXX
  26 */
  27
  28 /* System Clock Configuration Register */
  29 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
  30 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
  31 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  32
  33 /*
  34  * System IO Config
  35  */
  36 #define CONFIG_SYS_SICRH                0x08200000
  37 #define CONFIG_SYS_SICRL                0x00000000
  38
  39 /*
  40  * Output Buffer Impedance
  41  */
  42 #define CONFIG_SYS_OBIR         0x30100000
  43
  44 /*
  45  * Device configurations
  46  */
  47
  48 /* Vitesse 7385 */
  49
  50 #ifdef CONFIG_VSC7385_ENET
  51
  52 #define CONFIG_TSEC2
  53
  54 /* The flash address and size of the VSC7385 firmware image */
  55 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  56 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  57
  58 #endif
  59
  60 /*
  61  * DDR Setup
  62  */
  63 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  64 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
  65 #define CONFIG_SYS_83XX_DDR_USES_CS0
  66
  67 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  68
  69 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
  70
  71 /*
  72  * Manually set up DDR parameters
  73  */
  74 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  75 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
  76 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  77                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
  78                                         | CSCONFIG_ROW_BIT_13 \
  79                                         | CSCONFIG_COL_BIT_10)
  80
  81 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  82 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  83                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  84                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  85                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  86                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  87                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  88                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  89                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  90                                 /* 0x00260802 */ /* DDR400 */
  91 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  92                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  93                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  94                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  95                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
  96                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  97                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  98                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  99                                 /* 0x3937d322 */
 100 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 101                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 102                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 103                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 104                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 105                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 106                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 107                                 /* 0x02984cc8 */
 108
 109 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 110                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 111                                 /* 0x06090100 */
 112
 113 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 114                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 115                                         /* 0x43000000 */
 116 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 117 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 118                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 119                                         /* 0x04400442 */ /* DDR400 */
 120 #define CONFIG_SYS_DDR_MODE2            0x00000000
 121
 122 /*
 123  * Memory test
 124  */
 125 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 126
 127 /*
 128  * The reserved memory
 129  */
 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 131
 132 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 133 #define CONFIG_SYS_RAMBOOT
 134 #else
 135 #undef  CONFIG_SYS_RAMBOOT
 136 #endif
 137
 138 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 139
 140 /*
 141  * Initial RAM Base Address Setup
 142  */
 143 #define CONFIG_SYS_INIT_RAM_LOCK        1
 144 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 145 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 146 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 147                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 148
 149 /*
 150  * FLASH on the Local Bus
 151  */
 152 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 153 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 154
 155 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 156
 157
 158 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 159
 160 #undef  CONFIG_SYS_FLASH_CHECKSUM
 161 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 162 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 163
 164 /*
 165  * NAND Flash on the Local Bus
 166  */
 167 #define CONFIG_SYS_NAND_BASE    0xE0600000
 168
 169
 170 /* Vitesse 7385 */
 171
 172 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 173
 174 /*
 175  * Serial Port
 176  */
 177 #define CONFIG_SYS_NS16550_SERIAL
 178 #define CONFIG_SYS_NS16550_REG_SIZE     1
 179 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 180
 181 #define CONFIG_SYS_BAUDRATE_TABLE \
 182                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 183
 184 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 185 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 186
 187 /* SERDES */
 188 #define CONFIG_FSL_SERDES
 189 #define CONFIG_FSL_SERDES1      0xe3000
 190 #define CONFIG_FSL_SERDES2      0xe3100
 191
 192 /* I2C */
 193 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 194
 195 /*
 196  * Config on-board RTC
 197  */
 198 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 199 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 200
 201 /*
 202  * General PCI
 203  * Addresses are mapped 1-1.
 204  */
 205 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 206 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 207 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 208 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 209 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 210 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 211 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 212 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 213 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 214
 215 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 216 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 217 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 218
 219 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 220 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 221 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 222 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 223 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 224 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 225 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 226 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 227 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 228
 229 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 230 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 231 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 232 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 233 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 234 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 235 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 236 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 237 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 238
 239 #ifdef CONFIG_PCI
 240 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 241 #endif  /* CONFIG_PCI */
 242
 243 /*
 244  * TSEC
 245  */
 246 #ifdef CONFIG_TSEC_ENET
 247
 248 #define CONFIG_GMII                     /* MII PHY management */
 249
 250 #define CONFIG_TSEC1
 251
 252 #ifdef CONFIG_TSEC1
 253 #define CONFIG_TSEC1_NAME               "TSEC0"
 254 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 255 #define TSEC1_PHY_ADDR                  2
 256 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 257 #define TSEC1_PHYIDX                    0
 258 #endif
 259
 260 #ifdef CONFIG_TSEC2
 261 #define CONFIG_TSEC2_NAME               "TSEC1"
 262 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 263 #define TSEC2_PHY_ADDR                  0x1c
 264 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 265 #define TSEC2_PHYIDX                    0
 266 #endif
 267 #endif
 268
 269 /*
 270  * SATA
 271  */
 272 #define CONFIG_SATA1
 273 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 274 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 275 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 276 #define CONFIG_SATA2
 277 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 278 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 279 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 280
 281 #ifdef CONFIG_FSL_SATA
 282 #define CONFIG_LBA48
 283 #endif
 284
 285 /*
 286  * Environment
 287  */
 288
 289 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 290 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 291
 292 #ifdef CONFIG_MMC
 293 #define CONFIG_FSL_ESDHC_PIN_MUX
 294 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 295 #endif
 296
 297 /*
 298  * Miscellaneous configurable options
 299  */
 300
 301 /*
 302  * For booting Linux, the board info and command line data
 303  * have to be in the first 256 MB of memory, since this is
 304  * the maximum mapped by the Linux kernel during initialization.
 305  */
 306 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 307 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 308
 309 /*
 310  * Environment Configuration
 311  */
 312
 313 #define CONFIG_HAS_FSL_DR_USB
 314 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 315
 316 #define CONFIG_NETDEV           "eth1"
 317
 318 #define CONFIG_HOSTNAME         "mpc837x_rdb"
 319 #define CONFIG_ROOTPATH         "/nfsroot"
 320 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 321                                 /* U-Boot image on TFTP server */
 322 #define CONFIG_UBOOTPATH        "u-boot.bin"
 323 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 324
 325 #define CONFIG_EXTRA_ENV_SETTINGS \
 326         "netdev=" CONFIG_NETDEV "\0"                            \
 327         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 328         "tftpflash=tftp $loadaddr $uboot;"                              \
 329                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 330                         " +$filesize; " \
 331                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 332                         " +$filesize; " \
 333                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 334                         " $filesize; "  \
 335                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 336                         " +$filesize; " \
 337                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 338                         " $filesize\0"  \
 339         "fdtaddr=780000\0"                                              \
 340         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 341         "ramdiskaddr=1000000\0"                                         \
 342         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 343         "console=ttyS0\0"                                               \
 344         "setbootargs=setenv bootargs "                                  \
 345                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 346         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 347                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 348                                                         "$netdev:off "  \
 349                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 350
 351 #endif  /* __CONFIG_H */