include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <linux/stringify.h>
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16
  17 /*
  18  * On-board devices
  19  */
  20 #define CONFIG_VSC7385_ENET
  21
  22 /* System performance - define the value i.e. CONFIG_SYS_XXX
  23 */
  24
  25 /* System Clock Configuration Register */
  26 #define CFG_SYS_SCCR_TSEC1CM    1               /* eTSEC1 clock mode (0-3) */
  27 #define CFG_SYS_SCCR_TSEC2CM    1               /* eTSEC2 clock mode (0-3) */
  28 #define CFG_SYS_SCCR_SATACM     SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  29
  30 /*
  31  * System IO Config
  32  */
  33 #define CFG_SYS_SICRH           0x08200000
  34 #define CFG_SYS_SICRL           0x00000000
  35
  36 /*
  37  * Output Buffer Impedance
  38  */
  39 #define CFG_SYS_OBIR            0x30100000
  40
  41 /*
  42  * Device configurations
  43  */
  44
  45 /* Vitesse 7385 */
  46
  47 #ifdef CONFIG_VSC7385_ENET
  48
  49 #define CONFIG_TSEC2
  50
  51 /* The flash address and size of the VSC7385 firmware image */
  52 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  53 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  54
  55 #endif
  56
  57 /*
  58  * DDR Setup
  59  */
  60 #define CFG_SYS_SDRAM_BASE              0x00000000 /* DDR is system memory */
  61 #define CFG_SYS_DDR_SDRAM_CLK_CNTL      0x03000000
  62
  63 #define CFG_SYS_DDRCDR_VALUE    (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  64
  65 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
  66
  67 /*
  68  * Manually set up DDR parameters
  69  */
  70 #define CFG_SYS_SDRAM_SIZE              0x10000000 /* 256 MiB */
  71 #define CFG_SYS_DDR_CS0_BNDS            0x0000000f
  72 #define CFG_SYS_DDR_CS0_CONFIG  (CSCONFIG_EN \
  73                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
  74                                         | CSCONFIG_ROW_BIT_13 \
  75                                         | CSCONFIG_COL_BIT_10)
  76
  77 #define CFG_SYS_DDR_TIMING_3    0x00000000
  78 #define CFG_SYS_DDR_TIMING_0    ((0 << TIMING_CFG0_RWT_SHIFT) \
  79                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  80                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  81                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  82                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  83                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  84                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  85                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  86                                 /* 0x00260802 */ /* DDR400 */
  87 #define CFG_SYS_DDR_TIMING_1    ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  88                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  89                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  90                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  91                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
  92                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  93                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  94                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  95                                 /* 0x3937d322 */
  96 #define CFG_SYS_DDR_TIMING_2    ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  97                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
  98                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  99                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 100                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 101                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 102                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 103                                 /* 0x02984cc8 */
 104
 105 #define CFG_SYS_DDR_INTERVAL    ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 106                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 107                                 /* 0x06090100 */
 108
 109 #define CFG_SYS_DDR_SDRAM_CFG   (SDRAM_CFG_SREN \
 110                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 111                                         /* 0x43000000 */
 112 #define CFG_SYS_DDR_SDRAM_CFG2  0x00001000 /* 1 posted refresh */
 113 #define CFG_SYS_DDR_MODE                ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 114                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 115                                         /* 0x04400442 */ /* DDR400 */
 116 #define CFG_SYS_DDR_MODE2               0x00000000
 117
 118 /*
 119  * Memory test
 120  */
 121 #undef CFG_SYS_DRAM_TEST                /* memory test, takes time */
 122
 123 /*
 124  * The reserved memory
 125  */
 126
 127 /*
 128  * Initial RAM Base Address Setup
 129  */
 130 #define CFG_SYS_INIT_RAM_ADDR   0xE6000000 /* Initial RAM address */
 131 #define CFG_SYS_INIT_RAM_SIZE   0x1000 /* Size of used area in RAM */
 132
 133 /*
 134  * FLASH on the Local Bus
 135  */
 136 #define CFG_SYS_FLASH_BASE              0xFE000000 /* FLASH base address */
 137 #define CFG_SYS_FLASH_SIZE              8 /* max FLASH size is 32M */
 138
 139 /*
 140  * NAND Flash on the Local Bus
 141  */
 142 #define CFG_SYS_NAND_BASE       0xE0600000
 143
 144
 145 /* Vitesse 7385 */
 146
 147 #define CFG_SYS_VSC7385_BASE    0xF0000000
 148
 149 /*
 150  * Serial Port
 151  */
 152 #define CFG_SYS_NS16550_CLK             get_bus_freq(0)
 153
 154 #define CFG_SYS_BAUDRATE_TABLE \
 155                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 156
 157 #define CFG_SYS_NS16550_COM1    (CONFIG_SYS_IMMR+0x4500)
 158 #define CFG_SYS_NS16550_COM2    (CONFIG_SYS_IMMR+0x4600)
 159
 160 /* SERDES */
 161 #define CONFIG_FSL_SERDES1      0xe3000
 162 #define CONFIG_FSL_SERDES2      0xe3100
 163
 164 /* I2C */
 165 #define CFG_SYS_I2C_NOPROBES            { {0, 0x51} }
 166
 167 /*
 168  * Config on-board RTC
 169  */
 170 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 171 #define CFG_SYS_I2C_RTC_ADDR    0x68 /* at address 0x68 */
 172
 173 /*
 174  * General PCI
 175  * Addresses are mapped 1-1.
 176  */
 177 #define CFG_SYS_PCIE1_CFG_BASE  0xA0000000
 178 #define CFG_SYS_PCIE1_CFG_SIZE  0x08000000
 179 #define CFG_SYS_PCIE1_MEM_PHYS  0xA8000000
 180 #define CFG_SYS_PCIE1_IO_PHYS   0xB8000000
 181
 182 #define CFG_SYS_PCIE2_CFG_BASE  0xC0000000
 183 #define CFG_SYS_PCIE2_CFG_SIZE  0x08000000
 184 #define CFG_SYS_PCIE2_MEM_PHYS  0xC8000000
 185 #define CFG_SYS_PCIE2_IO_PHYS   0xD8000000
 186
 187 /*
 188  * TSEC
 189  */
 190 #ifdef CONFIG_TSEC_ENET
 191
 192 #define CONFIG_GMII                     /* MII PHY management */
 193
 194 #define CONFIG_TSEC1
 195
 196 #ifdef CONFIG_TSEC1
 197 #define CONFIG_TSEC1_NAME               "TSEC0"
 198 #define CFG_SYS_TSEC1_OFFSET            0x24000
 199 #define TSEC1_PHY_ADDR                  2
 200 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 201 #define TSEC1_PHYIDX                    0
 202 #endif
 203
 204 #ifdef CONFIG_TSEC2
 205 #define CONFIG_TSEC2_NAME               "TSEC1"
 206 #define TSEC2_PHY_ADDR                  0x1c
 207 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 208 #define TSEC2_PHYIDX                    0
 209 #endif
 210 #endif
 211
 212 #ifdef CONFIG_MMC
 213 #define CONFIG_FSL_ESDHC_PIN_MUX
 214 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC83xx_ESDHC_ADDR
 215 #endif
 216
 217 /*
 218  * Miscellaneous configurable options
 219  */
 220
 221 /*
 222  * For booting Linux, the board info and command line data
 223  * have to be in the first 256 MB of memory, since this is
 224  * the maximum mapped by the Linux kernel during initialization.
 225  */
 226 #define CFG_SYS_BOOTMAPSZ       (256 << 20) /* Initial Memory map for Linux */
 227
 228 /*
 229  * Environment Configuration
 230  */
 231
 232 #define CONFIG_NETDEV           "eth1"
 233
 234 #define CONFIG_HOSTNAME         "mpc837x_rdb"
 235 #define CONFIG_ROOTPATH         "/nfsroot"
 236                                 /* U-Boot image on TFTP server */
 237 #define CONFIG_UBOOTPATH        "u-boot.bin"
 238 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 239
 240 #define CONFIG_EXTRA_ENV_SETTINGS \
 241         "netdev=" CONFIG_NETDEV "\0"                            \
 242         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 243         "tftpflash=tftp $loadaddr $uboot;"                              \
 244                 "protect off " __stringify(CONFIG_TEXT_BASE)    \
 245                         " +$filesize; " \
 246                 "erase " __stringify(CONFIG_TEXT_BASE)          \
 247                         " +$filesize; " \
 248                 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
 249                         " $filesize; "  \
 250                 "protect on " __stringify(CONFIG_TEXT_BASE)             \
 251                         " +$filesize; " \
 252                 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE)        \
 253                         " $filesize\0"  \
 254         "fdtaddr=780000\0"                                              \
 255         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 256         "ramdiskaddr=1000000\0"                                         \
 257         "ramdiskfile=rootfs.ext2.gz.uboot\0"                            \
 258         "console=ttyS0\0"                                               \
 259         "setbootargs=setenv bootargs "                                  \
 260                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 261         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 262                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 263                                                         "$netdev:off "  \
 264                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 265
 266 #endif  /* __CONFIG_H */