include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <linux/stringify.h>
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16
  17 #define CONFIG_HWCONFIG
  18
  19 /*
  20  * On-board devices
  21  */
  22 #define CONFIG_VSC7385_ENET
  23
  24 /* System performance - define the value i.e. CONFIG_SYS_XXX
  25 */
  26
  27 /* System Clock Configuration Register */
  28 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
  29 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
  30 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  31
  32 /*
  33  * System IO Config
  34  */
  35 #define CONFIG_SYS_SICRH                0x08200000
  36 #define CONFIG_SYS_SICRL                0x00000000
  37
  38 /*
  39  * Output Buffer Impedance
  40  */
  41 #define CONFIG_SYS_OBIR         0x30100000
  42
  43 /*
  44  * Device configurations
  45  */
  46
  47 /* Vitesse 7385 */
  48
  49 #ifdef CONFIG_VSC7385_ENET
  50
  51 #define CONFIG_TSEC2
  52
  53 /* The flash address and size of the VSC7385 firmware image */
  54 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  55 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  56
  57 #endif
  58
  59 /*
  60  * DDR Setup
  61  */
  62 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  63 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
  64
  65 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  66
  67 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
  68
  69 /*
  70  * Manually set up DDR parameters
  71  */
  72 #define CONFIG_SYS_SDRAM_SIZE           0x10000000 /* 256 MiB */
  73 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
  74 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  75                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
  76                                         | CSCONFIG_ROW_BIT_13 \
  77                                         | CSCONFIG_COL_BIT_10)
  78
  79 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  80 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  81                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  82                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  83                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  84                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  85                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  86                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  87                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  88                                 /* 0x00260802 */ /* DDR400 */
  89 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  90                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  91                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  92                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  93                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
  94                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  95                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  96                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  97                                 /* 0x3937d322 */
  98 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  99                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 100                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 101                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 102                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 103                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 104                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 105                                 /* 0x02984cc8 */
 106
 107 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 108                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 109                                 /* 0x06090100 */
 110
 111 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 112                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 113                                         /* 0x43000000 */
 114 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 115 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 116                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 117                                         /* 0x04400442 */ /* DDR400 */
 118 #define CONFIG_SYS_DDR_MODE2            0x00000000
 119
 120 /*
 121  * Memory test
 122  */
 123 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 124
 125 /*
 126  * The reserved memory
 127  */
 128
 129 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 130
 131 /*
 132  * Initial RAM Base Address Setup
 133  */
 134 #define CONFIG_SYS_INIT_RAM_LOCK        1
 135 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 136 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 137
 138 /*
 139  * FLASH on the Local Bus
 140  */
 141 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 142 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 143
 144
 145 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 146
 147 #undef  CONFIG_SYS_FLASH_CHECKSUM
 148 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 149 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 150
 151 /*
 152  * NAND Flash on the Local Bus
 153  */
 154 #define CONFIG_SYS_NAND_BASE    0xE0600000
 155
 156
 157 /* Vitesse 7385 */
 158
 159 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 160
 161 /*
 162  * Serial Port
 163  */
 164 #define CONFIG_SYS_NS16550_SERIAL
 165 #define CONFIG_SYS_NS16550_REG_SIZE     1
 166 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 167
 168 #define CONFIG_SYS_BAUDRATE_TABLE \
 169                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 170
 171 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 172 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 173
 174 /* SERDES */
 175 #define CONFIG_FSL_SERDES
 176 #define CONFIG_FSL_SERDES1      0xe3000
 177 #define CONFIG_FSL_SERDES2      0xe3100
 178
 179 /* I2C */
 180 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 181
 182 /*
 183  * Config on-board RTC
 184  */
 185 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 186 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 187
 188 /*
 189  * General PCI
 190  * Addresses are mapped 1-1.
 191  */
 192 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 193 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 194 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 195 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 196
 197 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 198 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 199 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 200 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 201
 202 /*
 203  * TSEC
 204  */
 205 #ifdef CONFIG_TSEC_ENET
 206
 207 #define CONFIG_GMII                     /* MII PHY management */
 208
 209 #define CONFIG_TSEC1
 210
 211 #ifdef CONFIG_TSEC1
 212 #define CONFIG_TSEC1_NAME               "TSEC0"
 213 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 214 #define TSEC1_PHY_ADDR                  2
 215 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 216 #define TSEC1_PHYIDX                    0
 217 #endif
 218
 219 #ifdef CONFIG_TSEC2
 220 #define CONFIG_TSEC2_NAME               "TSEC1"
 221 #define TSEC2_PHY_ADDR                  0x1c
 222 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 223 #define TSEC2_PHYIDX                    0
 224 #endif
 225 #endif
 226
 227 /*
 228  * Environment
 229  */
 230
 231 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 232 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 233
 234 #ifdef CONFIG_MMC
 235 #define CONFIG_FSL_ESDHC_PIN_MUX
 236 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 237 #endif
 238
 239 /*
 240  * Miscellaneous configurable options
 241  */
 242
 243 /*
 244  * For booting Linux, the board info and command line data
 245  * have to be in the first 256 MB of memory, since this is
 246  * the maximum mapped by the Linux kernel during initialization.
 247  */
 248 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 249
 250 /*
 251  * Environment Configuration
 252  */
 253
 254 #define CONFIG_NETDEV           "eth1"
 255
 256 #define CONFIG_HOSTNAME         "mpc837x_rdb"
 257 #define CONFIG_ROOTPATH         "/nfsroot"
 258                                 /* U-Boot image on TFTP server */
 259 #define CONFIG_UBOOTPATH        "u-boot.bin"
 260 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 261
 262 #define CONFIG_EXTRA_ENV_SETTINGS \
 263         "netdev=" CONFIG_NETDEV "\0"                            \
 264         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 265         "tftpflash=tftp $loadaddr $uboot;"                              \
 266                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 267                         " +$filesize; " \
 268                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 269                         " +$filesize; " \
 270                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 271                         " $filesize; "  \
 272                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 273                         " +$filesize; " \
 274                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 275                         " $filesize\0"  \
 276         "fdtaddr=780000\0"                                              \
 277         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 278         "ramdiskaddr=1000000\0"                                         \
 279         "ramdiskfile=rootfs.ext2.gz.uboot\0"                            \
 280         "console=ttyS0\0"                                               \
 281         "setbootargs=setenv bootargs "                                  \
 282                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 283         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 284                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 285                                                         "$netdev:off "  \
 286                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 287
 288 #endif  /* __CONFIG_H */