include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <linux/stringify.h>
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16
  17 /* System performance - define the value i.e. CONFIG_SYS_XXX
  18 */
  19
  20 /* System Clock Configuration Register */
  21 #define CFG_SYS_SCCR_TSEC1CM    1               /* eTSEC1 clock mode (0-3) */
  22 #define CFG_SYS_SCCR_TSEC2CM    1               /* eTSEC2 clock mode (0-3) */
  23 #define CFG_SYS_SCCR_SATACM     SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  24
  25 /*
  26  * System IO Config
  27  */
  28 #define CFG_SYS_SICRH           0x08200000
  29 #define CFG_SYS_SICRL           0x00000000
  30
  31 /*
  32  * Output Buffer Impedance
  33  */
  34 #define CFG_SYS_OBIR            0x30100000
  35
  36 /*
  37  * Device configurations
  38  */
  39
  40 /* Vitesse 7385 */
  41
  42 #ifdef CONFIG_VSC7385_ENET
  43
  44 /* The flash address and size of the VSC7385 firmware image */
  45 #define CFG_VSC7385_IMAGE               0xFE7FE000
  46 #define CFG_VSC7385_IMAGE_SIZE  8192
  47
  48 #endif
  49
  50 /*
  51  * DDR Setup
  52  */
  53 #define CFG_SYS_SDRAM_BASE              0x00000000 /* DDR is system memory */
  54 #define CFG_SYS_DDR_SDRAM_CLK_CNTL      0x03000000
  55
  56 #define CFG_SYS_DDRCDR_VALUE    (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  57
  58 /*
  59  * Manually set up DDR parameters
  60  */
  61 #define CFG_SYS_SDRAM_SIZE              0x10000000 /* 256 MiB */
  62 #define CFG_SYS_DDR_CS0_BNDS            0x0000000f
  63 #define CFG_SYS_DDR_CS0_CONFIG  (CSCONFIG_EN \
  64                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
  65                                         | CSCONFIG_ROW_BIT_13 \
  66                                         | CSCONFIG_COL_BIT_10)
  67
  68 #define CFG_SYS_DDR_TIMING_3    0x00000000
  69 #define CFG_SYS_DDR_TIMING_0    ((0 << TIMING_CFG0_RWT_SHIFT) \
  70                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  71                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  72                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  73                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  74                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  75                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  76                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  77                                 /* 0x00260802 */ /* DDR400 */
  78 #define CFG_SYS_DDR_TIMING_1    ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  79                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  80                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  81                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  82                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
  83                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  84                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  85                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  86                                 /* 0x3937d322 */
  87 #define CFG_SYS_DDR_TIMING_2    ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  88                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
  89                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  90                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  91                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  92                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  93                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
  94                                 /* 0x02984cc8 */
  95
  96 #define CFG_SYS_DDR_INTERVAL    ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
  97                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  98                                 /* 0x06090100 */
  99
 100 #define CFG_SYS_DDR_SDRAM_CFG   (SDRAM_CFG_SREN \
 101                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 102                                         /* 0x43000000 */
 103 #define CFG_SYS_DDR_SDRAM_CFG2  0x00001000 /* 1 posted refresh */
 104 #define CFG_SYS_DDR_MODE                ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 105                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 106                                         /* 0x04400442 */ /* DDR400 */
 107 #define CFG_SYS_DDR_MODE2               0x00000000
 108
 109 /*
 110  * Memory test
 111  */
 112 #undef CFG_SYS_DRAM_TEST                /* memory test, takes time */
 113
 114 /*
 115  * The reserved memory
 116  */
 117
 118 /*
 119  * Initial RAM Base Address Setup
 120  */
 121 #define CFG_SYS_INIT_RAM_ADDR   0xE6000000 /* Initial RAM address */
 122 #define CFG_SYS_INIT_RAM_SIZE   0x1000 /* Size of used area in RAM */
 123
 124 /*
 125  * FLASH on the Local Bus
 126  */
 127 #define CFG_SYS_FLASH_BASE              0xFE000000 /* FLASH base address */
 128 #define CFG_SYS_FLASH_SIZE              8 /* max FLASH size is 32M */
 129
 130 /*
 131  * NAND Flash on the Local Bus
 132  */
 133 #define CFG_SYS_NAND_BASE       0xE0600000
 134
 135
 136 /* Vitesse 7385 */
 137
 138 #define CFG_SYS_VSC7385_BASE    0xF0000000
 139
 140 /*
 141  * Serial Port
 142  */
 143 #if !CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(DM_CLK)
 144 #define CFG_SYS_NS16550_CLK             get_bus_freq(0)
 145 #endif
 146
 147 #define CFG_SYS_BAUDRATE_TABLE \
 148                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 149
 150 #define CFG_SYS_NS16550_COM1    (CONFIG_SYS_IMMR+0x4500)
 151 #define CFG_SYS_NS16550_COM2    (CONFIG_SYS_IMMR+0x4600)
 152
 153 /* SERDES */
 154 #define CFG_FSL_SERDES1 0xe3000
 155 #define CFG_FSL_SERDES2 0xe3100
 156
 157 /* I2C */
 158 #define CFG_SYS_I2C_NOPROBES            { {0, 0x51} }
 159
 160 /*
 161  * Config on-board RTC
 162  */
 163 #define CFG_SYS_I2C_RTC_ADDR    0x68 /* at address 0x68 */
 164
 165 /*
 166  * General PCI
 167  * Addresses are mapped 1-1.
 168  */
 169 #define CFG_SYS_PCIE1_CFG_BASE  0xA0000000
 170 #define CFG_SYS_PCIE1_CFG_SIZE  0x08000000
 171 #define CFG_SYS_PCIE1_MEM_PHYS  0xA8000000
 172 #define CFG_SYS_PCIE1_IO_PHYS   0xB8000000
 173
 174 #define CFG_SYS_PCIE2_CFG_BASE  0xC0000000
 175 #define CFG_SYS_PCIE2_CFG_SIZE  0x08000000
 176 #define CFG_SYS_PCIE2_MEM_PHYS  0xC8000000
 177 #define CFG_SYS_PCIE2_IO_PHYS   0xD8000000
 178
 179 #ifdef CONFIG_MMC
 180 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC83xx_ESDHC_ADDR
 181 #endif
 182
 183 /*
 184  * Miscellaneous configurable options
 185  */
 186
 187 /*
 188  * For booting Linux, the board info and command line data
 189  * have to be in the first 256 MB of memory, since this is
 190  * the maximum mapped by the Linux kernel during initialization.
 191  */
 192 #define CFG_SYS_BOOTMAPSZ       (256 << 20) /* Initial Memory map for Linux */
 193
 194 /*
 195  * Environment Configuration
 196  */
 197
 198 #define FDTFILE                 "mpc8379_rdb.dtb"
 199
 200 #define CFG_EXTRA_ENV_SETTINGS \
 201         "netdev=eth1\0"                         \
 202         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 203         "tftpflash=tftp $loadaddr $uboot;"                              \
 204                 "protect off " __stringify(CONFIG_TEXT_BASE)    \
 205                         " +$filesize; " \
 206                 "erase " __stringify(CONFIG_TEXT_BASE)          \
 207                         " +$filesize; " \
 208                 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
 209                         " $filesize; "  \
 210                 "protect on " __stringify(CONFIG_TEXT_BASE)             \
 211                         " +$filesize; " \
 212                 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE)        \
 213                         " $filesize\0"  \
 214         "fdtaddr=780000\0"                                              \
 215         "fdtfile=" FDTFILE "\0"                                 \
 216         "ramdiskaddr=1000000\0"                                         \
 217         "ramdiskfile=rootfs.ext2.gz.uboot\0"                            \
 218         "console=ttyS0\0"                                               \
 219         "setbootargs=setenv bootargs "                                  \
 220                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 221         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 222                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 223                                                         "$netdev:off "  \
 224                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 225
 226 #endif  /* __CONFIG_H */