0f3e01d015daa7e2ec74a4e9f48d90a3b03c6256
[platform/kernel/u-boot.git] / include / configs / MPC837XEMDS.h
1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Dave Liu <daveliu@freescale.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #ifndef __CONFIG_H
9 #define __CONFIG_H
10
11 /*
12  * High Level Configuration Options
13  */
14 #define CONFIG_E300             1 /* E300 family */
15 #define CONFIG_MPC837x          1 /* MPC837x CPU specific */
16 #define CONFIG_MPC837XEMDS      1 /* MPC837XEMDS board specific */
17
18 #define CONFIG_SYS_TEXT_BASE    0xFE000000
19
20 /*
21  * System Clock Setup
22  */
23 #ifdef CONFIG_PCISLAVE
24 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
25 #else
26 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
27 #endif
28
29 #ifndef CONFIG_SYS_CLK_FREQ
30 #define CONFIG_SYS_CLK_FREQ     66000000
31 #endif
32
33 /*
34  * Hardware Reset Configuration Word
35  * if CLKIN is 66MHz, then
36  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
37  */
38 #define CONFIG_SYS_HRCW_LOW (\
39         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
40         HRCWL_DDR_TO_SCB_CLK_1X1 |\
41         HRCWL_SVCOD_DIV_2 |\
42         HRCWL_CSB_TO_CLKIN_6X1 |\
43         HRCWL_CORE_TO_CSB_1_5X1)
44
45 #ifdef CONFIG_PCISLAVE
46 #define CONFIG_SYS_HRCW_HIGH (\
47         HRCWH_PCI_AGENT |\
48         HRCWH_PCI1_ARBITER_DISABLE |\
49         HRCWH_CORE_ENABLE |\
50         HRCWH_FROM_0XFFF00100 |\
51         HRCWH_BOOTSEQ_DISABLE |\
52         HRCWH_SW_WATCHDOG_DISABLE |\
53         HRCWH_ROM_LOC_LOCAL_16BIT |\
54         HRCWH_RL_EXT_LEGACY |\
55         HRCWH_TSEC1M_IN_RGMII |\
56         HRCWH_TSEC2M_IN_RGMII |\
57         HRCWH_BIG_ENDIAN |\
58         HRCWH_LDP_CLEAR)
59 #else
60 #define CONFIG_SYS_HRCW_HIGH (\
61         HRCWH_PCI_HOST |\
62         HRCWH_PCI1_ARBITER_ENABLE |\
63         HRCWH_CORE_ENABLE |\
64         HRCWH_FROM_0X00000100 |\
65         HRCWH_BOOTSEQ_DISABLE |\
66         HRCWH_SW_WATCHDOG_DISABLE |\
67         HRCWH_ROM_LOC_LOCAL_16BIT |\
68         HRCWH_RL_EXT_LEGACY |\
69         HRCWH_TSEC1M_IN_RGMII |\
70         HRCWH_TSEC2M_IN_RGMII |\
71         HRCWH_BIG_ENDIAN |\
72         HRCWH_LDP_CLEAR)
73 #endif
74
75 /* Arbiter Configuration Register */
76 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth is 4 */
77 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count is 4 */
78
79 /* System Priority Control Register */
80 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC1/2 emergency has highest priority */
81
82 /*
83  * IP blocks clock configuration
84  */
85 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
86 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
87 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
88
89 /*
90  * System IO Config
91  */
92 #define CONFIG_SYS_SICRH                0x00000000
93 #define CONFIG_SYS_SICRL                0x00000000
94
95 /*
96  * Output Buffer Impedance
97  */
98 #define CONFIG_SYS_OBIR         0x31100000
99
100 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
101 #define CONFIG_BOARD_EARLY_INIT_R
102 #define CONFIG_HWCONFIG
103
104 /*
105  * IMMR new address
106  */
107 #define CONFIG_SYS_IMMR         0xE0000000
108
109 /*
110  * DDR Setup
111  */
112 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
113 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
114 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
115 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
116 #define CONFIG_SYS_83XX_DDR_USES_CS0
117 #define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_DHC_EN \
118                                         | DDRCDR_ODT \
119                                         | DDRCDR_Q_DRN)
120                                         /* 0x80080001 */ /* ODT 150ohm on SoC */
121
122 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
123 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
124
125 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
126 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
127
128 #if defined(CONFIG_SPD_EEPROM)
129 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
130 #else
131 /*
132  * Manually set up DDR parameters
133  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
134  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
135  */
136 #define CONFIG_SYS_DDR_SIZE             512 /* MB */
137 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
138 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
139                         | CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
140                         | CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
141                         | CSCONFIG_ROW_BIT_14 \
142                         | CSCONFIG_COL_BIT_10)
143                         /* 0x80010202 */
144 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
145 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
146                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
147                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
148                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
149                                 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
150                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
151                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
152                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
153                                 /* 0x00620802 */
154 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
155                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
156                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
157                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
158                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
159                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
160                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
161                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
162                                 /* 0x3935d322 */
163 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
164                                 | (6 << TIMING_CFG2_CPO_SHIFT) \
165                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
166                                 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
167                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
168                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
169                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
170                                 /* 0x131088c8 */
171 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
172                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
173                                 /* 0x03E00100 */
174 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
175 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
176 #define CONFIG_SYS_DDR_MODE     ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
177                                 | (0x1432 << SDRAM_MODE_SD_SHIFT))
178                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
179 #define CONFIG_SYS_DDR_MODE2    0x00000000
180 #endif
181
182 /*
183  * Memory test
184  */
185 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
186 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
187 #define CONFIG_SYS_MEMTEST_END          0x00140000
188
189 /*
190  * The reserved memory
191  */
192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
193
194 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
195 #define CONFIG_SYS_RAMBOOT
196 #else
197 #undef CONFIG_SYS_RAMBOOT
198 #endif
199
200 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
201 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
202 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
203
204 /*
205  * Initial RAM Base Address Setup
206  */
207 #define CONFIG_SYS_INIT_RAM_LOCK        1
208 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
209 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
210 #define CONFIG_SYS_GBL_DATA_OFFSET      \
211                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
212
213 /*
214  * Local Bus Configuration & Clock Setup
215  */
216 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
217 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
218 #define CONFIG_SYS_LBC_LBCR             0x00000000
219 #define CONFIG_FSL_ELBC         1
220
221 /*
222  * FLASH on the Local Bus
223  */
224 #define CONFIG_SYS_FLASH_CFI    /* use the Common Flash Interface */
225 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
226 #define CONFIG_SYS_FLASH_BASE   0xFE000000 /* FLASH base address */
227 #define CONFIG_SYS_FLASH_SIZE   32 /* max FLASH size is 32M */
228 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
229
230                                         /* Window base at flash base */
231 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
232 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
233
234 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
235                                 | BR_PS_16      /* 16 bit port */ \
236                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
237                                 | BR_V)         /* valid */
238 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
239                                 | OR_UPM_XAM \
240                                 | OR_GPCM_CSNT \
241                                 | OR_GPCM_ACS_DIV2 \
242                                 | OR_GPCM_XACS \
243                                 | OR_GPCM_SCY_15 \
244                                 | OR_GPCM_TRLX_SET \
245                                 | OR_GPCM_EHTR_SET \
246                                 | OR_GPCM_EAD)
247                                 /* 0xFE000FF7 */
248
249 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
250 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
251
252 #undef CONFIG_SYS_FLASH_CHECKSUM
253 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
254 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
255
256 /*
257  * BCSR on the Local Bus
258  */
259 #define CONFIG_SYS_BCSR         0xF8000000
260                                         /* Access window base at BCSR base */
261 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
262 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
263
264 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_BCSR \
265                                 | BR_PS_8 \
266                                 | BR_MS_GPCM \
267                                 | BR_V)
268                                 /* 0xF8000801 */
269 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
270                                 | OR_GPCM_XAM \
271                                 | OR_GPCM_CSNT \
272                                 | OR_GPCM_XACS \
273                                 | OR_GPCM_SCY_15 \
274                                 | OR_GPCM_TRLX_SET \
275                                 | OR_GPCM_EHTR_SET \
276                                 | OR_GPCM_EAD)
277                                 /* 0xFFFFE9F7 */
278
279 /*
280  * NAND Flash on the Local Bus
281  */
282 #define CONFIG_CMD_NAND         1
283 #define CONFIG_SYS_MAX_NAND_DEVICE      1
284 #define CONFIG_NAND_FSL_ELBC    1
285
286 #define CONFIG_SYS_NAND_BASE    0xE0600000
287 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE \
288                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
289                                 | BR_PS_8               /* 8 bit port */ \
290                                 | BR_MS_FCM             /* MSEL = FCM */ \
291                                 | BR_V)                 /* valid */
292 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_32KB \
293                                 | OR_FCM_BCTLD \
294                                 | OR_FCM_CST \
295                                 | OR_FCM_CHT \
296                                 | OR_FCM_SCY_1 \
297                                 | OR_FCM_RST \
298                                 | OR_FCM_TRLX \
299                                 | OR_FCM_EHTR)
300                                 /* 0xFFFF919E */
301
302 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_NAND_BASE
303 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
304
305 /*
306  * Serial Port
307  */
308 #define CONFIG_CONS_INDEX       1
309 #define CONFIG_SYS_NS16550_SERIAL
310 #define CONFIG_SYS_NS16550_REG_SIZE     1
311 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
312
313 #define CONFIG_SYS_BAUDRATE_TABLE  \
314                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
315
316 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
317 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
318
319 /* I2C */
320 #define CONFIG_SYS_I2C
321 #define CONFIG_SYS_I2C_FSL
322 #define CONFIG_SYS_FSL_I2C_SPEED        400000
323 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
324 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
325 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
326
327 /*
328  * Config on-board RTC
329  */
330 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
331 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
332
333 /*
334  * General PCI
335  * Addresses are mapped 1-1.
336  */
337 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
338 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
339 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
340 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
341 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
342 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
343 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
344 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
345 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
346
347 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
348 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
349 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
350
351 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
352 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
353 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
354 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
355 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
356 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
357 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
358 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
359 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
360
361 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
362 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
363 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
364 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
365 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
366 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
367 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
368 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
369 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
370
371 #ifdef CONFIG_PCI
372 #define CONFIG_PCI_INDIRECT_BRIDGE
373 #ifndef __ASSEMBLY__
374 extern int board_pci_host_broken(void);
375 #endif
376 #define CONFIG_PCIE
377 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
378
379 #define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
380 #define CONFIG_USB_EHCI
381 #define CONFIG_USB_EHCI_FSL
382 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
383
384 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
385
386 #undef CONFIG_EEPRO100
387 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
388 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
389 #endif /* CONFIG_PCI */
390
391 /*
392  * TSEC
393  */
394 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
395 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
396 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
397 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
398 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
399
400 /*
401  * TSEC ethernet configuration
402  */
403 #define CONFIG_MII              1 /* MII PHY management */
404 #define CONFIG_TSEC1            1
405 #define CONFIG_TSEC1_NAME       "eTSEC0"
406 #define CONFIG_TSEC2            1
407 #define CONFIG_TSEC2_NAME       "eTSEC1"
408 #define TSEC1_PHY_ADDR          2
409 #define TSEC2_PHY_ADDR          3
410 #define TSEC1_PHY_ADDR_SGMII    8
411 #define TSEC2_PHY_ADDR_SGMII    4
412 #define TSEC1_PHYIDX            0
413 #define TSEC2_PHYIDX            0
414 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
415 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
416
417 /* Options are: TSEC[0-1] */
418 #define CONFIG_ETHPRIME         "eTSEC1"
419
420 /* SERDES */
421 #define CONFIG_FSL_SERDES
422 #define CONFIG_FSL_SERDES1      0xe3000
423 #define CONFIG_FSL_SERDES2      0xe3100
424
425 /*
426  * SATA
427  */
428 #define CONFIG_LIBATA
429 #define CONFIG_FSL_SATA
430
431 #define CONFIG_SYS_SATA_MAX_DEVICE      2
432 #define CONFIG_SATA1
433 #define CONFIG_SYS_SATA1_OFFSET 0x18000
434 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
435 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
436 #define CONFIG_SATA2
437 #define CONFIG_SYS_SATA2_OFFSET 0x19000
438 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
439 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
440
441 #ifdef CONFIG_FSL_SATA
442 #define CONFIG_LBA48
443 #define CONFIG_CMD_SATA
444 #define CONFIG_DOS_PARTITION
445 #endif
446
447 /*
448  * Environment
449  */
450 #ifndef CONFIG_SYS_RAMBOOT
451         #define CONFIG_ENV_IS_IN_FLASH  1
452         #define CONFIG_ENV_ADDR         \
453                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
454         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
455         #define CONFIG_ENV_SIZE         0x2000
456 #else
457         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
458         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
459         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
460         #define CONFIG_ENV_SIZE         0x2000
461 #endif
462
463 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
464 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
465
466 /*
467  * BOOTP options
468  */
469 #define CONFIG_BOOTP_BOOTFILESIZE
470 #define CONFIG_BOOTP_BOOTPATH
471 #define CONFIG_BOOTP_GATEWAY
472 #define CONFIG_BOOTP_HOSTNAME
473
474 /*
475  * Command line configuration.
476  */
477 #define CONFIG_CMD_DATE
478
479 #if defined(CONFIG_PCI)
480     #define CONFIG_CMD_PCI
481 #endif
482
483 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
484 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
485
486 #undef CONFIG_WATCHDOG          /* watchdog disabled */
487
488 #define CONFIG_MMC     1
489
490 #ifdef CONFIG_MMC
491 #define CONFIG_FSL_ESDHC
492 #define CONFIG_FSL_ESDHC_PIN_MUX
493 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
494 #define CONFIG_GENERIC_MMC
495 #define CONFIG_DOS_PARTITION
496 #endif
497
498 /*
499  * Miscellaneous configurable options
500  */
501 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
502 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
503
504 #if defined(CONFIG_CMD_KGDB)
505         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
506 #else
507         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
508 #endif
509
510                                 /* Print Buffer Size */
511 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
512 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
513                                 /* Boot Argument Buffer Size */
514 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
515
516 /*
517  * For booting Linux, the board info and command line data
518  * have to be in the first 256 MB of memory, since this is
519  * the maximum mapped by the Linux kernel during initialization.
520  */
521 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
522 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
523
524 /*
525  * Core HID Setup
526  */
527 #define CONFIG_SYS_HID0_INIT    0x000000000
528 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
529                                  HID0_ENABLE_INSTRUCTION_CACHE)
530 #define CONFIG_SYS_HID2         HID2_HBE
531
532 /*
533  * MMU Setup
534  */
535 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
536
537 /* DDR: cache cacheable */
538 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
539 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
540
541 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
542                                 | BATL_PP_RW \
543                                 | BATL_MEMCOHERENCE)
544 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
545                                 | BATU_BL_256M \
546                                 | BATU_VS \
547                                 | BATU_VP)
548 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
549 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
550
551 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
552                                 | BATL_PP_RW \
553                                 | BATL_MEMCOHERENCE)
554 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
555                                 | BATU_BL_256M \
556                                 | BATU_VS \
557                                 | BATU_VP)
558 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
559 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
560
561 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
562 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
563                                 | BATL_PP_RW \
564                                 | BATL_CACHEINHIBIT \
565                                 | BATL_GUARDEDSTORAGE)
566 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
567                                 | BATU_BL_8M \
568                                 | BATU_VS \
569                                 | BATU_VP)
570 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
571 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
572
573 /* BCSR: cache-inhibit and guarded */
574 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_BCSR \
575                                 | BATL_PP_RW \
576                                 | BATL_CACHEINHIBIT \
577                                 | BATL_GUARDEDSTORAGE)
578 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_BCSR \
579                                 | BATU_BL_128K \
580                                 | BATU_VS \
581                                 | BATU_VP)
582 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
583 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
584
585 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
586 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
587                                 | BATL_PP_RW \
588                                 | BATL_MEMCOHERENCE)
589 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
590                                 | BATU_BL_32M \
591                                 | BATU_VS \
592                                 | BATU_VP)
593 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
594                                 | BATL_PP_RW \
595                                 | BATL_CACHEINHIBIT \
596                                 | BATL_GUARDEDSTORAGE)
597 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
598
599 /* Stack in dcache: cacheable, no memory coherence */
600 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
601 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
602                                 | BATU_BL_128K \
603                                 | BATU_VS \
604                                 | BATU_VP)
605 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
606 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
607
608 #ifdef CONFIG_PCI
609 /* PCI MEM space: cacheable */
610 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
611                                 | BATL_PP_RW \
612                                 | BATL_MEMCOHERENCE)
613 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
614                                 | BATU_BL_256M \
615                                 | BATU_VS \
616                                 | BATU_VP)
617 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
618 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
619 /* PCI MMIO space: cache-inhibit and guarded */
620 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
621                                 | BATL_PP_RW \
622                                 | BATL_CACHEINHIBIT \
623                                 | BATL_GUARDEDSTORAGE)
624 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
625                                 | BATU_BL_256M \
626                                 | BATU_VS \
627                                 | BATU_VP)
628 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
629 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
630 #else
631 #define CONFIG_SYS_IBAT6L       (0)
632 #define CONFIG_SYS_IBAT6U       (0)
633 #define CONFIG_SYS_IBAT7L       (0)
634 #define CONFIG_SYS_IBAT7U       (0)
635 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
636 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
637 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
638 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
639 #endif
640
641 #if defined(CONFIG_CMD_KGDB)
642 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
643 #endif
644
645 /*
646  * Environment Configuration
647  */
648
649 #define CONFIG_ENV_OVERWRITE
650
651 #if defined(CONFIG_TSEC_ENET)
652 #define CONFIG_HAS_ETH0
653 #define CONFIG_HAS_ETH1
654 #endif
655
656 #define CONFIG_BAUDRATE 115200
657
658 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
659
660 #undef CONFIG_BOOTARGS          /* the boot command will set bootargs */
661
662 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
663         "netdev=eth0\0"                                                 \
664         "consoledev=ttyS0\0"                                            \
665         "ramdiskaddr=1000000\0"                                         \
666         "ramdiskfile=ramfs.83xx\0"                                      \
667         "fdtaddr=780000\0"                                              \
668         "fdtfile=mpc8379_mds.dtb\0"                                     \
669         ""
670
671 #define CONFIG_NFSBOOTCOMMAND                                           \
672         "setenv bootargs root=/dev/nfs rw "                             \
673                 "nfsroot=$serverip:$rootpath "                          \
674                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
675                                                         "$netdev:off "  \
676                 "console=$consoledev,$baudrate $othbootargs;"           \
677         "tftp $loadaddr $bootfile;"                                     \
678         "tftp $fdtaddr $fdtfile;"                                       \
679         "bootm $loadaddr - $fdtaddr"
680
681 #define CONFIG_RAMBOOTCOMMAND                                           \
682         "setenv bootargs root=/dev/ram rw "                             \
683                 "console=$consoledev,$baudrate $othbootargs;"           \
684         "tftp $ramdiskaddr $ramdiskfile;"                               \
685         "tftp $loadaddr $bootfile;"                                     \
686         "tftp $fdtaddr $fdtfile;"                                       \
687         "bootm $loadaddr $ramdiskaddr $fdtaddr"
688
689 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
690
691 #endif  /* __CONFIG_H */