include/configs/MPC8349ITX.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
   9
  10  Memory map:
  11
  12  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  13  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  14  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  15  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  16  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  17  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  18  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  19  0xF001_0000-0xF001_FFFF Local bus expansion slot
  20  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  21  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  22  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  23
  24  I2C address list:
  25                                                 Align.  Board
  26  Bus    Addr    Part No.        Description     Length  Location
  27  ----------------------------------------------------------------
  28  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  29
  30  I2C1   0x20    PCF8574         I2C Expander    0       U8
  31  I2C1   0x21    PCF8574         I2C Expander    0       U10
  32  I2C1   0x38    PCF8574A        I2C Expander    0       U8
  33  I2C1   0x39    PCF8574A        I2C Expander    0       U10
  34  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  35  I2C1   0x68    DS1339          RTC             1       U68
  36
  37  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  38 */
  39
  40 #ifndef __CONFIG_H
  41 #define __CONFIG_H
  42
  43 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
  44 #define CONFIG_SYS_LOWBOOT
  45 #endif
  46
  47 /*
  48  * High Level Configuration Options
  49  */
  50 #define CONFIG_MPC834x          /* MPC834x family (8343, 8347, 8349) */
  51 #define CONFIG_MPC8349          /* MPC8349 specific */
  52
  53 #ifndef CONFIG_SYS_TEXT_BASE
  54 #define CONFIG_SYS_TEXT_BASE    0xFEF00000
  55 #endif
  56
  57 #define CONFIG_SYS_IMMR 0xE0000000      /* The IMMR is relocated to here */
  58
  59 #define CONFIG_MISC_INIT_F
  60 #define CONFIG_MISC_INIT_R
  61
  62 /*
  63  * On-board devices
  64  */
  65
  66 #ifdef CONFIG_MPC8349ITX
  67 /* The CF card interface on the back of the board */
  68 #define CONFIG_COMPACT_FLASH
  69 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  70 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  71 #endif
  72
  73 #define CONFIG_RTC_DS1337
  74 #define CONFIG_SYS_I2C
  75 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
  76
  77 /*
  78  * Device configurations
  79  */
  80
  81 /* I2C */
  82 #ifdef CONFIG_SYS_I2C
  83 #define CONFIG_SYS_I2C_FSL
  84 #define CONFIG_SYS_FSL_I2C_SPEED        400000
  85 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  86 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
  87 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
  88 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
  89 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
  90
  91 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
  92 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
  93
  94 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
  95 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
  96 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
  97 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
  98 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
  99 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
 100 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
 101
 102 /* Don't probe these addresses: */
 103 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
 104                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
 105                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
 106                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
 107 /* Bit definitions for the 8574[A] I2C expander */
 108                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
 109 #define I2C_8574_REVISION       0x03
 110 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
 111 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
 112 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
 113 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
 114
 115 #endif
 116
 117 /* Compact Flash */
 118 #ifdef CONFIG_COMPACT_FLASH
 119
 120 #define CONFIG_SYS_IDE_MAXBUS           1
 121 #define CONFIG_SYS_IDE_MAXDEVICE        1
 122
 123 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 124 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 125 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 126 #define CONFIG_SYS_ATA_REG_OFFSET       0
 127 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 128 #define CONFIG_SYS_ATA_STRIDE           2
 129
 130 /* If a CF card is not inserted, time out quickly */
 131 #define ATA_RESET_TIME  1
 132
 133 #endif
 134
 135 /*
 136  * SATA
 137  */
 138 #ifdef CONFIG_SATA_SIL3114
 139
 140 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 141 #define CONFIG_LIBATA
 142 #define CONFIG_LBA48
 143
 144 #endif
 145
 146 #ifdef CONFIG_SYS_USB_HOST
 147 /*
 148  * Support USB
 149  */
 150 #define CONFIG_USB_EHCI_FSL
 151
 152 /* Current USB implementation supports the only USB controller,
 153  * so we have to choose between the MPH or the DR ones */
 154 #if 1
 155 #define CONFIG_HAS_FSL_MPH_USB
 156 #else
 157 #define CONFIG_HAS_FSL_DR_USB
 158 #endif
 159
 160 #endif
 161
 162 /*
 163  * DDR Setup
 164  */
 165 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 166 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 167 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 168 #define CONFIG_SYS_83XX_DDR_USES_CS0
 169 #define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
 170 #define CONFIG_SYS_MEMTEST_END          0x2000
 171
 172 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 173                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 174
 175 #define CONFIG_VERY_BIG_RAM
 176 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 177
 178 #ifdef CONFIG_SYS_I2C
 179 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 180 #endif
 181
 182 /* No SPD? Then manually set up DDR parameters */
 183 #ifndef CONFIG_SPD_EEPROM
 184     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 185     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 186                                         | CSCONFIG_ROW_BIT_13 \
 187                                         | CSCONFIG_COL_BIT_10)
 188
 189     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 190     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 191 #endif
 192
 193 /*
 194  *Flash on the Local Bus
 195  */
 196
 197 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 198 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 199 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 200 #define CONFIG_SYS_FLASH_EMPTY_INFO
 201 /* 127 64KB sectors + 8 8KB sectors per device */
 202 #define CONFIG_SYS_MAX_FLASH_SECT       135
 203 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 204 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 205 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 206
 207 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 208 boards, we say we have two, but don't display a message if we find only one. */
 209 #define CONFIG_SYS_FLASH_QUIET_TEST
 210 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 211 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 212                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 213 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 214 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 215
 216 /* Vitesse 7385 */
 217
 218 #ifdef CONFIG_VSC7385_ENET
 219
 220 #define CONFIG_TSEC2
 221
 222 /* The flash address and size of the VSC7385 firmware image */
 223 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
 224 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 225
 226 #endif
 227
 228 /*
 229  * BRx, ORx, LBLAWBARx, and LBLAWARx
 230  */
 231
 232 /* Flash */
 233
 234 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 235                                 | BR_PS_16 \
 236                                 | BR_MS_GPCM \
 237                                 | BR_V)
 238 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 239                                 | OR_UPM_XAM \
 240                                 | OR_GPCM_CSNT \
 241                                 | OR_GPCM_ACS_DIV2 \
 242                                 | OR_GPCM_XACS \
 243                                 | OR_GPCM_SCY_15 \
 244                                 | OR_GPCM_TRLX_SET \
 245                                 | OR_GPCM_EHTR_SET \
 246                                 | OR_GPCM_EAD)
 247 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 248 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 249
 250 /* Vitesse 7385 */
 251
 252 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
 253
 254 #ifdef CONFIG_VSC7385_ENET
 255
 256 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_VSC7385_BASE \
 257                                 | BR_PS_8 \
 258                                 | BR_MS_GPCM \
 259                                 | BR_V)
 260 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128KB \
 261                                 | OR_GPCM_CSNT \
 262                                 | OR_GPCM_XACS \
 263                                 | OR_GPCM_SCY_15 \
 264                                 | OR_GPCM_SETA \
 265                                 | OR_GPCM_TRLX_SET \
 266                                 | OR_GPCM_EHTR_SET \
 267                                 | OR_GPCM_EAD)
 268
 269 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_VSC7385_BASE
 270 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 271
 272 #endif
 273
 274 /* LED */
 275
 276 #define CONFIG_SYS_LED_BASE     0xF9000000
 277 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_LED_BASE \
 278                                 | BR_PS_8 \
 279                                 | BR_MS_GPCM \
 280                                 | BR_V)
 281 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_2MB \
 282                                 | OR_GPCM_CSNT \
 283                                 | OR_GPCM_ACS_DIV2 \
 284                                 | OR_GPCM_XACS \
 285                                 | OR_GPCM_SCY_9 \
 286                                 | OR_GPCM_TRLX_SET \
 287                                 | OR_GPCM_EHTR_SET \
 288                                 | OR_GPCM_EAD)
 289
 290 /* Compact Flash */
 291
 292 #ifdef CONFIG_COMPACT_FLASH
 293
 294 #define CONFIG_SYS_CF_BASE      0xF0000000
 295
 296 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_CF_BASE \
 297                                 | BR_PS_16 \
 298                                 | BR_MS_UPMA \
 299                                 | BR_V)
 300 #define CONFIG_SYS_OR3_PRELIM   (OR_UPM_AM | OR_UPM_BI)
 301
 302 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CF_BASE
 303 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 304
 305 #endif
 306
 307 /*
 308  * U-Boot memory configuration
 309  */
 310 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 311
 312 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 313 #define CONFIG_SYS_RAMBOOT
 314 #else
 315 #undef  CONFIG_SYS_RAMBOOT
 316 #endif
 317
 318 #define CONFIG_SYS_INIT_RAM_LOCK
 319 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 320 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 321
 322 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 323                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 324 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 325
 326 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 327 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 328 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 329
 330 /*
 331  * Local Bus LCRR and LBCR regs
 332  *    LCRR:  DLL bypass, Clock divider is 4
 333  * External Local Bus rate is
 334  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 335  */
 336 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 337 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 338 #define CONFIG_SYS_LBC_LBCR     0x00000000
 339
 340                                 /* LB sdram refresh timer, about 6us */
 341 #define CONFIG_SYS_LBC_LSRT     0x32000000
 342                                 /* LB refresh timer prescal, 266MHz/32*/
 343 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 344
 345 /*
 346  * Serial Port
 347  */
 348 #define CONFIG_CONS_INDEX       1
 349 #define CONFIG_SYS_NS16550_SERIAL
 350 #define CONFIG_SYS_NS16550_REG_SIZE     1
 351 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 352
 353 #define CONFIG_SYS_BAUDRATE_TABLE  \
 354                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 355
 356 #define CONSOLE                 ttyS0
 357
 358 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 359 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 360
 361 /*
 362  * PCI
 363  */
 364 #ifdef CONFIG_PCI
 365 #define CONFIG_PCI_INDIRECT_BRIDGE
 366
 367 #define CONFIG_MPC83XX_PCI2
 368
 369 /*
 370  * General PCI
 371  * Addresses are mapped 1-1.
 372  */
 373 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 374 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 375 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 376 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 377                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 378 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 379 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 380 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 381 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 382 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 383
 384 #ifdef CONFIG_MPC83XX_PCI2
 385 #define CONFIG_SYS_PCI2_MEM_BASE        \
 386                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 387 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 388 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 389 #define CONFIG_SYS_PCI2_MMIO_BASE       \
 390                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 391 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 392 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 393 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 394 #define CONFIG_SYS_PCI2_IO_PHYS         \
 395                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 396 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 397 #endif
 398
 399 #ifndef CONFIG_PCI_PNP
 400     #define PCI_ENET0_IOADDR    0x00000000
 401     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 402     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 403 #endif
 404
 405 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 406
 407 #endif
 408
 409 #define CONFIG_PCI_66M
 410 #ifdef CONFIG_PCI_66M
 411 #define CONFIG_83XX_CLKIN       66666666        /* in Hz */
 412 #else
 413 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
 414 #endif
 415
 416 /* TSEC */
 417
 418 #ifdef CONFIG_TSEC_ENET
 419
 420 #define CONFIG_MII
 421
 422 #define CONFIG_TSEC1
 423
 424 #ifdef CONFIG_TSEC1
 425 #define CONFIG_HAS_ETH0
 426 #define CONFIG_TSEC1_NAME  "TSEC0"
 427 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 428 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 429 #define TSEC1_PHYIDX            0
 430 #define TSEC1_FLAGS             TSEC_GIGABIT
 431 #endif
 432
 433 #ifdef CONFIG_TSEC2
 434 #define CONFIG_HAS_ETH1
 435 #define CONFIG_TSEC2_NAME  "TSEC1"
 436 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 437
 438 #define TSEC2_PHY_ADDR          4
 439 #define TSEC2_PHYIDX            0
 440 #define TSEC2_FLAGS             TSEC_GIGABIT
 441 #endif
 442
 443 #define CONFIG_ETHPRIME         "Freescale TSEC"
 444
 445 #endif
 446
 447 /*
 448  * Environment
 449  */
 450 #define CONFIG_ENV_OVERWRITE
 451
 452 #ifndef CONFIG_SYS_RAMBOOT
 453   #define CONFIG_ENV_ADDR       \
 454                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 455   #define CONFIG_ENV_SECT_SIZE  0x10000 /* 64K (one sector) for environment */
 456   #define CONFIG_ENV_SIZE       0x2000
 457 #else
 458   #undef  CONFIG_FLASH_CFI_DRIVER
 459   #define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE - 0x1000)
 460   #define CONFIG_ENV_SIZE       0x2000
 461 #endif
 462
 463 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 464 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 465
 466 /*
 467  * BOOTP options
 468  */
 469 #define CONFIG_BOOTP_BOOTFILESIZE
 470 #define CONFIG_BOOTP_BOOTPATH
 471 #define CONFIG_BOOTP_GATEWAY
 472 #define CONFIG_BOOTP_HOSTNAME
 473
 474 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
 475                                 || defined(CONFIG_USB_STORAGE)
 476         #define CONFIG_SUPPORT_VFAT
 477 #endif
 478
 479 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
 480 #endif
 481
 482 /* Watchdog */
 483 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 484
 485 /*
 486  * Miscellaneous configurable options
 487  */
 488 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 489 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 490 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 491
 492 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 493 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 494
 495 /*
 496  * For booting Linux, the board info and command line data
 497  * have to be in the first 256 MB of memory, since this is
 498  * the maximum mapped by the Linux kernel during initialization.
 499  */
 500                                 /* Initial Memory map for Linux*/
 501 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 502 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 503
 504 #define CONFIG_SYS_HRCW_LOW (\
 505         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 506         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 507         HRCWL_CSB_TO_CLKIN_4X1 |\
 508         HRCWL_VCO_1X2 |\
 509         HRCWL_CORE_TO_CSB_2X1)
 510
 511 #ifdef CONFIG_SYS_LOWBOOT
 512 #define CONFIG_SYS_HRCW_HIGH (\
 513         HRCWH_PCI_HOST |\
 514         HRCWH_32_BIT_PCI |\
 515         HRCWH_PCI1_ARBITER_ENABLE |\
 516         HRCWH_PCI2_ARBITER_ENABLE |\
 517         HRCWH_CORE_ENABLE |\
 518         HRCWH_FROM_0X00000100 |\
 519         HRCWH_BOOTSEQ_DISABLE |\
 520         HRCWH_SW_WATCHDOG_DISABLE |\
 521         HRCWH_ROM_LOC_LOCAL_16BIT |\
 522         HRCWH_TSEC1M_IN_GMII |\
 523         HRCWH_TSEC2M_IN_GMII)
 524 #else
 525 #define CONFIG_SYS_HRCW_HIGH (\
 526         HRCWH_PCI_HOST |\
 527         HRCWH_32_BIT_PCI |\
 528         HRCWH_PCI1_ARBITER_ENABLE |\
 529         HRCWH_PCI2_ARBITER_ENABLE |\
 530         HRCWH_CORE_ENABLE |\
 531         HRCWH_FROM_0XFFF00100 |\
 532         HRCWH_BOOTSEQ_DISABLE |\
 533         HRCWH_SW_WATCHDOG_DISABLE |\
 534         HRCWH_ROM_LOC_LOCAL_16BIT |\
 535         HRCWH_TSEC1M_IN_GMII |\
 536         HRCWH_TSEC2M_IN_GMII)
 537 #endif
 538
 539 /*
 540  * System performance
 541  */
 542 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 543 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 544 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 545 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 546 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 547 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 548 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 549 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 550
 551 /*
 552  * System IO Config
 553  */
 554 /* Needed for gigabit to work on TSEC 1 */
 555 #define CONFIG_SYS_SICRH SICRH_TSOBI1
 556                                 /* USB DR as device + USB MPH as host */
 557 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 558
 559 #define CONFIG_SYS_HID0_INIT    0x00000000
 560 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_INSTRUCTION_CACHE
 561
 562 #define CONFIG_SYS_HID2 HID2_HBE
 563 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 564
 565 /* DDR  */
 566 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 567                                 | BATL_PP_RW \
 568                                 | BATL_MEMCOHERENCE)
 569 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 570                                 | BATU_BL_256M \
 571                                 | BATU_VS \
 572                                 | BATU_VP)
 573
 574 /* PCI  */
 575 #ifdef CONFIG_PCI
 576 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 577                                 | BATL_PP_RW \
 578                                 | BATL_MEMCOHERENCE)
 579 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 580                                 | BATU_BL_256M \
 581                                 | BATU_VS \
 582                                 | BATU_VP)
 583 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 584                                 | BATL_PP_RW \
 585                                 | BATL_CACHEINHIBIT \
 586                                 | BATL_GUARDEDSTORAGE)
 587 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 588                                 | BATU_BL_256M \
 589                                 | BATU_VS \
 590                                 | BATU_VP)
 591 #else
 592 #define CONFIG_SYS_IBAT1L       0
 593 #define CONFIG_SYS_IBAT1U       0
 594 #define CONFIG_SYS_IBAT2L       0
 595 #define CONFIG_SYS_IBAT2U       0
 596 #endif
 597
 598 #ifdef CONFIG_MPC83XX_PCI2
 599 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 600                                 | BATL_PP_RW \
 601                                 | BATL_MEMCOHERENCE)
 602 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 603                                 | BATU_BL_256M \
 604                                 | BATU_VS \
 605                                 | BATU_VP)
 606 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 607                                 | BATL_PP_RW \
 608                                 | BATL_CACHEINHIBIT \
 609                                 | BATL_GUARDEDSTORAGE)
 610 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 611                                 | BATU_BL_256M \
 612                                 | BATU_VS \
 613                                 | BATU_VP)
 614 #else
 615 #define CONFIG_SYS_IBAT3L       0
 616 #define CONFIG_SYS_IBAT3U       0
 617 #define CONFIG_SYS_IBAT4L       0
 618 #define CONFIG_SYS_IBAT4U       0
 619 #endif
 620
 621 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 622 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 623                                 | BATL_PP_RW \
 624                                 | BATL_CACHEINHIBIT \
 625                                 | BATL_GUARDEDSTORAGE)
 626 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 627                                 | BATU_BL_256M \
 628                                 | BATU_VS \
 629                                 | BATU_VP)
 630
 631 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 632 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 633                                 | BATL_PP_RW \
 634                                 | BATL_MEMCOHERENCE \
 635                                 | BATL_GUARDEDSTORAGE)
 636 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 637                                 | BATU_BL_256M \
 638                                 | BATU_VS \
 639                                 | BATU_VP)
 640
 641 #define CONFIG_SYS_IBAT7L       0
 642 #define CONFIG_SYS_IBAT7U       0
 643
 644 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 645 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 646 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 647 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 648 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 649 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 650 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 651 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 652 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 653 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 654 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 655 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 656 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 657 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 658 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 659 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 660
 661 #if defined(CONFIG_CMD_KGDB)
 662 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 663 #endif
 664
 665 /*
 666  * Environment Configuration
 667  */
 668 #define CONFIG_ENV_OVERWRITE
 669
 670 #define CONFIG_NETDEV           "eth0"
 671
 672 /* Default path and filenames */
 673 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 674 #define CONFIG_BOOTFILE         "uImage"
 675                                 /* U-Boot image on TFTP server */
 676 #define CONFIG_UBOOTPATH        "u-boot.bin"
 677
 678 #ifdef CONFIG_MPC8349ITX
 679 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 680 #else
 681 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 682 #endif
 683
 684
 685 #define CONFIG_EXTRA_ENV_SETTINGS \
 686         "console=" __stringify(CONSOLE) "\0"                    \
 687         "netdev=" CONFIG_NETDEV "\0"                                    \
 688         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 689         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 690                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 691                         " +$filesize; " \
 692                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 693                         " +$filesize; " \
 694                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 695                         " $filesize; "  \
 696                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 697                         " +$filesize; " \
 698                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 699                         " $filesize\0"  \
 700         "fdtaddr=780000\0"                                              \
 701         "fdtfile=" CONFIG_FDTFILE "\0"
 702
 703 #define CONFIG_NFSBOOTCOMMAND                                           \
 704         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 705         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 706         " console=$console,$baudrate $othbootargs; "                    \
 707         "tftp $loadaddr $bootfile;"                                     \
 708         "tftp $fdtaddr $fdtfile;"                                       \
 709         "bootm $loadaddr - $fdtaddr"
 710
 711 #define CONFIG_RAMBOOTCOMMAND                                           \
 712         "setenv bootargs root=/dev/ram rw"                              \
 713         " console=$console,$baudrate $othbootargs; "                    \
 714         "tftp $ramdiskaddr $ramdiskfile;"                               \
 715         "tftp $loadaddr $bootfile;"                                     \
 716         "tftp $fdtaddr $fdtfile;"                                       \
 717         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 718
 719 #endif