1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
7 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
17 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
18 0xF001_0000-0xF001_FFFF Local bus expansion slot
19 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
25 Bus Addr Part No. Description Length Location
26 ----------------------------------------------------------------
27 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
29 I2C1 0x20 PCF8574 I2C Expander 0 U8
30 I2C1 0x21 PCF8574 I2C Expander 0 U10
31 I2C1 0x38 PCF8574A I2C Expander 0 U8
32 I2C1 0x39 PCF8574A I2C Expander 0 U10
33 I2C1 0x51 (DDR) DDR EEPROM 1 U1
34 I2C1 0x68 DS1339 RTC 1 U68
36 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
46 #ifdef CONFIG_TARGET_MPC8349ITX
47 /* The CF card interface on the back of the board */
48 #define CONFIG_COMPACT_FLASH
49 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
50 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
53 #include <linux/stringify.h>
54 #define CONFIG_RTC_DS1337
55 #define CONFIG_SYS_I2C
58 * Device configurations
63 #define CONFIG_SYS_I2C_FSL
64 #define CONFIG_SYS_FSL_I2C_SPEED 400000
65 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
66 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
67 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
68 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
69 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
71 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
72 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
74 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
75 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
76 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
77 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
78 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
79 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
80 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
82 /* Don't probe these addresses: */
83 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
84 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
85 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
86 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
87 /* Bit definitions for the 8574[A] I2C expander */
88 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
89 #define I2C_8574_REVISION 0x03
90 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
91 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
92 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
93 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
98 #ifdef CONFIG_COMPACT_FLASH
100 #define CONFIG_SYS_IDE_MAXBUS 1
101 #define CONFIG_SYS_IDE_MAXDEVICE 1
103 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
104 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
105 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
106 #define CONFIG_SYS_ATA_REG_OFFSET 0
107 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
108 #define CONFIG_SYS_ATA_STRIDE 2
110 /* If a CF card is not inserted, time out quickly */
111 #define ATA_RESET_TIME 1
118 #ifdef CONFIG_SATA_SIL3114
120 #define CONFIG_SYS_SATA_MAX_DEVICE 4
125 #ifdef CONFIG_SYS_USB_HOST
129 #define CONFIG_USB_EHCI_FSL
131 /* Current USB implementation supports the only USB controller,
132 * so we have to choose between the MPH or the DR ones */
134 #define CONFIG_HAS_FSL_MPH_USB
136 #define CONFIG_HAS_FSL_DR_USB
144 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
145 #define CONFIG_SYS_83XX_DDR_USES_CS0
147 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
148 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
150 #define CONFIG_VERY_BIG_RAM
151 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
153 #ifdef CONFIG_SYS_I2C
154 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
157 /* No SPD? Then manually set up DDR parameters */
158 #ifndef CONFIG_SPD_EEPROM
159 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
160 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
161 | CSCONFIG_ROW_BIT_13 \
162 | CSCONFIG_COL_BIT_10)
164 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
165 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
169 *Flash on the Local Bus
172 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
173 #define CONFIG_SYS_FLASH_EMPTY_INFO
174 /* 127 64KB sectors + 8 8KB sectors per device */
175 #define CONFIG_SYS_MAX_FLASH_SECT 135
176 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
177 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
178 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
180 /* The ITX has two flash chips, but the ITX-GP has only one. To support both
181 boards, we say we have two, but don't display a message if we find only one. */
182 #define CONFIG_SYS_FLASH_QUIET_TEST
183 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
184 #define CONFIG_SYS_FLASH_BANKS_LIST \
185 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
186 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
190 #ifdef CONFIG_VSC7385_ENET
194 /* The flash address and size of the VSC7385 firmware image */
195 #define CONFIG_VSC7385_IMAGE 0xFEFFE000
196 #define CONFIG_VSC7385_IMAGE_SIZE 8192
201 * BRx, ORx, LBLAWBARx, and LBLAWARx
207 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
209 #define CONFIG_SYS_LED_BASE 0xF9000000
214 #ifdef CONFIG_COMPACT_FLASH
216 #define CONFIG_SYS_CF_BASE 0xF0000000
222 * U-Boot memory configuration
224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
226 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
227 #define CONFIG_SYS_RAMBOOT
229 #undef CONFIG_SYS_RAMBOOT
232 #define CONFIG_SYS_INIT_RAM_LOCK
233 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
234 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
236 #define CONFIG_SYS_GBL_DATA_OFFSET \
237 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
238 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
240 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
241 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
242 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
247 #define CONFIG_SYS_NS16550_SERIAL
248 #define CONFIG_SYS_NS16550_REG_SIZE 1
249 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
251 #define CONFIG_SYS_BAUDRATE_TABLE \
252 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
254 #define CONSOLE ttyS0
256 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
257 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
263 #define CONFIG_PCI_INDIRECT_BRIDGE
265 #define CONFIG_MPC83XX_PCI2
269 * Addresses are mapped 1-1.
271 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
272 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
273 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
274 #define CONFIG_SYS_PCI1_MMIO_BASE \
275 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
276 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
277 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
278 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
279 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
280 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
282 #ifdef CONFIG_MPC83XX_PCI2
283 #define CONFIG_SYS_PCI2_MEM_BASE \
284 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
285 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
286 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
287 #define CONFIG_SYS_PCI2_MMIO_BASE \
288 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
289 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
290 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
291 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
292 #define CONFIG_SYS_PCI2_IO_PHYS \
293 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
294 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
297 #ifndef CONFIG_PCI_PNP
298 #define PCI_ENET0_IOADDR 0x00000000
299 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
300 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
303 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
309 #ifdef CONFIG_TSEC_ENET
313 #define CONFIG_HAS_ETH0
314 #define CONFIG_TSEC1_NAME "TSEC0"
315 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
316 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
317 #define TSEC1_PHYIDX 0
318 #define TSEC1_FLAGS TSEC_GIGABIT
322 #define CONFIG_HAS_ETH1
323 #define CONFIG_TSEC2_NAME "TSEC1"
324 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
326 #define TSEC2_PHY_ADDR 4
327 #define TSEC2_PHYIDX 0
328 #define TSEC2_FLAGS TSEC_GIGABIT
331 #define CONFIG_ETHPRIME "Freescale TSEC"
339 #define CONFIG_LOADS_ECHO /* echo on for serial download */
340 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
345 #define CONFIG_BOOTP_BOOTFILESIZE
348 #undef CONFIG_WATCHDOG /* watchdog disabled */
351 * Miscellaneous configurable options
354 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
355 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
358 * For booting Linux, the board info and command line data
359 * have to be in the first 256 MB of memory, since this is
360 * the maximum mapped by the Linux kernel during initialization.
362 /* Initial Memory map for Linux*/
363 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
364 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
369 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
370 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
371 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
372 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
377 /* Needed for gigabit to work on TSEC 1 */
378 #define CONFIG_SYS_SICRH SICRH_TSOBI1
379 /* USB DR as device + USB MPH as host */
380 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
382 #if defined(CONFIG_CMD_KGDB)
383 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
387 * Environment Configuration
390 #define CONFIG_NETDEV "eth0"
392 /* Default path and filenames */
393 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
394 #define CONFIG_BOOTFILE "uImage"
395 /* U-Boot image on TFTP server */
396 #define CONFIG_UBOOTPATH "u-boot.bin"
398 #ifdef CONFIG_TARGET_MPC8349ITX
399 #define CONFIG_FDTFILE "mpc8349emitx.dtb"
401 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
405 #define CONFIG_EXTRA_ENV_SETTINGS \
406 "console=" __stringify(CONSOLE) "\0" \
407 "netdev=" CONFIG_NETDEV "\0" \
408 "uboot=" CONFIG_UBOOTPATH "\0" \
409 "tftpflash=tftpboot $loadaddr $uboot; " \
410 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
412 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
414 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
416 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
418 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
421 "fdtfile=" CONFIG_FDTFILE "\0"
423 #define CONFIG_NFSBOOTCOMMAND \
424 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
425 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
426 " console=$console,$baudrate $othbootargs; " \
427 "tftp $loadaddr $bootfile;" \
428 "tftp $fdtaddr $fdtfile;" \
429 "bootm $loadaddr - $fdtaddr"
431 #define CONFIG_RAMBOOTCOMMAND \
432 "setenv bootargs root=/dev/ram rw" \
433 " console=$console,$baudrate $othbootargs; " \
434 "tftp $ramdiskaddr $ramdiskfile;" \
435 "tftp $loadaddr $bootfile;" \
436 "tftp $fdtaddr $fdtfile;" \
437 "bootm $loadaddr $ramdiskaddr $fdtaddr"