1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2010
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * mpc8349emds board configuration file
16 * High Level Configuration Options
18 #define CONFIG_E300 1 /* E300 Family */
20 #define CONFIG_SYS_IMMR 0xE0000000
22 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
23 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
24 #define CONFIG_SYS_MEMTEST_END 0x00100000
29 #define CONFIG_DDR_ECC /* support DDR ECC function */
30 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
31 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
34 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
35 * unselect it to use old spd_sdram.c
37 #define CONFIG_SYS_SPD_BUS_NUM 0
38 #define SPD_EEPROM_ADDRESS1 0x52
39 #define SPD_EEPROM_ADDRESS2 0x51
40 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
41 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
42 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
43 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
46 * 32-bit data path mode.
48 * Please note that using this mode for devices with the real density of 64-bit
49 * effectively reduces the amount of available memory due to the effect of
50 * wrapping around while translating address to row/columns, for example in the
51 * 256MB module the upper 128MB get aliased with contents of the lower
52 * 128MB); normally this define should be used for devices with real 32-bit
55 #undef CONFIG_DDR_32BIT
57 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
58 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
59 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
60 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
61 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
62 #undef CONFIG_DDR_2T_TIMING
65 * DDRCDR - DDR Control Driver Register
67 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
69 #if defined(CONFIG_SPD_EEPROM)
71 * Determine DDR configuration from I2C interface.
73 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
76 * Manually set up DDR parameters
78 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
79 #if defined(CONFIG_DDR_II)
80 #define CONFIG_SYS_DDRCDR 0x80080001
81 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
82 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
83 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
84 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
85 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
86 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
87 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
88 #define CONFIG_SYS_DDR_MODE 0x47d00432
89 #define CONFIG_SYS_DDR_MODE2 0x8000c000
90 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
91 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
92 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
94 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
95 | CSCONFIG_ROW_BIT_13 \
96 | CSCONFIG_COL_BIT_10)
97 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
99 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
100 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
102 #if defined(CONFIG_DDR_32BIT)
103 /* set burst length to 8 for 32-bit data path */
104 /* DLL,normal,seq,4/2.5, 8 burst len */
105 #define CONFIG_SYS_DDR_MODE 0x00000023
107 /* the default burst length is 4 - for 64-bit data path */
108 /* DLL,normal,seq,4/2.5, 4 burst len */
109 #define CONFIG_SYS_DDR_MODE 0x00000022
115 * SDRAM on the Local Bus
117 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
118 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
121 * FLASH on the Local Bus
123 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
124 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
126 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
127 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
129 #undef CONFIG_SYS_FLASH_CHECKSUM
130 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
131 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
135 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
136 #define CONFIG_SYS_RAMBOOT
138 #undef CONFIG_SYS_RAMBOOT
142 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
144 #define CONFIG_SYS_BCSR 0xE2400000
145 /* Access window base at BCSR base */
146 #define CONFIG_SYS_INIT_RAM_LOCK 1
147 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
148 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
150 #define CONFIG_SYS_GBL_DATA_OFFSET \
151 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
152 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
154 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
155 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
158 * Local Bus LCRR and LBCR regs
159 * LCRR: DLL bypass, Clock divider is 4
160 * External Local Bus rate is
161 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
163 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
164 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
165 #define CONFIG_SYS_LBC_LBCR 0x00000000
168 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
171 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
173 * Base Register 2 and Option Register 2 configure SDRAM.
174 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
177 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
178 * port-size = 32-bits = BR2[19:20] = 11
179 * no parity checking = BR2[21:22] = 00
180 * SDRAM for MSEL = BR2[24:26] = 011
183 * 0 4 8 12 16 20 24 28
184 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
188 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
191 * 64MB mask for AM, OR2[0:7] = 1111 1100
192 * XAM, OR2[17:18] = 11
193 * 9 columns OR2[19-21] = 010
194 * 13 rows OR2[23-25] = 100
195 * EAD set for extra time OR[31] = 1
197 * 0 4 8 12 16 20 24 28
198 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
202 /* LB sdram refresh timer, about 6us */
203 #define CONFIG_SYS_LBC_LSRT 0x32000000
204 /* LB refresh timer prescal, 266MHz/32 */
205 #define CONFIG_SYS_LBC_MRTPR 0x20000000
207 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
217 * SDRAM Controller configuration sequence.
219 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
220 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
221 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
222 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
223 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
228 #define CONFIG_SYS_NS16550_SERIAL
229 #define CONFIG_SYS_NS16550_REG_SIZE 1
230 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
232 #define CONFIG_SYS_BAUDRATE_TABLE \
233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
235 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
236 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
239 #define CONFIG_SYS_I2C
240 #define CONFIG_SYS_I2C_FSL
241 #define CONFIG_SYS_FSL_I2C_SPEED 400000
242 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
243 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
244 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
245 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
246 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
247 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
250 #undef CONFIG_SOFT_SPI /* SPI bit-banged */
252 /* GPIOs. Used as SPI chip selects */
253 #define CONFIG_SYS_GPIO1_PRELIM
254 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
255 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
258 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
259 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
260 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
261 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
264 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
268 * Addresses are mapped 1-1.
270 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
271 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
272 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
273 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
274 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
275 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
276 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
277 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
278 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
280 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
281 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
282 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
283 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
284 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
285 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
286 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
287 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
288 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
290 #if defined(CONFIG_PCI)
292 #define CONFIG_83XX_PCI_STREAMING
294 #undef CONFIG_EEPRO100
297 #if !defined(CONFIG_PCI_PNP)
298 #define PCI_ENET0_IOADDR 0xFIXME
299 #define PCI_ENET0_MEMADDR 0xFIXME
300 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
303 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
304 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
306 #endif /* CONFIG_PCI */
312 #if defined(CONFIG_TSEC_ENET)
314 #define CONFIG_GMII 1 /* MII PHY management */
315 #define CONFIG_TSEC1 1
316 #define CONFIG_TSEC1_NAME "TSEC0"
317 #define CONFIG_TSEC2 1
318 #define CONFIG_TSEC2_NAME "TSEC1"
319 #define TSEC1_PHY_ADDR 0
320 #define TSEC2_PHY_ADDR 1
321 #define TSEC1_PHYIDX 0
322 #define TSEC2_PHYIDX 0
323 #define TSEC1_FLAGS TSEC_GIGABIT
324 #define TSEC2_FLAGS TSEC_GIGABIT
326 /* Options are: TSEC[0-1] */
327 #define CONFIG_ETHPRIME "TSEC0"
329 #endif /* CONFIG_TSEC_ENET */
332 * Configure on-board RTC
334 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
335 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
340 #ifndef CONFIG_SYS_RAMBOOT
341 #define CONFIG_ENV_ADDR \
342 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
343 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
344 #define CONFIG_ENV_SIZE 0x2000
346 /* Address and size of Redundant Environment Sector */
347 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
348 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
351 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
352 #define CONFIG_ENV_SIZE 0x2000
355 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
356 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
361 #define CONFIG_BOOTP_BOOTFILESIZE
364 * Command line configuration.
367 #undef CONFIG_WATCHDOG /* watchdog disabled */
370 * Miscellaneous configurable options
372 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
375 * For booting Linux, the board info and command line data
376 * have to be in the first 256 MB of memory, since this is
377 * the maximum mapped by the Linux kernel during initialization.
379 /* Initial Memory map for Linux*/
380 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
381 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
383 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
388 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
389 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
390 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
391 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
392 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
393 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
395 /* System IO Config */
396 #define CONFIG_SYS_SICRH 0
397 #define CONFIG_SYS_SICRL SICRL_LDP_A
400 #define CONFIG_PCI_INDIRECT_BRIDGE
403 #if defined(CONFIG_CMD_KGDB)
404 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
408 * Environment Configuration
410 #define CONFIG_ENV_OVERWRITE
412 #if defined(CONFIG_TSEC_ENET)
413 #define CONFIG_HAS_ETH1
414 #define CONFIG_HAS_ETH0
417 #define CONFIG_HOSTNAME "mpc8349emds"
418 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
419 #define CONFIG_BOOTFILE "uImage"
421 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
423 #define CONFIG_PREBOOT "echo;" \
424 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
427 #define CONFIG_EXTRA_ENV_SETTINGS \
429 "hostname=mpc8349emds\0" \
430 "nfsargs=setenv bootargs root=/dev/nfs rw " \
431 "nfsroot=${serverip}:${rootpath}\0" \
432 "ramargs=setenv bootargs root=/dev/ram rw\0" \
433 "addip=setenv bootargs ${bootargs} " \
434 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
435 ":${hostname}:${netdev}:off panic=1\0" \
436 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
437 "flash_nfs=run nfsargs addip addtty;" \
438 "bootm ${kernel_addr}\0" \
439 "flash_self=run ramargs addip addtty;" \
440 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
441 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
443 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
444 "update=protect off fe000000 fe03ffff; " \
445 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
446 "upd=run load update\0" \
448 "fdtfile=mpc834x_mds.dtb\0" \
451 #define CONFIG_NFSBOOTCOMMAND \
452 "setenv bootargs root=/dev/nfs rw " \
453 "nfsroot=$serverip:$rootpath " \
454 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
456 "console=$consoledev,$baudrate $othbootargs;" \
457 "tftp $loadaddr $bootfile;" \
458 "tftp $fdtaddr $fdtfile;" \
459 "bootm $loadaddr - $fdtaddr"
461 #define CONFIG_RAMBOOTCOMMAND \
462 "setenv bootargs root=/dev/ram rw " \
463 "console=$consoledev,$baudrate $othbootargs;" \
464 "tftp $ramdiskaddr $ramdiskfile;" \
465 "tftp $loadaddr $bootfile;" \
466 "tftp $fdtaddr $fdtfile;" \
467 "bootm $loadaddr $ramdiskaddr $fdtaddr"
469 #define CONFIG_BOOTCOMMAND "run flash_self"
471 #endif /* __CONFIG_H */