include/configs/MPC8349EMDS_SDRAM.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2006-2010
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  */
   6
   7 /*
   8  * mpc8349emds board configuration file
   9  *
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1       /* E300 Family */
  19
  20 #define CONFIG_PCI_66M
  21 #ifdef CONFIG_PCI_66M
  22 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  23 #else
  24 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  25 #endif
  26
  27 #ifdef CONFIG_PCISLAVE
  28 #define CONFIG_83XX_PCICLK      66666666        /* in Hz */
  29 #endif /* CONFIG_PCISLAVE */
  30
  31 #ifndef CONFIG_SYS_CLK_FREQ
  32 #ifdef CONFIG_PCI_66M
  33 #define CONFIG_SYS_CLK_FREQ     66000000
  34 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  35 #else
  36 #define CONFIG_SYS_CLK_FREQ     33000000
  37 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  38 #endif
  39 #endif
  40
  41 #define CONFIG_SYS_IMMR         0xE0000000
  42
  43 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  44 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  45 #define CONFIG_SYS_MEMTEST_END          0x00100000
  46
  47 /*
  48  * DDR Setup
  49  */
  50 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  51 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  52 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  53
  54 /*
  55  * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  56  * unselect it to use old spd_sdram.c
  57  */
  58 #define CONFIG_SYS_SPD_BUS_NUM  0
  59 #define SPD_EEPROM_ADDRESS1     0x52
  60 #define SPD_EEPROM_ADDRESS2     0x51
  61 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  62 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  63 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  64 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  65
  66 /*
  67  * 32-bit data path mode.
  68  *
  69  * Please note that using this mode for devices with the real density of 64-bit
  70  * effectively reduces the amount of available memory due to the effect of
  71  * wrapping around while translating address to row/columns, for example in the
  72  * 256MB module the upper 128MB get aliased with contents of the lower
  73  * 128MB); normally this define should be used for devices with real 32-bit
  74  * data path.
  75  */
  76 #undef CONFIG_DDR_32BIT
  77
  78 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory*/
  79 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  80 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  81 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  82                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  83 #undef  CONFIG_DDR_2T_TIMING
  84
  85 /*
  86  * DDRCDR - DDR Control Driver Register
  87  */
  88 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  89
  90 #if defined(CONFIG_SPD_EEPROM)
  91 /*
  92  * Determine DDR configuration from I2C interface.
  93  */
  94 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  95 #else
  96 /*
  97  * Manually set up DDR parameters
  98  */
  99 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 100 #if defined(CONFIG_DDR_II)
 101 #define CONFIG_SYS_DDRCDR               0x80080001
 102 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
 103 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
 104 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
 105 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
 106 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
 107 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 108 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
 109 #define CONFIG_SYS_DDR_MODE             0x47d00432
 110 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 111 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
 112 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 113 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 114 #else
 115 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
 116                                 | CSCONFIG_ROW_BIT_13 \
 117                                 | CSCONFIG_COL_BIT_10)
 118 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 119 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 120 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 121 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 122
 123 #if defined(CONFIG_DDR_32BIT)
 124 /* set burst length to 8 for 32-bit data path */
 125                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 126 #define CONFIG_SYS_DDR_MODE     0x00000023
 127 #else
 128 /* the default burst length is 4 - for 64-bit data path */
 129                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 130 #define CONFIG_SYS_DDR_MODE     0x00000022
 131 #endif
 132 #endif
 133 #endif
 134
 135 /*
 136  * SDRAM on the Local Bus
 137  */
 138 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 139 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 140
 141 /*
 142  * FLASH on the Local Bus
 143  */
 144 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 145 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 146
 147 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 148                                 | BR_PS_16      /* 16 bit port  */ \
 149                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 150                                 | BR_V)         /* valid */
 151 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 152                                 | OR_UPM_XAM \
 153                                 | OR_GPCM_CSNT \
 154                                 | OR_GPCM_ACS_DIV2 \
 155                                 | OR_GPCM_XACS \
 156                                 | OR_GPCM_SCY_15 \
 157                                 | OR_GPCM_TRLX_SET \
 158                                 | OR_GPCM_EHTR_SET \
 159                                 | OR_GPCM_EAD)
 160
 161                                         /* window base at flash base */
 162 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 163 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 164
 165 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 166 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 167
 168 #undef CONFIG_SYS_FLASH_CHECKSUM
 169 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 170 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 171
 172 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 173
 174 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 175 #define CONFIG_SYS_RAMBOOT
 176 #else
 177 #undef  CONFIG_SYS_RAMBOOT
 178 #endif
 179
 180 /*
 181  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 182  */
 183 #define CONFIG_SYS_BCSR                 0xE2400000
 184                                         /* Access window base at BCSR base */
 185 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 186 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 187 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 188                                         | BR_PS_8 \
 189                                         | BR_MS_GPCM \
 190                                         | BR_V)
 191                                         /* 0x00000801 */
 192 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 193                                         | OR_GPCM_XAM \
 194                                         | OR_GPCM_CSNT \
 195                                         | OR_GPCM_SCY_15 \
 196                                         | OR_GPCM_TRLX_CLEAR \
 197                                         | OR_GPCM_EHTR_CLEAR)
 198                                         /* 0xFFFFE8F0 */
 199
 200 #define CONFIG_SYS_INIT_RAM_LOCK        1
 201 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 202 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 203
 204 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 205                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 206 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 207
 208 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 209 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 210
 211 /*
 212  * Local Bus LCRR and LBCR regs
 213  *    LCRR:  DLL bypass, Clock divider is 4
 214  * External Local Bus rate is
 215  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 216  */
 217 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 218 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 219 #define CONFIG_SYS_LBC_LBCR     0x00000000
 220
 221 /*
 222  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 223  */
 224
 225 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 226 /*
 227  * Base Register 2 and Option Register 2 configure SDRAM.
 228  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 229  *
 230  * For BR2, need:
 231  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 232  *    port-size = 32-bits = BR2[19:20] = 11
 233  *    no parity checking = BR2[21:22] = 00
 234  *    SDRAM for MSEL = BR2[24:26] = 011
 235  *    Valid = BR[31] = 1
 236  *
 237  * 0    4    8    12   16   20   24   28
 238  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 239  */
 240
 241 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 242                                         | BR_PS_32      /* 32-bit port */ \
 243                                         | BR_MS_SDRAM   /* MSEL = SDRAM */ \
 244                                         | BR_V)         /* Valid */
 245                                         /* 0xF0001861 */
 246 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 247 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 248
 249 /*
 250  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 251  *
 252  * For OR2, need:
 253  *    64MB mask for AM, OR2[0:7] = 1111 1100
 254  *                 XAM, OR2[17:18] = 11
 255  *    9 columns OR2[19-21] = 010
 256  *    13 rows   OR2[23-25] = 100
 257  *    EAD set for extra time OR[31] = 1
 258  *
 259  * 0    4    8    12   16   20   24   28
 260  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 261  */
 262
 263 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_64MB \
 264                         | OR_SDRAM_XAM \
 265                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 266                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 267                         | OR_SDRAM_EAD)
 268                         /* 0xFC006901 */
 269
 270                                 /* LB sdram refresh timer, about 6us */
 271 #define CONFIG_SYS_LBC_LSRT     0x32000000
 272                                 /* LB refresh timer prescal, 266MHz/32 */
 273 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 274
 275 #define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN      \
 276                                 | LSDMR_BSMA1516        \
 277                                 | LSDMR_RFCR8           \
 278                                 | LSDMR_PRETOACT6       \
 279                                 | LSDMR_ACTTORW3        \
 280                                 | LSDMR_BL8             \
 281                                 | LSDMR_WRC3            \
 282                                 | LSDMR_CL3)
 283
 284 /*
 285  * SDRAM Controller configuration sequence.
 286  */
 287 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 288 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 289 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 290 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 291 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 292
 293 /*
 294  * Serial Port
 295  */
 296 #define CONFIG_SYS_NS16550_SERIAL
 297 #define CONFIG_SYS_NS16550_REG_SIZE    1
 298 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 299
 300 #define CONFIG_SYS_BAUDRATE_TABLE  \
 301                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 302
 303 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 304 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 305
 306 /* I2C */
 307 #define CONFIG_SYS_I2C
 308 #define CONFIG_SYS_I2C_FSL
 309 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 310 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 311 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 312 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 313 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 314 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 315 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 316
 317 /* SPI */
 318 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 319
 320 /* GPIOs.  Used as SPI chip selects */
 321 #define CONFIG_SYS_GPIO1_PRELIM
 322 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 323 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 324
 325 /* TSEC */
 326 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 327 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 328 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 329 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 330
 331 /* USB */
 332 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 333
 334 /*
 335  * General PCI
 336  * Addresses are mapped 1-1.
 337  */
 338 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 339 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 340 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 341 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 342 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 343 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 344 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 345 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 346 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 347
 348 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 349 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 350 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 351 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 352 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 353 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 354 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 355 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 356 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 357
 358 #if defined(CONFIG_PCI)
 359
 360 #define CONFIG_83XX_PCI_STREAMING
 361
 362 #undef CONFIG_EEPRO100
 363 #undef CONFIG_TULIP
 364
 365 #if !defined(CONFIG_PCI_PNP)
 366         #define PCI_ENET0_IOADDR        0xFIXME
 367         #define PCI_ENET0_MEMADDR       0xFIXME
 368         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 369 #endif
 370
 371 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 372 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 373
 374 #endif  /* CONFIG_PCI */
 375
 376 /*
 377  * TSEC configuration
 378  */
 379
 380 #if defined(CONFIG_TSEC_ENET)
 381
 382 #define CONFIG_GMII             1       /* MII PHY management */
 383 #define CONFIG_TSEC1            1
 384 #define CONFIG_TSEC1_NAME       "TSEC0"
 385 #define CONFIG_TSEC2            1
 386 #define CONFIG_TSEC2_NAME       "TSEC1"
 387 #define TSEC1_PHY_ADDR          0
 388 #define TSEC2_PHY_ADDR          1
 389 #define TSEC1_PHYIDX            0
 390 #define TSEC2_PHYIDX            0
 391 #define TSEC1_FLAGS             TSEC_GIGABIT
 392 #define TSEC2_FLAGS             TSEC_GIGABIT
 393
 394 /* Options are: TSEC[0-1] */
 395 #define CONFIG_ETHPRIME         "TSEC0"
 396
 397 #endif  /* CONFIG_TSEC_ENET */
 398
 399 /*
 400  * Configure on-board RTC
 401  */
 402 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 403 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 404
 405 /*
 406  * Environment
 407  */
 408 #ifndef CONFIG_SYS_RAMBOOT
 409         #define CONFIG_ENV_ADDR         \
 410                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 411         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 412         #define CONFIG_ENV_SIZE         0x2000
 413
 414 /* Address and size of Redundant Environment Sector     */
 415 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 416 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 417
 418 #else
 419         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 420         #define CONFIG_ENV_SIZE         0x2000
 421 #endif
 422
 423 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 424 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 425
 426 /*
 427  * BOOTP options
 428  */
 429 #define CONFIG_BOOTP_BOOTFILESIZE
 430
 431 /*
 432  * Command line configuration.
 433  */
 434
 435 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 436
 437 /*
 438  * Miscellaneous configurable options
 439  */
 440 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 441
 442 /*
 443  * For booting Linux, the board info and command line data
 444  * have to be in the first 256 MB of memory, since this is
 445  * the maximum mapped by the Linux kernel during initialization.
 446  */
 447                                 /* Initial Memory map for Linux*/
 448 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 449 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 450
 451 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 452
 453 #if 1 /*528/264*/
 454 #define CONFIG_SYS_HRCW_LOW (\
 455         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 456         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 457         HRCWL_CSB_TO_CLKIN |\
 458         HRCWL_VCO_1X2 |\
 459         HRCWL_CORE_TO_CSB_2X1)
 460 #elif 0 /*396/132*/
 461 #define CONFIG_SYS_HRCW_LOW (\
 462         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 463         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 464         HRCWL_CSB_TO_CLKIN |\
 465         HRCWL_VCO_1X4 |\
 466         HRCWL_CORE_TO_CSB_3X1)
 467 #elif 0 /*264/132*/
 468 #define CONFIG_SYS_HRCW_LOW (\
 469         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 470         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 471         HRCWL_CSB_TO_CLKIN |\
 472         HRCWL_VCO_1X4 |\
 473         HRCWL_CORE_TO_CSB_2X1)
 474 #elif 0 /*132/132*/
 475 #define CONFIG_SYS_HRCW_LOW (\
 476         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 477         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 478         HRCWL_CSB_TO_CLKIN |\
 479         HRCWL_VCO_1X4 |\
 480         HRCWL_CORE_TO_CSB_1X1)
 481 #elif 0 /*264/264 */
 482 #define CONFIG_SYS_HRCW_LOW (\
 483         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 484         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 485         HRCWL_CSB_TO_CLKIN |\
 486         HRCWL_VCO_1X4 |\
 487         HRCWL_CORE_TO_CSB_1X1)
 488 #endif
 489
 490 #ifdef CONFIG_PCISLAVE
 491 #define CONFIG_SYS_HRCW_HIGH (\
 492         HRCWH_PCI_AGENT |\
 493         HRCWH_64_BIT_PCI |\
 494         HRCWH_PCI1_ARBITER_DISABLE |\
 495         HRCWH_PCI2_ARBITER_DISABLE |\
 496         HRCWH_CORE_ENABLE |\
 497         HRCWH_FROM_0X00000100 |\
 498         HRCWH_BOOTSEQ_DISABLE |\
 499         HRCWH_SW_WATCHDOG_DISABLE |\
 500         HRCWH_ROM_LOC_LOCAL_16BIT |\
 501         HRCWH_TSEC1M_IN_GMII |\
 502         HRCWH_TSEC2M_IN_GMII)
 503 #else
 504 #if defined(CONFIG_PCI_64BIT)
 505 #define CONFIG_SYS_HRCW_HIGH (\
 506         HRCWH_PCI_HOST |\
 507         HRCWH_64_BIT_PCI |\
 508         HRCWH_PCI1_ARBITER_ENABLE |\
 509         HRCWH_PCI2_ARBITER_DISABLE |\
 510         HRCWH_CORE_ENABLE |\
 511         HRCWH_FROM_0X00000100 |\
 512         HRCWH_BOOTSEQ_DISABLE |\
 513         HRCWH_SW_WATCHDOG_DISABLE |\
 514         HRCWH_ROM_LOC_LOCAL_16BIT |\
 515         HRCWH_TSEC1M_IN_GMII |\
 516         HRCWH_TSEC2M_IN_GMII)
 517 #else
 518 #define CONFIG_SYS_HRCW_HIGH (\
 519         HRCWH_PCI_HOST |\
 520         HRCWH_32_BIT_PCI |\
 521         HRCWH_PCI1_ARBITER_ENABLE |\
 522         HRCWH_PCI2_ARBITER_ENABLE |\
 523         HRCWH_CORE_ENABLE |\
 524         HRCWH_FROM_0X00000100 |\
 525         HRCWH_BOOTSEQ_DISABLE |\
 526         HRCWH_SW_WATCHDOG_DISABLE |\
 527         HRCWH_ROM_LOC_LOCAL_16BIT |\
 528         HRCWH_TSEC1M_IN_GMII |\
 529         HRCWH_TSEC2M_IN_GMII)
 530 #endif /* CONFIG_PCI_64BIT */
 531 #endif /* CONFIG_PCISLAVE */
 532
 533 /*
 534  * System performance
 535  */
 536 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 537 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 538 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 539 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 540 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 541 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 542
 543 /* System IO Config */
 544 #define CONFIG_SYS_SICRH 0
 545 #define CONFIG_SYS_SICRL SICRL_LDP_A
 546
 547 #define CONFIG_SYS_HID0_INIT    0x000000000
 548 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 549                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 550
 551 /* #define CONFIG_SYS_HID0_FINAL        (\
 552         HID0_ENABLE_INSTRUCTION_CACHE |\
 553         HID0_ENABLE_M_BIT |\
 554         HID0_ENABLE_ADDRESS_BROADCAST) */
 555
 556 #define CONFIG_SYS_HID2 HID2_HBE
 557 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 558
 559 /* DDR @ 0x00000000 */
 560 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 561                                 | BATL_PP_RW \
 562                                 | BATL_MEMCOHERENCE)
 563 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 564                                 | BATU_BL_256M \
 565                                 | BATU_VS \
 566                                 | BATU_VP)
 567
 568 /* PCI @ 0x80000000 */
 569 #ifdef CONFIG_PCI
 570 #define CONFIG_PCI_INDIRECT_BRIDGE
 571 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 572                                 | BATL_PP_RW \
 573                                 | BATL_MEMCOHERENCE)
 574 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 575                                 | BATU_BL_256M \
 576                                 | BATU_VS \
 577                                 | BATU_VP)
 578 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 579                                 | BATL_PP_RW \
 580                                 | BATL_CACHEINHIBIT \
 581                                 | BATL_GUARDEDSTORAGE)
 582 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 583                                 | BATU_BL_256M \
 584                                 | BATU_VS \
 585                                 | BATU_VP)
 586 #else
 587 #define CONFIG_SYS_IBAT1L       (0)
 588 #define CONFIG_SYS_IBAT1U       (0)
 589 #define CONFIG_SYS_IBAT2L       (0)
 590 #define CONFIG_SYS_IBAT2U       (0)
 591 #endif
 592
 593 #ifdef CONFIG_MPC83XX_PCI2
 594 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 595                                 | BATL_PP_RW \
 596                                 | BATL_MEMCOHERENCE)
 597 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 598                                 | BATU_BL_256M \
 599                                 | BATU_VS \
 600                                 | BATU_VP)
 601 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 602                                 | BATL_PP_RW \
 603                                 | BATL_CACHEINHIBIT \
 604                                 | BATL_GUARDEDSTORAGE)
 605 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 606                                 | BATU_BL_256M \
 607                                 | BATU_VS \
 608                                 | BATU_VP)
 609 #else
 610 #define CONFIG_SYS_IBAT3L       (0)
 611 #define CONFIG_SYS_IBAT3U       (0)
 612 #define CONFIG_SYS_IBAT4L       (0)
 613 #define CONFIG_SYS_IBAT4U       (0)
 614 #endif
 615
 616 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 617 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 618                                 | BATL_PP_RW \
 619                                 | BATL_CACHEINHIBIT \
 620                                 | BATL_GUARDEDSTORAGE)
 621 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 622                                 | BATU_BL_256M \
 623                                 | BATU_VS \
 624                                 | BATU_VP)
 625
 626 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 627 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 628                                 | BATL_PP_RW \
 629                                 | BATL_MEMCOHERENCE \
 630                                 | BATL_GUARDEDSTORAGE)
 631 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 632                                 | BATU_BL_256M \
 633                                 | BATU_VS \
 634                                 | BATU_VP)
 635
 636 #define CONFIG_SYS_IBAT7L       (0)
 637 #define CONFIG_SYS_IBAT7U       (0)
 638
 639 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 640 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 641 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 642 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 643 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 644 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 645 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 646 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 647 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 648 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 649 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 650 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 651 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 652 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 653 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 654 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 655
 656 #if defined(CONFIG_CMD_KGDB)
 657 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 658 #endif
 659
 660 /*
 661  * Environment Configuration
 662  */
 663 #define CONFIG_ENV_OVERWRITE
 664
 665 #if defined(CONFIG_TSEC_ENET)
 666 #define CONFIG_HAS_ETH1
 667 #define CONFIG_HAS_ETH0
 668 #endif
 669
 670 #define CONFIG_HOSTNAME         "mpc8349emds"
 671 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 672 #define CONFIG_BOOTFILE         "uImage"
 673
 674 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 675
 676 #define CONFIG_PREBOOT  "echo;" \
 677         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 678         "echo"
 679
 680 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 681         "netdev=eth0\0"                                                 \
 682         "hostname=mpc8349emds\0"                                        \
 683         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 684                 "nfsroot=${serverip}:${rootpath}\0"                     \
 685         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 686         "addip=setenv bootargs ${bootargs} "                            \
 687                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 688                 ":${hostname}:${netdev}:off panic=1\0"                  \
 689         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 690         "flash_nfs=run nfsargs addip addtty;"                           \
 691                 "bootm ${kernel_addr}\0"                                \
 692         "flash_self=run ramargs addip addtty;"                          \
 693                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 694         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 695                 "bootm\0"                                               \
 696         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 697         "update=protect off fe000000 fe03ffff; "                        \
 698                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 699         "upd=run load update\0"                                         \
 700         "fdtaddr=780000\0"                                              \
 701         "fdtfile=mpc834x_mds.dtb\0"                                     \
 702         ""
 703
 704 #define CONFIG_NFSBOOTCOMMAND                                           \
 705         "setenv bootargs root=/dev/nfs rw "                             \
 706                 "nfsroot=$serverip:$rootpath "                          \
 707                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 708                                                         "$netdev:off "  \
 709                 "console=$consoledev,$baudrate $othbootargs;"           \
 710         "tftp $loadaddr $bootfile;"                                     \
 711         "tftp $fdtaddr $fdtfile;"                                       \
 712         "bootm $loadaddr - $fdtaddr"
 713
 714 #define CONFIG_RAMBOOTCOMMAND                                           \
 715         "setenv bootargs root=/dev/ram rw "                             \
 716                 "console=$consoledev,$baudrate $othbootargs;"           \
 717         "tftp $ramdiskaddr $ramdiskfile;"                               \
 718         "tftp $loadaddr $bootfile;"                                     \
 719         "tftp $fdtaddr $fdtfile;"                                       \
 720         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 721
 722 #define CONFIG_BOOTCOMMAND      "run flash_self"
 723
 724 #endif  /* __CONFIG_H */