include/configs/MPC8349EMDS.h

   1 /*
   2  * (C) Copyright 2006-2010
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * mpc8349emds board configuration file
  10  *
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_E300             1       /* E300 Family */
  20 #define CONFIG_MPC834x          1       /* MPC834x family */
  21 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  22 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  25
  26 #define CONFIG_PCI_66M
  27 #ifdef CONFIG_PCI_66M
  28 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  29 #else
  30 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  31 #endif
  32
  33 #ifdef CONFIG_PCISLAVE
  34 #define CONFIG_83XX_PCICLK      66666666        /* in Hz */
  35 #endif /* CONFIG_PCISLAVE */
  36
  37 #ifndef CONFIG_SYS_CLK_FREQ
  38 #ifdef CONFIG_PCI_66M
  39 #define CONFIG_SYS_CLK_FREQ     66000000
  40 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  41 #else
  42 #define CONFIG_SYS_CLK_FREQ     33000000
  43 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  44 #endif
  45 #endif
  46
  47 #define CONFIG_SYS_IMMR         0xE0000000
  48
  49 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  50 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  51 #define CONFIG_SYS_MEMTEST_END          0x00100000
  52
  53 /*
  54  * DDR Setup
  55  */
  56 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  57 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  58 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  59
  60 /*
  61  * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  62  * unselect it to use old spd_sdram.c
  63  */
  64 #define CONFIG_SYS_SPD_BUS_NUM  0
  65 #define SPD_EEPROM_ADDRESS1     0x52
  66 #define SPD_EEPROM_ADDRESS2     0x51
  67 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  68 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  69 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  70 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  71
  72 /*
  73  * 32-bit data path mode.
  74  *
  75  * Please note that using this mode for devices with the real density of 64-bit
  76  * effectively reduces the amount of available memory due to the effect of
  77  * wrapping around while translating address to row/columns, for example in the
  78  * 256MB module the upper 128MB get aliased with contents of the lower
  79  * 128MB); normally this define should be used for devices with real 32-bit
  80  * data path.
  81  */
  82 #undef CONFIG_DDR_32BIT
  83
  84 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory*/
  85 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  86 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  87 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  88                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  89 #undef  CONFIG_DDR_2T_TIMING
  90
  91 /*
  92  * DDRCDR - DDR Control Driver Register
  93  */
  94 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  95
  96 #if defined(CONFIG_SPD_EEPROM)
  97 /*
  98  * Determine DDR configuration from I2C interface.
  99  */
 100 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 101 #else
 102 /*
 103  * Manually set up DDR parameters
 104  */
 105 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 106 #if defined(CONFIG_DDR_II)
 107 #define CONFIG_SYS_DDRCDR               0x80080001
 108 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
 109 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
 110 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
 111 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
 112 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
 113 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 114 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
 115 #define CONFIG_SYS_DDR_MODE             0x47d00432
 116 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 117 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
 118 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 119 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 120 #else
 121 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
 122                                 | CSCONFIG_ROW_BIT_13 \
 123                                 | CSCONFIG_COL_BIT_10)
 124 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 125 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 126 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 127 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 128
 129 #if defined(CONFIG_DDR_32BIT)
 130 /* set burst length to 8 for 32-bit data path */
 131                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 132 #define CONFIG_SYS_DDR_MODE     0x00000023
 133 #else
 134 /* the default burst length is 4 - for 64-bit data path */
 135                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 136 #define CONFIG_SYS_DDR_MODE     0x00000022
 137 #endif
 138 #endif
 139 #endif
 140
 141 /*
 142  * SDRAM on the Local Bus
 143  */
 144 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 145 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 146
 147 /*
 148  * FLASH on the Local Bus
 149  */
 150 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 151 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 152 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 153 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 154 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 155 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 156
 157 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 158                                 | BR_PS_16      /* 16 bit port  */ \
 159                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 160                                 | BR_V)         /* valid */
 161 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 162                                 | OR_UPM_XAM \
 163                                 | OR_GPCM_CSNT \
 164                                 | OR_GPCM_ACS_DIV2 \
 165                                 | OR_GPCM_XACS \
 166                                 | OR_GPCM_SCY_15 \
 167                                 | OR_GPCM_TRLX_SET \
 168                                 | OR_GPCM_EHTR_SET \
 169                                 | OR_GPCM_EAD)
 170
 171                                         /* window base at flash base */
 172 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 173 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 174
 175 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 176 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 177
 178 #undef CONFIG_SYS_FLASH_CHECKSUM
 179 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 180 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 181
 182 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 183
 184 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 185 #define CONFIG_SYS_RAMBOOT
 186 #else
 187 #undef  CONFIG_SYS_RAMBOOT
 188 #endif
 189
 190 /*
 191  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 192  */
 193 #define CONFIG_SYS_BCSR                 0xE2400000
 194                                         /* Access window base at BCSR base */
 195 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 196 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 197 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 198                                         | BR_PS_8 \
 199                                         | BR_MS_GPCM \
 200                                         | BR_V)
 201                                         /* 0x00000801 */
 202 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 203                                         | OR_GPCM_XAM \
 204                                         | OR_GPCM_CSNT \
 205                                         | OR_GPCM_SCY_15 \
 206                                         | OR_GPCM_TRLX_CLEAR \
 207                                         | OR_GPCM_EHTR_CLEAR)
 208                                         /* 0xFFFFE8F0 */
 209
 210 #define CONFIG_SYS_INIT_RAM_LOCK        1
 211 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 212 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 213
 214 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 215                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 216 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 217
 218 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 219 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 220
 221 /*
 222  * Local Bus LCRR and LBCR regs
 223  *    LCRR:  DLL bypass, Clock divider is 4
 224  * External Local Bus rate is
 225  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 226  */
 227 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 228 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 229 #define CONFIG_SYS_LBC_LBCR     0x00000000
 230
 231 /*
 232  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 233  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
 234  */
 235 #undef CONFIG_SYS_LB_SDRAM
 236
 237 #ifdef CONFIG_SYS_LB_SDRAM
 238 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 239 /*
 240  * Base Register 2 and Option Register 2 configure SDRAM.
 241  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 242  *
 243  * For BR2, need:
 244  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 245  *    port-size = 32-bits = BR2[19:20] = 11
 246  *    no parity checking = BR2[21:22] = 00
 247  *    SDRAM for MSEL = BR2[24:26] = 011
 248  *    Valid = BR[31] = 1
 249  *
 250  * 0    4    8    12   16   20   24   28
 251  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 252  */
 253
 254 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 255                                         | BR_PS_32      /* 32-bit port */ \
 256                                         | BR_MS_SDRAM   /* MSEL = SDRAM */ \
 257                                         | BR_V)         /* Valid */
 258                                         /* 0xF0001861 */
 259 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 260 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 261
 262 /*
 263  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 264  *
 265  * For OR2, need:
 266  *    64MB mask for AM, OR2[0:7] = 1111 1100
 267  *                 XAM, OR2[17:18] = 11
 268  *    9 columns OR2[19-21] = 010
 269  *    13 rows   OR2[23-25] = 100
 270  *    EAD set for extra time OR[31] = 1
 271  *
 272  * 0    4    8    12   16   20   24   28
 273  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 274  */
 275
 276 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_64MB \
 277                         | OR_SDRAM_XAM \
 278                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 279                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 280                         | OR_SDRAM_EAD)
 281                         /* 0xFC006901 */
 282
 283                                 /* LB sdram refresh timer, about 6us */
 284 #define CONFIG_SYS_LBC_LSRT     0x32000000
 285                                 /* LB refresh timer prescal, 266MHz/32 */
 286 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 287
 288 #define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN      \
 289                                 | LSDMR_BSMA1516        \
 290                                 | LSDMR_RFCR8           \
 291                                 | LSDMR_PRETOACT6       \
 292                                 | LSDMR_ACTTORW3        \
 293                                 | LSDMR_BL8             \
 294                                 | LSDMR_WRC3            \
 295                                 | LSDMR_CL3)
 296
 297 /*
 298  * SDRAM Controller configuration sequence.
 299  */
 300 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 301 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 302 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 303 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 304 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 305 #endif
 306
 307 /*
 308  * Serial Port
 309  */
 310 #define CONFIG_CONS_INDEX     1
 311 #define CONFIG_SYS_NS16550_SERIAL
 312 #define CONFIG_SYS_NS16550_REG_SIZE    1
 313 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 314
 315 #define CONFIG_SYS_BAUDRATE_TABLE  \
 316                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 317
 318 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 319 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 320
 321 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 322 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 323
 324 /* I2C */
 325 #define CONFIG_SYS_I2C
 326 #define CONFIG_SYS_I2C_FSL
 327 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 328 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 329 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 330 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 331 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 332 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 333 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 334
 335 /* SPI */
 336 #define CONFIG_MPC8XXX_SPI
 337 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 338
 339 /* GPIOs.  Used as SPI chip selects */
 340 #define CONFIG_SYS_GPIO1_PRELIM
 341 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 342 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 343
 344 /* TSEC */
 345 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 346 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 347 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 348 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 349
 350 /* USB */
 351 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 352
 353 /*
 354  * General PCI
 355  * Addresses are mapped 1-1.
 356  */
 357 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 358 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 359 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 360 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 361 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 362 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 363 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 364 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 365 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 366
 367 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 368 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 369 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 370 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 371 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 372 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 373 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 374 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 375 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 376
 377 #if defined(CONFIG_PCI)
 378
 379 #define PCI_ONE_PCI1
 380 #if defined(PCI_64BIT)
 381 #undef PCI_ALL_PCI1
 382 #undef PCI_TWO_PCI1
 383 #undef PCI_ONE_PCI1
 384 #endif
 385
 386 #define CONFIG_83XX_PCI_STREAMING
 387
 388 #undef CONFIG_EEPRO100
 389 #undef CONFIG_TULIP
 390
 391 #if !defined(CONFIG_PCI_PNP)
 392         #define PCI_ENET0_IOADDR        0xFIXME
 393         #define PCI_ENET0_MEMADDR       0xFIXME
 394         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 395 #endif
 396
 397 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 398 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 399
 400 #endif  /* CONFIG_PCI */
 401
 402 /*
 403  * TSEC configuration
 404  */
 405 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 406
 407 #if defined(CONFIG_TSEC_ENET)
 408
 409 #define CONFIG_GMII             1       /* MII PHY management */
 410 #define CONFIG_TSEC1            1
 411 #define CONFIG_TSEC1_NAME       "TSEC0"
 412 #define CONFIG_TSEC2            1
 413 #define CONFIG_TSEC2_NAME       "TSEC1"
 414 #define TSEC1_PHY_ADDR          0
 415 #define TSEC2_PHY_ADDR          1
 416 #define TSEC1_PHYIDX            0
 417 #define TSEC2_PHYIDX            0
 418 #define TSEC1_FLAGS             TSEC_GIGABIT
 419 #define TSEC2_FLAGS             TSEC_GIGABIT
 420
 421 /* Options are: TSEC[0-1] */
 422 #define CONFIG_ETHPRIME         "TSEC0"
 423
 424 #endif  /* CONFIG_TSEC_ENET */
 425
 426 /*
 427  * Configure on-board RTC
 428  */
 429 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 430 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 431
 432 /*
 433  * Environment
 434  */
 435 #ifndef CONFIG_SYS_RAMBOOT
 436         #define CONFIG_ENV_ADDR         \
 437                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 438         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 439         #define CONFIG_ENV_SIZE         0x2000
 440
 441 /* Address and size of Redundant Environment Sector     */
 442 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 443 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 444
 445 #else
 446         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 447         #define CONFIG_ENV_SIZE         0x2000
 448 #endif
 449
 450 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 451 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 452
 453 /*
 454  * BOOTP options
 455  */
 456 #define CONFIG_BOOTP_BOOTFILESIZE
 457 #define CONFIG_BOOTP_BOOTPATH
 458 #define CONFIG_BOOTP_GATEWAY
 459 #define CONFIG_BOOTP_HOSTNAME
 460
 461 /*
 462  * Command line configuration.
 463  */
 464
 465 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 466
 467 /*
 468  * Miscellaneous configurable options
 469  */
 470 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 471 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 472
 473 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 474                                 /* Boot Argument Buffer Size */
 475 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 476
 477 /*
 478  * For booting Linux, the board info and command line data
 479  * have to be in the first 256 MB of memory, since this is
 480  * the maximum mapped by the Linux kernel during initialization.
 481  */
 482                                 /* Initial Memory map for Linux*/
 483 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 484 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 485
 486 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 487
 488 #if 1 /*528/264*/
 489 #define CONFIG_SYS_HRCW_LOW (\
 490         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 491         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 492         HRCWL_CSB_TO_CLKIN |\
 493         HRCWL_VCO_1X2 |\
 494         HRCWL_CORE_TO_CSB_2X1)
 495 #elif 0 /*396/132*/
 496 #define CONFIG_SYS_HRCW_LOW (\
 497         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 498         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 499         HRCWL_CSB_TO_CLKIN |\
 500         HRCWL_VCO_1X4 |\
 501         HRCWL_CORE_TO_CSB_3X1)
 502 #elif 0 /*264/132*/
 503 #define CONFIG_SYS_HRCW_LOW (\
 504         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 505         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 506         HRCWL_CSB_TO_CLKIN |\
 507         HRCWL_VCO_1X4 |\
 508         HRCWL_CORE_TO_CSB_2X1)
 509 #elif 0 /*132/132*/
 510 #define CONFIG_SYS_HRCW_LOW (\
 511         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 512         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 513         HRCWL_CSB_TO_CLKIN |\
 514         HRCWL_VCO_1X4 |\
 515         HRCWL_CORE_TO_CSB_1X1)
 516 #elif 0 /*264/264 */
 517 #define CONFIG_SYS_HRCW_LOW (\
 518         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 519         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 520         HRCWL_CSB_TO_CLKIN |\
 521         HRCWL_VCO_1X4 |\
 522         HRCWL_CORE_TO_CSB_1X1)
 523 #endif
 524
 525 #ifdef CONFIG_PCISLAVE
 526 #define CONFIG_SYS_HRCW_HIGH (\
 527         HRCWH_PCI_AGENT |\
 528         HRCWH_64_BIT_PCI |\
 529         HRCWH_PCI1_ARBITER_DISABLE |\
 530         HRCWH_PCI2_ARBITER_DISABLE |\
 531         HRCWH_CORE_ENABLE |\
 532         HRCWH_FROM_0X00000100 |\
 533         HRCWH_BOOTSEQ_DISABLE |\
 534         HRCWH_SW_WATCHDOG_DISABLE |\
 535         HRCWH_ROM_LOC_LOCAL_16BIT |\
 536         HRCWH_TSEC1M_IN_GMII |\
 537         HRCWH_TSEC2M_IN_GMII)
 538 #else
 539 #if defined(PCI_64BIT)
 540 #define CONFIG_SYS_HRCW_HIGH (\
 541         HRCWH_PCI_HOST |\
 542         HRCWH_64_BIT_PCI |\
 543         HRCWH_PCI1_ARBITER_ENABLE |\
 544         HRCWH_PCI2_ARBITER_DISABLE |\
 545         HRCWH_CORE_ENABLE |\
 546         HRCWH_FROM_0X00000100 |\
 547         HRCWH_BOOTSEQ_DISABLE |\
 548         HRCWH_SW_WATCHDOG_DISABLE |\
 549         HRCWH_ROM_LOC_LOCAL_16BIT |\
 550         HRCWH_TSEC1M_IN_GMII |\
 551         HRCWH_TSEC2M_IN_GMII)
 552 #else
 553 #define CONFIG_SYS_HRCW_HIGH (\
 554         HRCWH_PCI_HOST |\
 555         HRCWH_32_BIT_PCI |\
 556         HRCWH_PCI1_ARBITER_ENABLE |\
 557         HRCWH_PCI2_ARBITER_ENABLE |\
 558         HRCWH_CORE_ENABLE |\
 559         HRCWH_FROM_0X00000100 |\
 560         HRCWH_BOOTSEQ_DISABLE |\
 561         HRCWH_SW_WATCHDOG_DISABLE |\
 562         HRCWH_ROM_LOC_LOCAL_16BIT |\
 563         HRCWH_TSEC1M_IN_GMII |\
 564         HRCWH_TSEC2M_IN_GMII)
 565 #endif /* PCI_64BIT */
 566 #endif /* CONFIG_PCISLAVE */
 567
 568 /*
 569  * System performance
 570  */
 571 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 572 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 573 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 574 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 575 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 576 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 577
 578 /* System IO Config */
 579 #define CONFIG_SYS_SICRH 0
 580 #define CONFIG_SYS_SICRL SICRL_LDP_A
 581
 582 #define CONFIG_SYS_HID0_INIT    0x000000000
 583 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 584                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 585
 586 /* #define CONFIG_SYS_HID0_FINAL        (\
 587         HID0_ENABLE_INSTRUCTION_CACHE |\
 588         HID0_ENABLE_M_BIT |\
 589         HID0_ENABLE_ADDRESS_BROADCAST) */
 590
 591 #define CONFIG_SYS_HID2 HID2_HBE
 592 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 593
 594 /* DDR @ 0x00000000 */
 595 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 596                                 | BATL_PP_RW \
 597                                 | BATL_MEMCOHERENCE)
 598 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 599                                 | BATU_BL_256M \
 600                                 | BATU_VS \
 601                                 | BATU_VP)
 602
 603 /* PCI @ 0x80000000 */
 604 #ifdef CONFIG_PCI
 605 #define CONFIG_PCI_INDIRECT_BRIDGE
 606 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 607                                 | BATL_PP_RW \
 608                                 | BATL_MEMCOHERENCE)
 609 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 610                                 | BATU_BL_256M \
 611                                 | BATU_VS \
 612                                 | BATU_VP)
 613 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 614                                 | BATL_PP_RW \
 615                                 | BATL_CACHEINHIBIT \
 616                                 | BATL_GUARDEDSTORAGE)
 617 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 618                                 | BATU_BL_256M \
 619                                 | BATU_VS \
 620                                 | BATU_VP)
 621 #else
 622 #define CONFIG_SYS_IBAT1L       (0)
 623 #define CONFIG_SYS_IBAT1U       (0)
 624 #define CONFIG_SYS_IBAT2L       (0)
 625 #define CONFIG_SYS_IBAT2U       (0)
 626 #endif
 627
 628 #ifdef CONFIG_MPC83XX_PCI2
 629 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 630                                 | BATL_PP_RW \
 631                                 | BATL_MEMCOHERENCE)
 632 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 633                                 | BATU_BL_256M \
 634                                 | BATU_VS \
 635                                 | BATU_VP)
 636 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 637                                 | BATL_PP_RW \
 638                                 | BATL_CACHEINHIBIT \
 639                                 | BATL_GUARDEDSTORAGE)
 640 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 641                                 | BATU_BL_256M \
 642                                 | BATU_VS \
 643                                 | BATU_VP)
 644 #else
 645 #define CONFIG_SYS_IBAT3L       (0)
 646 #define CONFIG_SYS_IBAT3U       (0)
 647 #define CONFIG_SYS_IBAT4L       (0)
 648 #define CONFIG_SYS_IBAT4U       (0)
 649 #endif
 650
 651 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 652 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 653                                 | BATL_PP_RW \
 654                                 | BATL_CACHEINHIBIT \
 655                                 | BATL_GUARDEDSTORAGE)
 656 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 657                                 | BATU_BL_256M \
 658                                 | BATU_VS \
 659                                 | BATU_VP)
 660
 661 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 662 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 663                                 | BATL_PP_RW \
 664                                 | BATL_MEMCOHERENCE \
 665                                 | BATL_GUARDEDSTORAGE)
 666 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 667                                 | BATU_BL_256M \
 668                                 | BATU_VS \
 669                                 | BATU_VP)
 670
 671 #define CONFIG_SYS_IBAT7L       (0)
 672 #define CONFIG_SYS_IBAT7U       (0)
 673
 674 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 675 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 676 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 677 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 678 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 679 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 680 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 681 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 682 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 683 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 684 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 685 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 686 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 687 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 688 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 689 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 690
 691 #if defined(CONFIG_CMD_KGDB)
 692 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 693 #endif
 694
 695 /*
 696  * Environment Configuration
 697  */
 698 #define CONFIG_ENV_OVERWRITE
 699
 700 #if defined(CONFIG_TSEC_ENET)
 701 #define CONFIG_HAS_ETH1
 702 #define CONFIG_HAS_ETH0
 703 #endif
 704
 705 #define CONFIG_HOSTNAME         mpc8349emds
 706 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 707 #define CONFIG_BOOTFILE         "uImage"
 708
 709 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 710
 711 #define CONFIG_PREBOOT  "echo;" \
 712         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 713         "echo"
 714
 715 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 716         "netdev=eth0\0"                                                 \
 717         "hostname=mpc8349emds\0"                                        \
 718         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 719                 "nfsroot=${serverip}:${rootpath}\0"                     \
 720         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 721         "addip=setenv bootargs ${bootargs} "                            \
 722                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 723                 ":${hostname}:${netdev}:off panic=1\0"                  \
 724         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 725         "flash_nfs=run nfsargs addip addtty;"                           \
 726                 "bootm ${kernel_addr}\0"                                \
 727         "flash_self=run ramargs addip addtty;"                          \
 728                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 729         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 730                 "bootm\0"                                               \
 731         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 732         "update=protect off fe000000 fe03ffff; "                        \
 733                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 734         "upd=run load update\0"                                         \
 735         "fdtaddr=780000\0"                                              \
 736         "fdtfile=mpc834x_mds.dtb\0"                                     \
 737         ""
 738
 739 #define CONFIG_NFSBOOTCOMMAND                                           \
 740         "setenv bootargs root=/dev/nfs rw "                             \
 741                 "nfsroot=$serverip:$rootpath "                          \
 742                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 743                                                         "$netdev:off "  \
 744                 "console=$consoledev,$baudrate $othbootargs;"           \
 745         "tftp $loadaddr $bootfile;"                                     \
 746         "tftp $fdtaddr $fdtfile;"                                       \
 747         "bootm $loadaddr - $fdtaddr"
 748
 749 #define CONFIG_RAMBOOTCOMMAND                                           \
 750         "setenv bootargs root=/dev/ram rw "                             \
 751                 "console=$consoledev,$baudrate $othbootargs;"           \
 752         "tftp $ramdiskaddr $ramdiskfile;"                               \
 753         "tftp $loadaddr $bootfile;"                                     \
 754         "tftp $fdtaddr $fdtfile;"                                       \
 755         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 756
 757 #define CONFIG_BOOTCOMMAND      "run flash_self"
 758
 759 #endif  /* __CONFIG_H */