include/configs/MPC8349EMDS.h

   1 /*
   2  * (C) Copyright 2006-2010
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * mpc8349emds board configuration file
  10  *
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_E300             1       /* E300 Family */
  20 #define CONFIG_MPC834x          1       /* MPC834x family */
  21 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  22 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  25
  26 #define CONFIG_PCI_66M
  27 #ifdef CONFIG_PCI_66M
  28 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  29 #else
  30 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  31 #endif
  32
  33 #ifdef CONFIG_PCISLAVE
  34 #define CONFIG_83XX_PCICLK      66666666        /* in Hz */
  35 #endif /* CONFIG_PCISLAVE */
  36
  37 #ifndef CONFIG_SYS_CLK_FREQ
  38 #ifdef CONFIG_PCI_66M
  39 #define CONFIG_SYS_CLK_FREQ     66000000
  40 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  41 #else
  42 #define CONFIG_SYS_CLK_FREQ     33000000
  43 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  44 #endif
  45 #endif
  46
  47 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  48
  49 #define CONFIG_SYS_IMMR         0xE0000000
  50
  51 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  52 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  53 #define CONFIG_SYS_MEMTEST_END          0x00100000
  54
  55 /*
  56  * DDR Setup
  57  */
  58 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  59 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  60 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  61
  62 /*
  63  * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
  64  * undefine it to use old spd_sdram.c
  65  */
  66 #define CONFIG_SYS_FSL_DDR2
  67 #ifdef CONFIG_SYS_FSL_DDR2
  68 #define CONFIG_SYS_FSL_DDRC_GEN2
  69 #define CONFIG_SYS_SPD_BUS_NUM  0
  70 #define SPD_EEPROM_ADDRESS1     0x52
  71 #define SPD_EEPROM_ADDRESS2     0x51
  72 #define CONFIG_NUM_DDR_CONTROLLERS      1
  73 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  74 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  76 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  77 #endif
  78
  79 /*
  80  * 32-bit data path mode.
  81  *
  82  * Please note that using this mode for devices with the real density of 64-bit
  83  * effectively reduces the amount of available memory due to the effect of
  84  * wrapping around while translating address to row/columns, for example in the
  85  * 256MB module the upper 128MB get aliased with contents of the lower
  86  * 128MB); normally this define should be used for devices with real 32-bit
  87  * data path.
  88  */
  89 #undef CONFIG_DDR_32BIT
  90
  91 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory*/
  92 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  93 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  94 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  95                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  96 #undef  CONFIG_DDR_2T_TIMING
  97
  98 /*
  99  * DDRCDR - DDR Control Driver Register
 100  */
 101 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 102
 103 #if defined(CONFIG_SPD_EEPROM)
 104 /*
 105  * Determine DDR configuration from I2C interface.
 106  */
 107 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 108 #else
 109 /*
 110  * Manually set up DDR parameters
 111  */
 112 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 113 #if defined(CONFIG_DDR_II)
 114 #define CONFIG_SYS_DDRCDR               0x80080001
 115 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
 116 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
 117 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
 118 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
 119 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
 120 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 121 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
 122 #define CONFIG_SYS_DDR_MODE             0x47d00432
 123 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 124 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
 125 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 126 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 127 #else
 128 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
 129                                 | CSCONFIG_ROW_BIT_13 \
 130                                 | CSCONFIG_COL_BIT_10)
 131 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 132 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 133 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 134 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 135
 136 #if defined(CONFIG_DDR_32BIT)
 137 /* set burst length to 8 for 32-bit data path */
 138                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 139 #define CONFIG_SYS_DDR_MODE     0x00000023
 140 #else
 141 /* the default burst length is 4 - for 64-bit data path */
 142                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 143 #define CONFIG_SYS_DDR_MODE     0x00000022
 144 #endif
 145 #endif
 146 #endif
 147
 148 /*
 149  * SDRAM on the Local Bus
 150  */
 151 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 152 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 153
 154 /*
 155  * FLASH on the Local Bus
 156  */
 157 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 158 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 159 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 160 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 161 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 162 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 163
 164 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 165                                 | BR_PS_16      /* 16 bit port  */ \
 166                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 167                                 | BR_V)         /* valid */
 168 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 169                                 | OR_UPM_XAM \
 170                                 | OR_GPCM_CSNT \
 171                                 | OR_GPCM_ACS_DIV2 \
 172                                 | OR_GPCM_XACS \
 173                                 | OR_GPCM_SCY_15 \
 174                                 | OR_GPCM_TRLX_SET \
 175                                 | OR_GPCM_EHTR_SET \
 176                                 | OR_GPCM_EAD)
 177
 178                                         /* window base at flash base */
 179 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 180 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 181
 182 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 183 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 184
 185 #undef CONFIG_SYS_FLASH_CHECKSUM
 186 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 187 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 188
 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 190
 191 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 192 #define CONFIG_SYS_RAMBOOT
 193 #else
 194 #undef  CONFIG_SYS_RAMBOOT
 195 #endif
 196
 197 /*
 198  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 199  */
 200 #define CONFIG_SYS_BCSR                 0xE2400000
 201                                         /* Access window base at BCSR base */
 202 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 203 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 204 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 205                                         | BR_PS_8 \
 206                                         | BR_MS_GPCM \
 207                                         | BR_V)
 208                                         /* 0x00000801 */
 209 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 210                                         | OR_GPCM_XAM \
 211                                         | OR_GPCM_CSNT \
 212                                         | OR_GPCM_SCY_15 \
 213                                         | OR_GPCM_TRLX_CLEAR \
 214                                         | OR_GPCM_EHTR_CLEAR)
 215                                         /* 0xFFFFE8F0 */
 216
 217 #define CONFIG_SYS_INIT_RAM_LOCK        1
 218 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 219 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 220
 221 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 222                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 223 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 224
 225 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 226 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 227
 228 /*
 229  * Local Bus LCRR and LBCR regs
 230  *    LCRR:  DLL bypass, Clock divider is 4
 231  * External Local Bus rate is
 232  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 233  */
 234 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 235 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 236 #define CONFIG_SYS_LBC_LBCR     0x00000000
 237
 238 /*
 239  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 240  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
 241  */
 242 #undef CONFIG_SYS_LB_SDRAM
 243
 244 #ifdef CONFIG_SYS_LB_SDRAM
 245 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 246 /*
 247  * Base Register 2 and Option Register 2 configure SDRAM.
 248  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 249  *
 250  * For BR2, need:
 251  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 252  *    port-size = 32-bits = BR2[19:20] = 11
 253  *    no parity checking = BR2[21:22] = 00
 254  *    SDRAM for MSEL = BR2[24:26] = 011
 255  *    Valid = BR[31] = 1
 256  *
 257  * 0    4    8    12   16   20   24   28
 258  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 259  */
 260
 261 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 262                                         | BR_PS_32      /* 32-bit port */ \
 263                                         | BR_MS_SDRAM   /* MSEL = SDRAM */ \
 264                                         | BR_V)         /* Valid */
 265                                         /* 0xF0001861 */
 266 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 267 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 268
 269 /*
 270  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 271  *
 272  * For OR2, need:
 273  *    64MB mask for AM, OR2[0:7] = 1111 1100
 274  *                 XAM, OR2[17:18] = 11
 275  *    9 columns OR2[19-21] = 010
 276  *    13 rows   OR2[23-25] = 100
 277  *    EAD set for extra time OR[31] = 1
 278  *
 279  * 0    4    8    12   16   20   24   28
 280  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 281  */
 282
 283 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_64MB \
 284                         | OR_SDRAM_XAM \
 285                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 286                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 287                         | OR_SDRAM_EAD)
 288                         /* 0xFC006901 */
 289
 290                                 /* LB sdram refresh timer, about 6us */
 291 #define CONFIG_SYS_LBC_LSRT     0x32000000
 292                                 /* LB refresh timer prescal, 266MHz/32 */
 293 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 294
 295 #define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN      \
 296                                 | LSDMR_BSMA1516        \
 297                                 | LSDMR_RFCR8           \
 298                                 | LSDMR_PRETOACT6       \
 299                                 | LSDMR_ACTTORW3        \
 300                                 | LSDMR_BL8             \
 301                                 | LSDMR_WRC3            \
 302                                 | LSDMR_CL3)
 303
 304 /*
 305  * SDRAM Controller configuration sequence.
 306  */
 307 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 308 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 309 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 310 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 311 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 312 #endif
 313
 314 /*
 315  * Serial Port
 316  */
 317 #define CONFIG_CONS_INDEX     1
 318 #define CONFIG_SYS_NS16550_SERIAL
 319 #define CONFIG_SYS_NS16550_REG_SIZE    1
 320 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 321
 322 #define CONFIG_SYS_BAUDRATE_TABLE  \
 323                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 324
 325 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 326 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 327
 328 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 329 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 330
 331 /* I2C */
 332 #define CONFIG_SYS_I2C
 333 #define CONFIG_SYS_I2C_FSL
 334 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 335 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 336 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 337 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 338 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 339 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 340 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 341
 342 /* SPI */
 343 #define CONFIG_MPC8XXX_SPI
 344 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 345
 346 /* GPIOs.  Used as SPI chip selects */
 347 #define CONFIG_SYS_GPIO1_PRELIM
 348 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 349 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 350
 351 /* TSEC */
 352 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 353 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 354 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 355 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 356
 357 /* USB */
 358 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 359
 360 /*
 361  * General PCI
 362  * Addresses are mapped 1-1.
 363  */
 364 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 365 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 366 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 367 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 368 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 369 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 370 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 371 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 372 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 373
 374 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 375 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 376 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 377 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 378 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 379 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 380 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 381 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 382 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 383
 384 #if defined(CONFIG_PCI)
 385
 386 #define PCI_ONE_PCI1
 387 #if defined(PCI_64BIT)
 388 #undef PCI_ALL_PCI1
 389 #undef PCI_TWO_PCI1
 390 #undef PCI_ONE_PCI1
 391 #endif
 392
 393 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 394 #define CONFIG_83XX_PCI_STREAMING
 395
 396 #undef CONFIG_EEPRO100
 397 #undef CONFIG_TULIP
 398
 399 #if !defined(CONFIG_PCI_PNP)
 400         #define PCI_ENET0_IOADDR        0xFIXME
 401         #define PCI_ENET0_MEMADDR       0xFIXME
 402         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 403 #endif
 404
 405 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 406 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 407
 408 #endif  /* CONFIG_PCI */
 409
 410 /*
 411  * TSEC configuration
 412  */
 413 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 414
 415 #if defined(CONFIG_TSEC_ENET)
 416
 417 #define CONFIG_GMII             1       /* MII PHY management */
 418 #define CONFIG_TSEC1            1
 419 #define CONFIG_TSEC1_NAME       "TSEC0"
 420 #define CONFIG_TSEC2            1
 421 #define CONFIG_TSEC2_NAME       "TSEC1"
 422 #define TSEC1_PHY_ADDR          0
 423 #define TSEC2_PHY_ADDR          1
 424 #define TSEC1_PHYIDX            0
 425 #define TSEC2_PHYIDX            0
 426 #define TSEC1_FLAGS             TSEC_GIGABIT
 427 #define TSEC2_FLAGS             TSEC_GIGABIT
 428
 429 /* Options are: TSEC[0-1] */
 430 #define CONFIG_ETHPRIME         "TSEC0"
 431
 432 #endif  /* CONFIG_TSEC_ENET */
 433
 434 /*
 435  * Configure on-board RTC
 436  */
 437 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 438 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 439
 440 /*
 441  * Environment
 442  */
 443 #ifndef CONFIG_SYS_RAMBOOT
 444         #define CONFIG_ENV_IS_IN_FLASH  1
 445         #define CONFIG_ENV_ADDR         \
 446                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 447         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 448         #define CONFIG_ENV_SIZE         0x2000
 449
 450 /* Address and size of Redundant Environment Sector     */
 451 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 452 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 453
 454 #else
 455         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 456         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 457         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 458         #define CONFIG_ENV_SIZE         0x2000
 459 #endif
 460
 461 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 462 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 463
 464 /*
 465  * BOOTP options
 466  */
 467 #define CONFIG_BOOTP_BOOTFILESIZE
 468 #define CONFIG_BOOTP_BOOTPATH
 469 #define CONFIG_BOOTP_GATEWAY
 470 #define CONFIG_BOOTP_HOSTNAME
 471
 472 /*
 473  * Command line configuration.
 474  */
 475 #define CONFIG_CMD_DATE
 476
 477 #if defined(CONFIG_PCI)
 478     #define CONFIG_CMD_PCI
 479 #endif
 480
 481 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 482
 483 /*
 484  * Miscellaneous configurable options
 485  */
 486 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 487 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 488
 489 #if defined(CONFIG_CMD_KGDB)
 490         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 491 #else
 492         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 493 #endif
 494
 495                                 /* Print Buffer Size */
 496 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 497 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 498                                 /* Boot Argument Buffer Size */
 499 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 500
 501 /*
 502  * For booting Linux, the board info and command line data
 503  * have to be in the first 256 MB of memory, since this is
 504  * the maximum mapped by the Linux kernel during initialization.
 505  */
 506                                 /* Initial Memory map for Linux*/
 507 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 508 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 509
 510 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 511
 512 #if 1 /*528/264*/
 513 #define CONFIG_SYS_HRCW_LOW (\
 514         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 515         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 516         HRCWL_CSB_TO_CLKIN |\
 517         HRCWL_VCO_1X2 |\
 518         HRCWL_CORE_TO_CSB_2X1)
 519 #elif 0 /*396/132*/
 520 #define CONFIG_SYS_HRCW_LOW (\
 521         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 522         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 523         HRCWL_CSB_TO_CLKIN |\
 524         HRCWL_VCO_1X4 |\
 525         HRCWL_CORE_TO_CSB_3X1)
 526 #elif 0 /*264/132*/
 527 #define CONFIG_SYS_HRCW_LOW (\
 528         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 529         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 530         HRCWL_CSB_TO_CLKIN |\
 531         HRCWL_VCO_1X4 |\
 532         HRCWL_CORE_TO_CSB_2X1)
 533 #elif 0 /*132/132*/
 534 #define CONFIG_SYS_HRCW_LOW (\
 535         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 536         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 537         HRCWL_CSB_TO_CLKIN |\
 538         HRCWL_VCO_1X4 |\
 539         HRCWL_CORE_TO_CSB_1X1)
 540 #elif 0 /*264/264 */
 541 #define CONFIG_SYS_HRCW_LOW (\
 542         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 543         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 544         HRCWL_CSB_TO_CLKIN |\
 545         HRCWL_VCO_1X4 |\
 546         HRCWL_CORE_TO_CSB_1X1)
 547 #endif
 548
 549 #ifdef CONFIG_PCISLAVE
 550 #define CONFIG_SYS_HRCW_HIGH (\
 551         HRCWH_PCI_AGENT |\
 552         HRCWH_64_BIT_PCI |\
 553         HRCWH_PCI1_ARBITER_DISABLE |\
 554         HRCWH_PCI2_ARBITER_DISABLE |\
 555         HRCWH_CORE_ENABLE |\
 556         HRCWH_FROM_0X00000100 |\
 557         HRCWH_BOOTSEQ_DISABLE |\
 558         HRCWH_SW_WATCHDOG_DISABLE |\
 559         HRCWH_ROM_LOC_LOCAL_16BIT |\
 560         HRCWH_TSEC1M_IN_GMII |\
 561         HRCWH_TSEC2M_IN_GMII)
 562 #else
 563 #if defined(PCI_64BIT)
 564 #define CONFIG_SYS_HRCW_HIGH (\
 565         HRCWH_PCI_HOST |\
 566         HRCWH_64_BIT_PCI |\
 567         HRCWH_PCI1_ARBITER_ENABLE |\
 568         HRCWH_PCI2_ARBITER_DISABLE |\
 569         HRCWH_CORE_ENABLE |\
 570         HRCWH_FROM_0X00000100 |\
 571         HRCWH_BOOTSEQ_DISABLE |\
 572         HRCWH_SW_WATCHDOG_DISABLE |\
 573         HRCWH_ROM_LOC_LOCAL_16BIT |\
 574         HRCWH_TSEC1M_IN_GMII |\
 575         HRCWH_TSEC2M_IN_GMII)
 576 #else
 577 #define CONFIG_SYS_HRCW_HIGH (\
 578         HRCWH_PCI_HOST |\
 579         HRCWH_32_BIT_PCI |\
 580         HRCWH_PCI1_ARBITER_ENABLE |\
 581         HRCWH_PCI2_ARBITER_ENABLE |\
 582         HRCWH_CORE_ENABLE |\
 583         HRCWH_FROM_0X00000100 |\
 584         HRCWH_BOOTSEQ_DISABLE |\
 585         HRCWH_SW_WATCHDOG_DISABLE |\
 586         HRCWH_ROM_LOC_LOCAL_16BIT |\
 587         HRCWH_TSEC1M_IN_GMII |\
 588         HRCWH_TSEC2M_IN_GMII)
 589 #endif /* PCI_64BIT */
 590 #endif /* CONFIG_PCISLAVE */
 591
 592 /*
 593  * System performance
 594  */
 595 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 596 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 597 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 598 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 599 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 600 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 601
 602 /* System IO Config */
 603 #define CONFIG_SYS_SICRH 0
 604 #define CONFIG_SYS_SICRL SICRL_LDP_A
 605
 606 #define CONFIG_SYS_HID0_INIT    0x000000000
 607 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 608                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 609
 610 /* #define CONFIG_SYS_HID0_FINAL        (\
 611         HID0_ENABLE_INSTRUCTION_CACHE |\
 612         HID0_ENABLE_M_BIT |\
 613         HID0_ENABLE_ADDRESS_BROADCAST) */
 614
 615 #define CONFIG_SYS_HID2 HID2_HBE
 616 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 617
 618 /* DDR @ 0x00000000 */
 619 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 620                                 | BATL_PP_RW \
 621                                 | BATL_MEMCOHERENCE)
 622 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 623                                 | BATU_BL_256M \
 624                                 | BATU_VS \
 625                                 | BATU_VP)
 626
 627 /* PCI @ 0x80000000 */
 628 #ifdef CONFIG_PCI
 629 #define CONFIG_PCI_INDIRECT_BRIDGE
 630 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 631                                 | BATL_PP_RW \
 632                                 | BATL_MEMCOHERENCE)
 633 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 634                                 | BATU_BL_256M \
 635                                 | BATU_VS \
 636                                 | BATU_VP)
 637 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 638                                 | BATL_PP_RW \
 639                                 | BATL_CACHEINHIBIT \
 640                                 | BATL_GUARDEDSTORAGE)
 641 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 642                                 | BATU_BL_256M \
 643                                 | BATU_VS \
 644                                 | BATU_VP)
 645 #else
 646 #define CONFIG_SYS_IBAT1L       (0)
 647 #define CONFIG_SYS_IBAT1U       (0)
 648 #define CONFIG_SYS_IBAT2L       (0)
 649 #define CONFIG_SYS_IBAT2U       (0)
 650 #endif
 651
 652 #ifdef CONFIG_MPC83XX_PCI2
 653 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 654                                 | BATL_PP_RW \
 655                                 | BATL_MEMCOHERENCE)
 656 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 657                                 | BATU_BL_256M \
 658                                 | BATU_VS \
 659                                 | BATU_VP)
 660 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 661                                 | BATL_PP_RW \
 662                                 | BATL_CACHEINHIBIT \
 663                                 | BATL_GUARDEDSTORAGE)
 664 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 665                                 | BATU_BL_256M \
 666                                 | BATU_VS \
 667                                 | BATU_VP)
 668 #else
 669 #define CONFIG_SYS_IBAT3L       (0)
 670 #define CONFIG_SYS_IBAT3U       (0)
 671 #define CONFIG_SYS_IBAT4L       (0)
 672 #define CONFIG_SYS_IBAT4U       (0)
 673 #endif
 674
 675 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 676 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 677                                 | BATL_PP_RW \
 678                                 | BATL_CACHEINHIBIT \
 679                                 | BATL_GUARDEDSTORAGE)
 680 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 681                                 | BATU_BL_256M \
 682                                 | BATU_VS \
 683                                 | BATU_VP)
 684
 685 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 686 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 687                                 | BATL_PP_RW \
 688                                 | BATL_MEMCOHERENCE \
 689                                 | BATL_GUARDEDSTORAGE)
 690 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 691                                 | BATU_BL_256M \
 692                                 | BATU_VS \
 693                                 | BATU_VP)
 694
 695 #define CONFIG_SYS_IBAT7L       (0)
 696 #define CONFIG_SYS_IBAT7U       (0)
 697
 698 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 699 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 700 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 701 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 702 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 703 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 704 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 705 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 706 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 707 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 708 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 709 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 710 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 711 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 712 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 713 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 714
 715 #if defined(CONFIG_CMD_KGDB)
 716 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 717 #endif
 718
 719 /*
 720  * Environment Configuration
 721  */
 722 #define CONFIG_ENV_OVERWRITE
 723
 724 #if defined(CONFIG_TSEC_ENET)
 725 #define CONFIG_HAS_ETH1
 726 #define CONFIG_HAS_ETH0
 727 #endif
 728
 729 #define CONFIG_HOSTNAME         mpc8349emds
 730 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 731 #define CONFIG_BOOTFILE         "uImage"
 732
 733 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 734
 735 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 736
 737 #define CONFIG_BAUDRATE  115200
 738
 739 #define CONFIG_PREBOOT  "echo;" \
 740         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 741         "echo"
 742
 743 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 744         "netdev=eth0\0"                                                 \
 745         "hostname=mpc8349emds\0"                                        \
 746         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 747                 "nfsroot=${serverip}:${rootpath}\0"                     \
 748         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 749         "addip=setenv bootargs ${bootargs} "                            \
 750                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 751                 ":${hostname}:${netdev}:off panic=1\0"                  \
 752         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 753         "flash_nfs=run nfsargs addip addtty;"                           \
 754                 "bootm ${kernel_addr}\0"                                \
 755         "flash_self=run ramargs addip addtty;"                          \
 756                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 757         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 758                 "bootm\0"                                               \
 759         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 760         "update=protect off fe000000 fe03ffff; "                        \
 761                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 762         "upd=run load update\0"                                         \
 763         "fdtaddr=780000\0"                                              \
 764         "fdtfile=mpc834x_mds.dtb\0"                                     \
 765         ""
 766
 767 #define CONFIG_NFSBOOTCOMMAND                                           \
 768         "setenv bootargs root=/dev/nfs rw "                             \
 769                 "nfsroot=$serverip:$rootpath "                          \
 770                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 771                                                         "$netdev:off "  \
 772                 "console=$consoledev,$baudrate $othbootargs;"           \
 773         "tftp $loadaddr $bootfile;"                                     \
 774         "tftp $fdtaddr $fdtfile;"                                       \
 775         "bootm $loadaddr - $fdtaddr"
 776
 777 #define CONFIG_RAMBOOTCOMMAND                                           \
 778         "setenv bootargs root=/dev/ram rw "                             \
 779                 "console=$consoledev,$baudrate $othbootargs;"           \
 780         "tftp $ramdiskaddr $ramdiskfile;"                               \
 781         "tftp $loadaddr $bootfile;"                                     \
 782         "tftp $fdtaddr $fdtfile;"                                       \
 783         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 784
 785 #define CONFIG_BOOTCOMMAND      "run flash_self"
 786
 787 #endif  /* __CONFIG_H */