include/configs/MPC832XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * High Level Configuration Options
  11  */
  12 #define CONFIG_E300             1       /* E300 family */
  13 #define CONFIG_QE               1       /* Has QE */
  14
  15 /*
  16  * Hardware Reset Configuration Word
  17  */
  18 #define CONFIG_SYS_HRCW_LOW (\
  19         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  20         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  21         HRCWL_VCO_1X2 |\
  22         HRCWL_CSB_TO_CLKIN_2X1 |\
  23         HRCWL_CORE_TO_CSB_2X1 |\
  24         HRCWL_CE_PLL_VCO_DIV_2 |\
  25         HRCWL_CE_PLL_DIV_1X1 |\
  26         HRCWL_CE_TO_PLL_1X3)
  27
  28 #ifdef CONFIG_PCISLAVE
  29 #define CONFIG_SYS_HRCW_HIGH (\
  30         HRCWH_PCI_AGENT |\
  31         HRCWH_PCI1_ARBITER_DISABLE |\
  32         HRCWH_CORE_ENABLE |\
  33         HRCWH_FROM_0XFFF00100 |\
  34         HRCWH_BOOTSEQ_DISABLE |\
  35         HRCWH_SW_WATCHDOG_DISABLE |\
  36         HRCWH_ROM_LOC_LOCAL_16BIT |\
  37         HRCWH_BIG_ENDIAN |\
  38         HRCWH_LALE_NORMAL)
  39 #else
  40 #define CONFIG_SYS_HRCW_HIGH (\
  41         HRCWH_PCI_HOST |\
  42         HRCWH_PCI1_ARBITER_ENABLE |\
  43         HRCWH_CORE_ENABLE |\
  44         HRCWH_FROM_0X00000100 |\
  45         HRCWH_BOOTSEQ_DISABLE |\
  46         HRCWH_SW_WATCHDOG_DISABLE |\
  47         HRCWH_ROM_LOC_LOCAL_16BIT |\
  48         HRCWH_BIG_ENDIAN |\
  49         HRCWH_LALE_NORMAL)
  50 #endif
  51
  52 /*
  53  * System IO Config
  54  */
  55 #define CONFIG_SYS_SICRL                0x00000000
  56
  57 /*
  58  * IMMR new address
  59  */
  60 #define CONFIG_SYS_IMMR         0xE0000000
  61
  62 /*
  63  * DDR Setup
  64  */
  65 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  66 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  67 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  69
  70 #undef CONFIG_SPD_EEPROM
  71 #if defined(CONFIG_SPD_EEPROM)
  72 /* Determine DDR configuration from I2C interface
  73  */
  74 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  75 #else
  76 /* Manually set up DDR parameters
  77  */
  78 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
  79 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  80                                         | CSCONFIG_AP \
  81                                         | CSCONFIG_ODT_WR_CFG \
  82                                         | CSCONFIG_ROW_BIT_13 \
  83                                         | CSCONFIG_COL_BIT_10)
  84                                         /* 0x80840102 */
  85 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
  86                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
  87                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
  88                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
  89                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  90                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  91                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  92                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  93                                         /* 0x00220802 */
  94 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  95                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  96                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  97                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  98                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
  99                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
 100                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 101                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
 102                                         /* 0x3935D322 */
 103 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 104                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 105                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 106                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 107                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 108                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 109                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
 110                                 /* 0x0F9048CA */
 111 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 112 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 113                                         /* 0x02000000 */
 114 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
 115                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
 116                                         /* 0x44400232 */
 117 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 118 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 119                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 120                                         /* 0x03200064 */
 121 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
 122 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 123                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 124                                         | SDRAM_CFG_32_BE)
 125                                         /* 0x43080000 */
 126 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 127 #endif
 128
 129 /*
 130  * Memory test
 131  */
 132 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 133 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
 134 #define CONFIG_SYS_MEMTEST_END          0x00100000
 135
 136 /*
 137  * The reserved memory
 138  */
 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 140
 141 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 142 #define CONFIG_SYS_RAMBOOT
 143 #else
 144 #undef  CONFIG_SYS_RAMBOOT
 145 #endif
 146
 147 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 148 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 149 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 150
 151 /*
 152  * Initial RAM Base Address Setup
 153  */
 154 #define CONFIG_SYS_INIT_RAM_LOCK        1
 155 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 156 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 157 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 158                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 159
 160 /*
 161  * Local Bus Configuration & Clock Setup
 162  */
 163 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 164 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 165 #define CONFIG_SYS_LBC_LBCR             0x00000000
 166
 167 /*
 168  * FLASH on the Local Bus
 169  */
 170 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 171 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 172
 173                                         /* Window base at flash base */
 174 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 175 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 176
 177 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 178                                 | BR_PS_16      /* 16 bit port */ \
 179                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 180                                 | BR_V)         /* valid */
 181 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 182                                 | OR_GPCM_XAM \
 183                                 | OR_GPCM_CSNT \
 184                                 | OR_GPCM_ACS_DIV2 \
 185                                 | OR_GPCM_XACS \
 186                                 | OR_GPCM_SCY_15 \
 187                                 | OR_GPCM_TRLX_SET \
 188                                 | OR_GPCM_EHTR_SET \
 189                                 | OR_GPCM_EAD)
 190                                 /* 0xfe006ff7 */
 191
 192 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 193 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 194
 195 #undef CONFIG_SYS_FLASH_CHECKSUM
 196
 197 /*
 198  * BCSR on the Local Bus
 199  */
 200 #define CONFIG_SYS_BCSR                 0xF8000000
 201                                         /* Access window base at BCSR base */
 202 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 203 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 204
 205 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 206                                         | BR_PS_8 \
 207                                         | BR_MS_GPCM \
 208                                         | BR_V)
 209 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 210                                         | OR_GPCM_XAM \
 211                                         | OR_GPCM_CSNT \
 212                                         | OR_GPCM_XACS \
 213                                         | OR_GPCM_SCY_15 \
 214                                         | OR_GPCM_TRLX_SET \
 215                                         | OR_GPCM_EHTR_SET \
 216                                         | OR_GPCM_EAD)
 217                                         /* 0xFFFFE9F7 */
 218
 219 /*
 220  * Windows to access PIB via local bus
 221  */
 222                                         /* PIB window base 0xF8008000 */
 223 #define CONFIG_SYS_PIB_BASE             0xF8008000
 224 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 225 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PIB_BASE
 226 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 227
 228 /*
 229  * CS2 on Local Bus, to PIB
 230  */
 231 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_PIB_BASE \
 232                                 | BR_PS_8 \
 233                                 | BR_MS_GPCM \
 234                                 | BR_V)
 235                                 /* 0xF8008801 */
 236 #define CONFIG_SYS_OR2_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 237                                 | OR_GPCM_XAM \
 238                                 | OR_GPCM_CSNT \
 239                                 | OR_GPCM_XACS \
 240                                 | OR_GPCM_SCY_15 \
 241                                 | OR_GPCM_TRLX_SET \
 242                                 | OR_GPCM_EHTR_SET \
 243                                 | OR_GPCM_EAD)
 244                                 /* 0xffffe9f7 */
 245
 246 /*
 247  * CS3 on Local Bus, to PIB
 248  */
 249 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIB_BASE + \
 250                                         CONFIG_SYS_PIB_WINDOW_SIZE) \
 251                                 | BR_PS_8 \
 252                                 | BR_MS_GPCM \
 253                                 | BR_V)
 254                                 /* 0xF8010801 */
 255 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 256                                 | OR_GPCM_XAM \
 257                                 | OR_GPCM_CSNT \
 258                                 | OR_GPCM_XACS \
 259                                 | OR_GPCM_SCY_15 \
 260                                 | OR_GPCM_TRLX_SET \
 261                                 | OR_GPCM_EHTR_SET \
 262                                 | OR_GPCM_EAD)
 263                                 /* 0xffffe9f7 */
 264
 265 /*
 266  * Serial Port
 267  */
 268 #define CONFIG_SYS_NS16550_SERIAL
 269 #define CONFIG_SYS_NS16550_REG_SIZE     1
 270 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 271
 272 #define CONFIG_SYS_BAUDRATE_TABLE  \
 273                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 274
 275 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 276 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 277
 278 /* I2C */
 279 #define CONFIG_SYS_I2C
 280 #define CONFIG_SYS_I2C_FSL
 281 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 282 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 283 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 284 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 285
 286 /*
 287  * Config on-board RTC
 288  */
 289 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 290 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 291
 292 /*
 293  * General PCI
 294  * Addresses are mapped 1-1.
 295  */
 296 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 297 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 298 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 299 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 300 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 301 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 302 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 303 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 304 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 305
 306 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 307 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 308 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 309
 310 #ifdef CONFIG_PCI
 311 #define CONFIG_PCI_INDIRECT_BRIDGE
 312
 313 #define CONFIG_83XX_PCI_STREAMING
 314
 315 #undef CONFIG_EEPRO100
 316 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 317 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 318
 319 #endif  /* CONFIG_PCI */
 320
 321 /*
 322  * QE UEC ethernet configuration
 323  */
 324 #define CONFIG_UEC_ETH
 325 #define CONFIG_ETHPRIME         "UEC0"
 326
 327 #define CONFIG_UEC_ETH1         /* ETH3 */
 328
 329 #ifdef CONFIG_UEC_ETH1
 330 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 331 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 332 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 333 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 334 #define CONFIG_SYS_UEC1_PHY_ADDR        3
 335 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 336 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 337 #endif
 338
 339 #define CONFIG_UEC_ETH2         /* ETH4 */
 340
 341 #ifdef CONFIG_UEC_ETH2
 342 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 343 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 344 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 345 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 346 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 347 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 348 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 349 #endif
 350
 351 /*
 352  * Environment
 353  */
 354 #ifndef CONFIG_SYS_RAMBOOT
 355         #define CONFIG_ENV_ADDR         \
 356                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 357         #define CONFIG_ENV_SECT_SIZE    0x20000
 358         #define CONFIG_ENV_SIZE         0x2000
 359 #else
 360         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 361         #define CONFIG_ENV_SIZE         0x2000
 362 #endif
 363
 364 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 365 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 366
 367 /*
 368  * BOOTP options
 369  */
 370 #define CONFIG_BOOTP_BOOTFILESIZE
 371
 372 /*
 373  * Command line configuration.
 374  */
 375
 376 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 377
 378 /*
 379  * Miscellaneous configurable options
 380  */
 381 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 382
 383 /*
 384  * For booting Linux, the board info and command line data
 385  * have to be in the first 256 MB of memory, since this is
 386  * the maximum mapped by the Linux kernel during initialization.
 387  */
 388                                         /* Initial Memory map for Linux */
 389 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 390 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 391
 392 /*
 393  * Core HID Setup
 394  */
 395 #define CONFIG_SYS_HID0_INIT    0x000000000
 396 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 397                                  HID0_ENABLE_INSTRUCTION_CACHE)
 398 #define CONFIG_SYS_HID2         HID2_HBE
 399
 400 /*
 401  * MMU Setup
 402  */
 403
 404 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 405
 406 /* DDR: cache cacheable */
 407 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 408                                 | BATL_PP_RW \
 409                                 | BATL_MEMCOHERENCE)
 410 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 411                                 | BATU_BL_256M \
 412                                 | BATU_VS \
 413                                 | BATU_VP)
 414 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 415 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 416
 417 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 418 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 419                                 | BATL_PP_RW \
 420                                 | BATL_CACHEINHIBIT \
 421                                 | BATL_GUARDEDSTORAGE)
 422 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 423                                 | BATU_BL_4M \
 424                                 | BATU_VS \
 425                                 | BATU_VP)
 426 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 427 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 428
 429 /* BCSR: cache-inhibit and guarded */
 430 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 431                                 | BATL_PP_RW \
 432                                 | BATL_CACHEINHIBIT \
 433                                 | BATL_GUARDEDSTORAGE)
 434 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 435                                 | BATU_BL_128K \
 436                                 | BATU_VS \
 437                                 | BATU_VP)
 438 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 439 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 440
 441 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 442 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 443                                 | BATL_PP_RW \
 444                                 | BATL_MEMCOHERENCE)
 445 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 446                                 | BATU_BL_32M \
 447                                 | BATU_VS \
 448                                 | BATU_VP)
 449 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 450                                 | BATL_PP_RW \
 451                                 | BATL_CACHEINHIBIT \
 452                                 | BATL_GUARDEDSTORAGE)
 453 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 454
 455 #define CONFIG_SYS_IBAT4L       (0)
 456 #define CONFIG_SYS_IBAT4U       (0)
 457 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 458 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 459
 460 /* Stack in dcache: cacheable, no memory coherence */
 461 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 462 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 463                                 | BATU_BL_128K \
 464                                 | BATU_VS \
 465                                 | BATU_VP)
 466 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 467 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 468
 469 #ifdef CONFIG_PCI
 470 /* PCI MEM space: cacheable */
 471 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 472                                 | BATL_PP_RW \
 473                                 | BATL_MEMCOHERENCE)
 474 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 475                                 | BATU_BL_256M \
 476                                 | BATU_VS \
 477                                 | BATU_VP)
 478 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 479 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 480 /* PCI MMIO space: cache-inhibit and guarded */
 481 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 482                                 | BATL_PP_RW \
 483                                 | BATL_CACHEINHIBIT \
 484                                 | BATL_GUARDEDSTORAGE)
 485 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 486                                 | BATU_BL_256M \
 487                                 | BATU_VS \
 488                                 | BATU_VP)
 489 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 490 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 491 #else
 492 #define CONFIG_SYS_IBAT6L       (0)
 493 #define CONFIG_SYS_IBAT6U       (0)
 494 #define CONFIG_SYS_IBAT7L       (0)
 495 #define CONFIG_SYS_IBAT7U       (0)
 496 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 497 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 498 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 499 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 500 #endif
 501
 502 #if defined(CONFIG_CMD_KGDB)
 503 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 504 #endif
 505
 506 /*
 507  * Environment Configuration
 508  */ #define CONFIG_ENV_OVERWRITE
 509
 510 #if defined(CONFIG_UEC_ETH)
 511 #define CONFIG_HAS_ETH0
 512 #define CONFIG_HAS_ETH1
 513 #endif
 514
 515 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 516
 517 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 518         "netdev=eth0\0"                                                 \
 519         "consoledev=ttyS0\0"                                            \
 520         "ramdiskaddr=1000000\0"                                         \
 521         "ramdiskfile=ramfs.83xx\0"                                      \
 522         "fdtaddr=780000\0"                                              \
 523         "fdtfile=mpc832x_mds.dtb\0"                                     \
 524         ""
 525
 526 #define CONFIG_NFSBOOTCOMMAND                                           \
 527         "setenv bootargs root=/dev/nfs rw "                             \
 528                 "nfsroot=$serverip:$rootpath "                          \
 529                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 530                                                         "$netdev:off "  \
 531                 "console=$consoledev,$baudrate $othbootargs;"           \
 532         "tftp $loadaddr $bootfile;"                                     \
 533         "tftp $fdtaddr $fdtfile;"                                       \
 534         "bootm $loadaddr - $fdtaddr"
 535
 536 #define CONFIG_RAMBOOTCOMMAND                                           \
 537         "setenv bootargs root=/dev/ram rw "                             \
 538                 "console=$consoledev,$baudrate $othbootargs;"           \
 539         "tftp $ramdiskaddr $ramdiskfile;"                               \
 540         "tftp $loadaddr $bootfile;"                                     \
 541         "tftp $fdtaddr $fdtfile;"                                       \
 542         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 543
 544 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 545
 546 #endif  /* __CONFIG_H */