include/configs/MPC832XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * High Level Configuration Options
  11  */
  12 #define CONFIG_E300             1       /* E300 family */
  13 #define CONFIG_QE               1       /* Has QE */
  14 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
  15 #define CONFIG_MPC832XEMDS      1       /* MPC832XEMDS board specific */
  16
  17 /*
  18  * System Clock Setup
  19  */
  20 #ifdef CONFIG_PCISLAVE
  21 #define CONFIG_83XX_PCICLK      66000000        /* in HZ */
  22 #else
  23 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  24 #endif
  25
  26 #ifndef CONFIG_SYS_CLK_FREQ
  27 #define CONFIG_SYS_CLK_FREQ     66000000
  28 #endif
  29
  30 /*
  31  * Hardware Reset Configuration Word
  32  */
  33 #define CONFIG_SYS_HRCW_LOW (\
  34         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  35         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  36         HRCWL_VCO_1X2 |\
  37         HRCWL_CSB_TO_CLKIN_2X1 |\
  38         HRCWL_CORE_TO_CSB_2X1 |\
  39         HRCWL_CE_PLL_VCO_DIV_2 |\
  40         HRCWL_CE_PLL_DIV_1X1 |\
  41         HRCWL_CE_TO_PLL_1X3)
  42
  43 #ifdef CONFIG_PCISLAVE
  44 #define CONFIG_SYS_HRCW_HIGH (\
  45         HRCWH_PCI_AGENT |\
  46         HRCWH_PCI1_ARBITER_DISABLE |\
  47         HRCWH_CORE_ENABLE |\
  48         HRCWH_FROM_0XFFF00100 |\
  49         HRCWH_BOOTSEQ_DISABLE |\
  50         HRCWH_SW_WATCHDOG_DISABLE |\
  51         HRCWH_ROM_LOC_LOCAL_16BIT |\
  52         HRCWH_BIG_ENDIAN |\
  53         HRCWH_LALE_NORMAL)
  54 #else
  55 #define CONFIG_SYS_HRCW_HIGH (\
  56         HRCWH_PCI_HOST |\
  57         HRCWH_PCI1_ARBITER_ENABLE |\
  58         HRCWH_CORE_ENABLE |\
  59         HRCWH_FROM_0X00000100 |\
  60         HRCWH_BOOTSEQ_DISABLE |\
  61         HRCWH_SW_WATCHDOG_DISABLE |\
  62         HRCWH_ROM_LOC_LOCAL_16BIT |\
  63         HRCWH_BIG_ENDIAN |\
  64         HRCWH_LALE_NORMAL)
  65 #endif
  66
  67 /*
  68  * System IO Config
  69  */
  70 #define CONFIG_SYS_SICRL                0x00000000
  71
  72 /*
  73  * IMMR new address
  74  */
  75 #define CONFIG_SYS_IMMR         0xE0000000
  76
  77 /*
  78  * DDR Setup
  79  */
  80 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  81 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  82 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  83 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  84
  85 #undef CONFIG_SPD_EEPROM
  86 #if defined(CONFIG_SPD_EEPROM)
  87 /* Determine DDR configuration from I2C interface
  88  */
  89 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  90 #else
  91 /* Manually set up DDR parameters
  92  */
  93 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
  94 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  95                                         | CSCONFIG_AP \
  96                                         | CSCONFIG_ODT_WR_CFG \
  97                                         | CSCONFIG_ROW_BIT_13 \
  98                                         | CSCONFIG_COL_BIT_10)
  99                                         /* 0x80840102 */
 100 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
 101                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
 102                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
 103                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
 104                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 105                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 106                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 107                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 108                                         /* 0x00220802 */
 109 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 110                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 111                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 112                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 113                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
 114                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
 115                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 116                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
 117                                         /* 0x3935D322 */
 118 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 119                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 120                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 121                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 122                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 123                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 124                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
 125                                 /* 0x0F9048CA */
 126 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 127 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 128                                         /* 0x02000000 */
 129 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
 130                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
 131                                         /* 0x44400232 */
 132 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 133 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 134                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 135                                         /* 0x03200064 */
 136 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
 137 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 138                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 139                                         | SDRAM_CFG_32_BE)
 140                                         /* 0x43080000 */
 141 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 142 #endif
 143
 144 /*
 145  * Memory test
 146  */
 147 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 148 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
 149 #define CONFIG_SYS_MEMTEST_END          0x00100000
 150
 151 /*
 152  * The reserved memory
 153  */
 154 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 155
 156 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 157 #define CONFIG_SYS_RAMBOOT
 158 #else
 159 #undef  CONFIG_SYS_RAMBOOT
 160 #endif
 161
 162 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 163 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 164 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 165
 166 /*
 167  * Initial RAM Base Address Setup
 168  */
 169 #define CONFIG_SYS_INIT_RAM_LOCK        1
 170 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 171 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 172 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 173                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 174
 175 /*
 176  * Local Bus Configuration & Clock Setup
 177  */
 178 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 179 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 180 #define CONFIG_SYS_LBC_LBCR             0x00000000
 181
 182 /*
 183  * FLASH on the Local Bus
 184  */
 185 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 186 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 187
 188                                         /* Window base at flash base */
 189 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 190 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 191
 192 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 193                                 | BR_PS_16      /* 16 bit port */ \
 194                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 195                                 | BR_V)         /* valid */
 196 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 197                                 | OR_GPCM_XAM \
 198                                 | OR_GPCM_CSNT \
 199                                 | OR_GPCM_ACS_DIV2 \
 200                                 | OR_GPCM_XACS \
 201                                 | OR_GPCM_SCY_15 \
 202                                 | OR_GPCM_TRLX_SET \
 203                                 | OR_GPCM_EHTR_SET \
 204                                 | OR_GPCM_EAD)
 205                                 /* 0xfe006ff7 */
 206
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 208 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 209
 210 #undef CONFIG_SYS_FLASH_CHECKSUM
 211
 212 /*
 213  * BCSR on the Local Bus
 214  */
 215 #define CONFIG_SYS_BCSR                 0xF8000000
 216                                         /* Access window base at BCSR base */
 217 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 218 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 219
 220 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 221                                         | BR_PS_8 \
 222                                         | BR_MS_GPCM \
 223                                         | BR_V)
 224 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 225                                         | OR_GPCM_XAM \
 226                                         | OR_GPCM_CSNT \
 227                                         | OR_GPCM_XACS \
 228                                         | OR_GPCM_SCY_15 \
 229                                         | OR_GPCM_TRLX_SET \
 230                                         | OR_GPCM_EHTR_SET \
 231                                         | OR_GPCM_EAD)
 232                                         /* 0xFFFFE9F7 */
 233
 234 /*
 235  * Windows to access PIB via local bus
 236  */
 237                                         /* PIB window base 0xF8008000 */
 238 #define CONFIG_SYS_PIB_BASE             0xF8008000
 239 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 240 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PIB_BASE
 241 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 242
 243 /*
 244  * CS2 on Local Bus, to PIB
 245  */
 246 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_PIB_BASE \
 247                                 | BR_PS_8 \
 248                                 | BR_MS_GPCM \
 249                                 | BR_V)
 250                                 /* 0xF8008801 */
 251 #define CONFIG_SYS_OR2_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 252                                 | OR_GPCM_XAM \
 253                                 | OR_GPCM_CSNT \
 254                                 | OR_GPCM_XACS \
 255                                 | OR_GPCM_SCY_15 \
 256                                 | OR_GPCM_TRLX_SET \
 257                                 | OR_GPCM_EHTR_SET \
 258                                 | OR_GPCM_EAD)
 259                                 /* 0xffffe9f7 */
 260
 261 /*
 262  * CS3 on Local Bus, to PIB
 263  */
 264 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIB_BASE + \
 265                                         CONFIG_SYS_PIB_WINDOW_SIZE) \
 266                                 | BR_PS_8 \
 267                                 | BR_MS_GPCM \
 268                                 | BR_V)
 269                                 /* 0xF8010801 */
 270 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 271                                 | OR_GPCM_XAM \
 272                                 | OR_GPCM_CSNT \
 273                                 | OR_GPCM_XACS \
 274                                 | OR_GPCM_SCY_15 \
 275                                 | OR_GPCM_TRLX_SET \
 276                                 | OR_GPCM_EHTR_SET \
 277                                 | OR_GPCM_EAD)
 278                                 /* 0xffffe9f7 */
 279
 280 /*
 281  * Serial Port
 282  */
 283 #define CONFIG_SYS_NS16550_SERIAL
 284 #define CONFIG_SYS_NS16550_REG_SIZE     1
 285 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 286
 287 #define CONFIG_SYS_BAUDRATE_TABLE  \
 288                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 289
 290 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 291 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 292
 293 /* I2C */
 294 #define CONFIG_SYS_I2C
 295 #define CONFIG_SYS_I2C_FSL
 296 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 297 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 298 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 299 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 300
 301 /*
 302  * Config on-board RTC
 303  */
 304 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 305 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 306
 307 /*
 308  * General PCI
 309  * Addresses are mapped 1-1.
 310  */
 311 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 312 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 313 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 314 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 315 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 316 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 317 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 318 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 319 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 320
 321 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 322 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 323 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 324
 325 #ifdef CONFIG_PCI
 326 #define CONFIG_PCI_INDIRECT_BRIDGE
 327
 328 #define CONFIG_83XX_PCI_STREAMING
 329
 330 #undef CONFIG_EEPRO100
 331 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 332 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 333
 334 #endif  /* CONFIG_PCI */
 335
 336 /*
 337  * QE UEC ethernet configuration
 338  */
 339 #define CONFIG_UEC_ETH
 340 #define CONFIG_ETHPRIME         "UEC0"
 341
 342 #define CONFIG_UEC_ETH1         /* ETH3 */
 343
 344 #ifdef CONFIG_UEC_ETH1
 345 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 346 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 347 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 348 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 349 #define CONFIG_SYS_UEC1_PHY_ADDR        3
 350 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 351 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 352 #endif
 353
 354 #define CONFIG_UEC_ETH2         /* ETH4 */
 355
 356 #ifdef CONFIG_UEC_ETH2
 357 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 358 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 359 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 360 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 361 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 362 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 363 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 364 #endif
 365
 366 /*
 367  * Environment
 368  */
 369 #ifndef CONFIG_SYS_RAMBOOT
 370         #define CONFIG_ENV_ADDR         \
 371                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 372         #define CONFIG_ENV_SECT_SIZE    0x20000
 373         #define CONFIG_ENV_SIZE         0x2000
 374 #else
 375         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 376         #define CONFIG_ENV_SIZE         0x2000
 377 #endif
 378
 379 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 380 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 381
 382 /*
 383  * BOOTP options
 384  */
 385 #define CONFIG_BOOTP_BOOTFILESIZE
 386
 387 /*
 388  * Command line configuration.
 389  */
 390
 391 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 392
 393 /*
 394  * Miscellaneous configurable options
 395  */
 396 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 397
 398 /*
 399  * For booting Linux, the board info and command line data
 400  * have to be in the first 256 MB of memory, since this is
 401  * the maximum mapped by the Linux kernel during initialization.
 402  */
 403                                         /* Initial Memory map for Linux */
 404 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 405 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 406
 407 /*
 408  * Core HID Setup
 409  */
 410 #define CONFIG_SYS_HID0_INIT    0x000000000
 411 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 412                                  HID0_ENABLE_INSTRUCTION_CACHE)
 413 #define CONFIG_SYS_HID2         HID2_HBE
 414
 415 /*
 416  * MMU Setup
 417  */
 418
 419 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 420
 421 /* DDR: cache cacheable */
 422 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 423                                 | BATL_PP_RW \
 424                                 | BATL_MEMCOHERENCE)
 425 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 426                                 | BATU_BL_256M \
 427                                 | BATU_VS \
 428                                 | BATU_VP)
 429 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 430 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 431
 432 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 433 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 434                                 | BATL_PP_RW \
 435                                 | BATL_CACHEINHIBIT \
 436                                 | BATL_GUARDEDSTORAGE)
 437 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 438                                 | BATU_BL_4M \
 439                                 | BATU_VS \
 440                                 | BATU_VP)
 441 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 442 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 443
 444 /* BCSR: cache-inhibit and guarded */
 445 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 446                                 | BATL_PP_RW \
 447                                 | BATL_CACHEINHIBIT \
 448                                 | BATL_GUARDEDSTORAGE)
 449 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 450                                 | BATU_BL_128K \
 451                                 | BATU_VS \
 452                                 | BATU_VP)
 453 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 454 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 455
 456 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 457 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 458                                 | BATL_PP_RW \
 459                                 | BATL_MEMCOHERENCE)
 460 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 461                                 | BATU_BL_32M \
 462                                 | BATU_VS \
 463                                 | BATU_VP)
 464 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 465                                 | BATL_PP_RW \
 466                                 | BATL_CACHEINHIBIT \
 467                                 | BATL_GUARDEDSTORAGE)
 468 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 469
 470 #define CONFIG_SYS_IBAT4L       (0)
 471 #define CONFIG_SYS_IBAT4U       (0)
 472 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 473 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 474
 475 /* Stack in dcache: cacheable, no memory coherence */
 476 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 477 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 478                                 | BATU_BL_128K \
 479                                 | BATU_VS \
 480                                 | BATU_VP)
 481 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 482 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 483
 484 #ifdef CONFIG_PCI
 485 /* PCI MEM space: cacheable */
 486 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 487                                 | BATL_PP_RW \
 488                                 | BATL_MEMCOHERENCE)
 489 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 490                                 | BATU_BL_256M \
 491                                 | BATU_VS \
 492                                 | BATU_VP)
 493 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 494 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 495 /* PCI MMIO space: cache-inhibit and guarded */
 496 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 497                                 | BATL_PP_RW \
 498                                 | BATL_CACHEINHIBIT \
 499                                 | BATL_GUARDEDSTORAGE)
 500 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 501                                 | BATU_BL_256M \
 502                                 | BATU_VS \
 503                                 | BATU_VP)
 504 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 505 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 506 #else
 507 #define CONFIG_SYS_IBAT6L       (0)
 508 #define CONFIG_SYS_IBAT6U       (0)
 509 #define CONFIG_SYS_IBAT7L       (0)
 510 #define CONFIG_SYS_IBAT7U       (0)
 511 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 512 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 513 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 514 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 515 #endif
 516
 517 #if defined(CONFIG_CMD_KGDB)
 518 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 519 #endif
 520
 521 /*
 522  * Environment Configuration
 523  */ #define CONFIG_ENV_OVERWRITE
 524
 525 #if defined(CONFIG_UEC_ETH)
 526 #define CONFIG_HAS_ETH0
 527 #define CONFIG_HAS_ETH1
 528 #endif
 529
 530 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 531
 532 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 533         "netdev=eth0\0"                                                 \
 534         "consoledev=ttyS0\0"                                            \
 535         "ramdiskaddr=1000000\0"                                         \
 536         "ramdiskfile=ramfs.83xx\0"                                      \
 537         "fdtaddr=780000\0"                                              \
 538         "fdtfile=mpc832x_mds.dtb\0"                                     \
 539         ""
 540
 541 #define CONFIG_NFSBOOTCOMMAND                                           \
 542         "setenv bootargs root=/dev/nfs rw "                             \
 543                 "nfsroot=$serverip:$rootpath "                          \
 544                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 545                                                         "$netdev:off "  \
 546                 "console=$consoledev,$baudrate $othbootargs;"           \
 547         "tftp $loadaddr $bootfile;"                                     \
 548         "tftp $fdtaddr $fdtfile;"                                       \
 549         "bootm $loadaddr - $fdtaddr"
 550
 551 #define CONFIG_RAMBOOTCOMMAND                                           \
 552         "setenv bootargs root=/dev/ram rw "                             \
 553                 "console=$consoledev,$baudrate $othbootargs;"           \
 554         "tftp $ramdiskaddr $ramdiskfile;"                               \
 555         "tftp $loadaddr $bootfile;"                                     \
 556         "tftp $fdtaddr $fdtfile;"                                       \
 557         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 558
 559 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 560
 561 #endif  /* __CONFIG_H */