Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
[platform/kernel/u-boot.git] / include / configs / MPC832XEMDS.h
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /*
11  * High Level Configuration Options
12  */
13 #define CONFIG_E300             1       /* E300 family */
14 #define CONFIG_QE               1       /* Has QE */
15 #define CONFIG_MPC83xx          1       /* MPC83xx family */
16 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
17 #define CONFIG_MPC832XEMDS      1       /* MPC832XEMDS board specific */
18
19 #define CONFIG_SYS_TEXT_BASE    0xFE000000
20
21 /*
22  * System Clock Setup
23  */
24 #ifdef CONFIG_PCISLAVE
25 #define CONFIG_83XX_PCICLK      66000000        /* in HZ */
26 #else
27 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
28 #endif
29
30 #ifndef CONFIG_SYS_CLK_FREQ
31 #define CONFIG_SYS_CLK_FREQ     66000000
32 #endif
33
34 /*
35  * Hardware Reset Configuration Word
36  */
37 #define CONFIG_SYS_HRCW_LOW (\
38         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
39         HRCWL_DDR_TO_SCB_CLK_2X1 |\
40         HRCWL_VCO_1X2 |\
41         HRCWL_CSB_TO_CLKIN_2X1 |\
42         HRCWL_CORE_TO_CSB_2X1 |\
43         HRCWL_CE_PLL_VCO_DIV_2 |\
44         HRCWL_CE_PLL_DIV_1X1 |\
45         HRCWL_CE_TO_PLL_1X3)
46
47 #ifdef CONFIG_PCISLAVE
48 #define CONFIG_SYS_HRCW_HIGH (\
49         HRCWH_PCI_AGENT |\
50         HRCWH_PCI1_ARBITER_DISABLE |\
51         HRCWH_CORE_ENABLE |\
52         HRCWH_FROM_0XFFF00100 |\
53         HRCWH_BOOTSEQ_DISABLE |\
54         HRCWH_SW_WATCHDOG_DISABLE |\
55         HRCWH_ROM_LOC_LOCAL_16BIT |\
56         HRCWH_BIG_ENDIAN |\
57         HRCWH_LALE_NORMAL)
58 #else
59 #define CONFIG_SYS_HRCW_HIGH (\
60         HRCWH_PCI_HOST |\
61         HRCWH_PCI1_ARBITER_ENABLE |\
62         HRCWH_CORE_ENABLE |\
63         HRCWH_FROM_0X00000100 |\
64         HRCWH_BOOTSEQ_DISABLE |\
65         HRCWH_SW_WATCHDOG_DISABLE |\
66         HRCWH_ROM_LOC_LOCAL_16BIT |\
67         HRCWH_BIG_ENDIAN |\
68         HRCWH_LALE_NORMAL)
69 #endif
70
71 /*
72  * System IO Config
73  */
74 #define CONFIG_SYS_SICRL                0x00000000
75
76 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_pre_init */
77 #define CONFIG_BOARD_EARLY_INIT_R
78
79 /*
80  * IMMR new address
81  */
82 #define CONFIG_SYS_IMMR         0xE0000000
83
84 /*
85  * DDR Setup
86  */
87 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
88 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
89 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
90 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
91
92 #undef CONFIG_SPD_EEPROM
93 #if defined(CONFIG_SPD_EEPROM)
94 /* Determine DDR configuration from I2C interface
95  */
96 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
97 #else
98 /* Manually set up DDR parameters
99  */
100 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
101 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
102                                         | CSCONFIG_AP \
103                                         | CSCONFIG_ODT_WR_CFG \
104                                         | CSCONFIG_ROW_BIT_13 \
105                                         | CSCONFIG_COL_BIT_10)
106                                         /* 0x80840102 */
107 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
108                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
109                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
110                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
111                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
112                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
113                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
114                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
115                                         /* 0x00220802 */
116 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
117                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
118                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
119                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
120                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
121                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
122                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
123                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
124                                         /* 0x3935D322 */
125 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
126                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
127                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
128                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
129                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
130                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
131                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
132                                 /* 0x0F9048CA */
133 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
134 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
135                                         /* 0x02000000 */
136 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
137                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
138                                         /* 0x44400232 */
139 #define CONFIG_SYS_DDR_MODE2            0x8000c000
140 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
141                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
142                                         /* 0x03200064 */
143 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
144 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
145                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
146                                         | SDRAM_CFG_32_BE)
147                                         /* 0x43080000 */
148 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
149 #endif
150
151 /*
152  * Memory test
153  */
154 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
155 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
156 #define CONFIG_SYS_MEMTEST_END          0x00100000
157
158 /*
159  * The reserved memory
160  */
161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
162
163 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
164 #define CONFIG_SYS_RAMBOOT
165 #else
166 #undef  CONFIG_SYS_RAMBOOT
167 #endif
168
169 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
170 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
171 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
172
173 /*
174  * Initial RAM Base Address Setup
175  */
176 #define CONFIG_SYS_INIT_RAM_LOCK        1
177 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
178 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
179 #define CONFIG_SYS_GBL_DATA_OFFSET      \
180                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
181
182 /*
183  * Local Bus Configuration & Clock Setup
184  */
185 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
186 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
187 #define CONFIG_SYS_LBC_LBCR             0x00000000
188
189 /*
190  * FLASH on the Local Bus
191  */
192 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
193 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
194 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
195 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
196 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
197
198                                         /* Window base at flash base */
199 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
200 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
201
202 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
203                                 | BR_PS_16      /* 16 bit port */ \
204                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
205                                 | BR_V)         /* valid */
206 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
207                                 | OR_GPCM_XAM \
208                                 | OR_GPCM_CSNT \
209                                 | OR_GPCM_ACS_DIV2 \
210                                 | OR_GPCM_XACS \
211                                 | OR_GPCM_SCY_15 \
212                                 | OR_GPCM_TRLX_SET \
213                                 | OR_GPCM_EHTR_SET \
214                                 | OR_GPCM_EAD)
215                                 /* 0xfe006ff7 */
216
217 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
218 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
219
220 #undef CONFIG_SYS_FLASH_CHECKSUM
221
222 /*
223  * BCSR on the Local Bus
224  */
225 #define CONFIG_SYS_BCSR                 0xF8000000
226                                         /* Access window base at BCSR base */
227 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
228 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
229
230 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
231                                         | BR_PS_8 \
232                                         | BR_MS_GPCM \
233                                         | BR_V)
234 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
235                                         | OR_GPCM_XAM \
236                                         | OR_GPCM_CSNT \
237                                         | OR_GPCM_XACS \
238                                         | OR_GPCM_SCY_15 \
239                                         | OR_GPCM_TRLX_SET \
240                                         | OR_GPCM_EHTR_SET \
241                                         | OR_GPCM_EAD)
242                                         /* 0xFFFFE9F7 */
243
244 /*
245  * Windows to access PIB via local bus
246  */
247                                         /* PIB window base 0xF8008000 */
248 #define CONFIG_SYS_PIB_BASE             0xF8008000
249 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
250 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PIB_BASE
251 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
252
253 /*
254  * CS2 on Local Bus, to PIB
255  */
256 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_PIB_BASE \
257                                 | BR_PS_8 \
258                                 | BR_MS_GPCM \
259                                 | BR_V)
260                                 /* 0xF8008801 */
261 #define CONFIG_SYS_OR2_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
262                                 | OR_GPCM_XAM \
263                                 | OR_GPCM_CSNT \
264                                 | OR_GPCM_XACS \
265                                 | OR_GPCM_SCY_15 \
266                                 | OR_GPCM_TRLX_SET \
267                                 | OR_GPCM_EHTR_SET \
268                                 | OR_GPCM_EAD)
269                                 /* 0xffffe9f7 */
270
271 /*
272  * CS3 on Local Bus, to PIB
273  */
274 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIB_BASE + \
275                                         CONFIG_SYS_PIB_WINDOW_SIZE) \
276                                 | BR_PS_8 \
277                                 | BR_MS_GPCM \
278                                 | BR_V)
279                                 /* 0xF8010801 */
280 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
281                                 | OR_GPCM_XAM \
282                                 | OR_GPCM_CSNT \
283                                 | OR_GPCM_XACS \
284                                 | OR_GPCM_SCY_15 \
285                                 | OR_GPCM_TRLX_SET \
286                                 | OR_GPCM_EHTR_SET \
287                                 | OR_GPCM_EAD)
288                                 /* 0xffffe9f7 */
289
290 /*
291  * Serial Port
292  */
293 #define CONFIG_CONS_INDEX       1
294 #define CONFIG_SYS_NS16550
295 #define CONFIG_SYS_NS16550_SERIAL
296 #define CONFIG_SYS_NS16550_REG_SIZE     1
297 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
298
299 #define CONFIG_SYS_BAUDRATE_TABLE  \
300                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
301
302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
304
305 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
306 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
307 /* Use the HUSH parser */
308 #define CONFIG_SYS_HUSH_PARSER
309
310 /* pass open firmware flat tree */
311 #define CONFIG_OF_LIBFDT        1
312 #define CONFIG_OF_BOARD_SETUP   1
313 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
314
315 /* I2C */
316 #define CONFIG_SYS_I2C
317 #define CONFIG_SYS_I2C_FSL
318 #define CONFIG_SYS_FSL_I2C_SPEED        400000
319 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
320 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
321 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
322
323 /*
324  * Config on-board RTC
325  */
326 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
327 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
328
329 /*
330  * General PCI
331  * Addresses are mapped 1-1.
332  */
333 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
334 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
335 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
336 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
337 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
338 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
339 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
340 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
341 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
342
343 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
344 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
345 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
346
347
348 #ifdef CONFIG_PCI
349 #define CONFIG_PCI_INDIRECT_BRIDGE
350
351 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
352 #define CONFIG_83XX_PCI_STREAMING
353
354 #undef CONFIG_EEPRO100
355 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
356 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
357
358 #endif  /* CONFIG_PCI */
359
360 /*
361  * QE UEC ethernet configuration
362  */
363 #define CONFIG_UEC_ETH
364 #define CONFIG_ETHPRIME         "UEC0"
365
366 #define CONFIG_UEC_ETH1         /* ETH3 */
367
368 #ifdef CONFIG_UEC_ETH1
369 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
370 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
371 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
372 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
373 #define CONFIG_SYS_UEC1_PHY_ADDR        3
374 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
375 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
376 #endif
377
378 #define CONFIG_UEC_ETH2         /* ETH4 */
379
380 #ifdef CONFIG_UEC_ETH2
381 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
382 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
383 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
384 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
385 #define CONFIG_SYS_UEC2_PHY_ADDR        4
386 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
387 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
388 #endif
389
390 /*
391  * Environment
392  */
393 #ifndef CONFIG_SYS_RAMBOOT
394         #define CONFIG_ENV_IS_IN_FLASH  1
395         #define CONFIG_ENV_ADDR         \
396                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
397         #define CONFIG_ENV_SECT_SIZE    0x20000
398         #define CONFIG_ENV_SIZE         0x2000
399 #else
400         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
401         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
402         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
403         #define CONFIG_ENV_SIZE         0x2000
404 #endif
405
406 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
407 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
408
409 /*
410  * BOOTP options
411  */
412 #define CONFIG_BOOTP_BOOTFILESIZE
413 #define CONFIG_BOOTP_BOOTPATH
414 #define CONFIG_BOOTP_GATEWAY
415 #define CONFIG_BOOTP_HOSTNAME
416
417
418 /*
419  * Command line configuration.
420  */
421 #include <config_cmd_default.h>
422
423 #define CONFIG_CMD_PING
424 #define CONFIG_CMD_I2C
425 #define CONFIG_CMD_ASKENV
426
427 #if defined(CONFIG_PCI)
428     #define CONFIG_CMD_PCI
429 #endif
430
431 #if defined(CONFIG_SYS_RAMBOOT)
432     #undef CONFIG_CMD_SAVEENV
433     #undef CONFIG_CMD_LOADS
434 #endif
435
436
437 #undef CONFIG_WATCHDOG          /* watchdog disabled */
438
439 /*
440  * Miscellaneous configurable options
441  */
442 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
443 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
444
445 #if defined(CONFIG_CMD_KGDB)
446         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
447 #else
448         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
449 #endif
450
451                                 /* Print Buffer Size */
452 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
453 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
454                                 /* Boot Argument Buffer Size */
455 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
456
457 /*
458  * For booting Linux, the board info and command line data
459  * have to be in the first 256 MB of memory, since this is
460  * the maximum mapped by the Linux kernel during initialization.
461  */
462                                         /* Initial Memory map for Linux */
463 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
464
465 /*
466  * Core HID Setup
467  */
468 #define CONFIG_SYS_HID0_INIT    0x000000000
469 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
470                                  HID0_ENABLE_INSTRUCTION_CACHE)
471 #define CONFIG_SYS_HID2         HID2_HBE
472
473 /*
474  * MMU Setup
475  */
476
477 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
478
479 /* DDR: cache cacheable */
480 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
481                                 | BATL_PP_RW \
482                                 | BATL_MEMCOHERENCE)
483 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
484                                 | BATU_BL_256M \
485                                 | BATU_VS \
486                                 | BATU_VP)
487 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
488 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
489
490 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
491 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
492                                 | BATL_PP_RW \
493                                 | BATL_CACHEINHIBIT \
494                                 | BATL_GUARDEDSTORAGE)
495 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
496                                 | BATU_BL_4M \
497                                 | BATU_VS \
498                                 | BATU_VP)
499 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
500 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
501
502 /* BCSR: cache-inhibit and guarded */
503 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
504                                 | BATL_PP_RW \
505                                 | BATL_CACHEINHIBIT \
506                                 | BATL_GUARDEDSTORAGE)
507 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
508                                 | BATU_BL_128K \
509                                 | BATU_VS \
510                                 | BATU_VP)
511 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
512 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
513
514 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
515 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
516                                 | BATL_PP_RW \
517                                 | BATL_MEMCOHERENCE)
518 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
519                                 | BATU_BL_32M \
520                                 | BATU_VS \
521                                 | BATU_VP)
522 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
523                                 | BATL_PP_RW \
524                                 | BATL_CACHEINHIBIT \
525                                 | BATL_GUARDEDSTORAGE)
526 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
527
528 #define CONFIG_SYS_IBAT4L       (0)
529 #define CONFIG_SYS_IBAT4U       (0)
530 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
531 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
532
533 /* Stack in dcache: cacheable, no memory coherence */
534 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
535 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
536                                 | BATU_BL_128K \
537                                 | BATU_VS \
538                                 | BATU_VP)
539 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
540 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
541
542 #ifdef CONFIG_PCI
543 /* PCI MEM space: cacheable */
544 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
545                                 | BATL_PP_RW \
546                                 | BATL_MEMCOHERENCE)
547 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
548                                 | BATU_BL_256M \
549                                 | BATU_VS \
550                                 | BATU_VP)
551 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
552 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
553 /* PCI MMIO space: cache-inhibit and guarded */
554 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
555                                 | BATL_PP_RW \
556                                 | BATL_CACHEINHIBIT \
557                                 | BATL_GUARDEDSTORAGE)
558 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
559                                 | BATU_BL_256M \
560                                 | BATU_VS \
561                                 | BATU_VP)
562 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
563 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
564 #else
565 #define CONFIG_SYS_IBAT6L       (0)
566 #define CONFIG_SYS_IBAT6U       (0)
567 #define CONFIG_SYS_IBAT7L       (0)
568 #define CONFIG_SYS_IBAT7U       (0)
569 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
570 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
571 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
572 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
573 #endif
574
575 #if defined(CONFIG_CMD_KGDB)
576 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
577 #endif
578
579 /*
580  * Environment Configuration
581  */ #define CONFIG_ENV_OVERWRITE
582
583 #if defined(CONFIG_UEC_ETH)
584 #define CONFIG_HAS_ETH0
585 #define CONFIG_HAS_ETH1
586 #endif
587
588 #define CONFIG_BAUDRATE 115200
589
590 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
591
592 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
593 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
594
595 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
596         "netdev=eth0\0"                                                 \
597         "consoledev=ttyS0\0"                                            \
598         "ramdiskaddr=1000000\0"                                         \
599         "ramdiskfile=ramfs.83xx\0"                                      \
600         "fdtaddr=780000\0"                                              \
601         "fdtfile=mpc832x_mds.dtb\0"                                     \
602         ""
603
604 #define CONFIG_NFSBOOTCOMMAND                                           \
605         "setenv bootargs root=/dev/nfs rw "                             \
606                 "nfsroot=$serverip:$rootpath "                          \
607                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
608                                                         "$netdev:off "  \
609                 "console=$consoledev,$baudrate $othbootargs;"           \
610         "tftp $loadaddr $bootfile;"                                     \
611         "tftp $fdtaddr $fdtfile;"                                       \
612         "bootm $loadaddr - $fdtaddr"
613
614 #define CONFIG_RAMBOOTCOMMAND                                           \
615         "setenv bootargs root=/dev/ram rw "                             \
616                 "console=$consoledev,$baudrate $othbootargs;"           \
617         "tftp $ramdiskaddr $ramdiskfile;"                               \
618         "tftp $loadaddr $bootfile;"                                     \
619         "tftp $fdtaddr $fdtfile;"                                       \
620         "bootm $loadaddr $ramdiskaddr $fdtaddr"
621
622
623 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
624
625 #endif  /* __CONFIG_H */