include/configs/MPC832XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * High Level Configuration Options
  11  */
  12 #define CONFIG_E300             1       /* E300 family */
  13 #define CONFIG_QE               1       /* Has QE */
  14
  15 /*
  16  * System IO Config
  17  */
  18 #define CONFIG_SYS_SICRL                0x00000000
  19
  20 /*
  21  * IMMR new address
  22  */
  23 #define CONFIG_SYS_IMMR         0xE0000000
  24
  25 /*
  26  * DDR Setup
  27  */
  28 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  29 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  30 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  31 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  32
  33 #undef CONFIG_SPD_EEPROM
  34 #if defined(CONFIG_SPD_EEPROM)
  35 /* Determine DDR configuration from I2C interface
  36  */
  37 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  38 #else
  39 /* Manually set up DDR parameters
  40  */
  41 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
  42 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  43                                         | CSCONFIG_AP \
  44                                         | CSCONFIG_ODT_WR_CFG \
  45                                         | CSCONFIG_ROW_BIT_13 \
  46                                         | CSCONFIG_COL_BIT_10)
  47                                         /* 0x80840102 */
  48 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
  49                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
  50                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
  51                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
  52                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  53                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  54                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  55                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  56                                         /* 0x00220802 */
  57 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  58                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  59                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  60                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  61                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
  62                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
  63                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  64                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
  65                                         /* 0x3935D322 */
  66 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  67                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  68                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  69                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  70                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  71                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  72                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
  73                                 /* 0x0F9048CA */
  74 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
  75 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  76                                         /* 0x02000000 */
  77 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  78                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
  79                                         /* 0x44400232 */
  80 #define CONFIG_SYS_DDR_MODE2            0x8000c000
  81 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  82                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  83                                         /* 0x03200064 */
  84 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
  85 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  86                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  87                                         | SDRAM_CFG_32_BE)
  88                                         /* 0x43080000 */
  89 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  90 #endif
  91
  92 /*
  93  * Memory test
  94  */
  95 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  96 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  97 #define CONFIG_SYS_MEMTEST_END          0x00100000
  98
  99 /*
 100  * The reserved memory
 101  */
 102 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 103
 104 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 105 #define CONFIG_SYS_RAMBOOT
 106 #else
 107 #undef  CONFIG_SYS_RAMBOOT
 108 #endif
 109
 110 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 111 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 112 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 113
 114 /*
 115  * Initial RAM Base Address Setup
 116  */
 117 #define CONFIG_SYS_INIT_RAM_LOCK        1
 118 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 119 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 120 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 121                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 122
 123 /*
 124  * Local Bus Configuration & Clock Setup
 125  */
 126 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 127 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 128 #define CONFIG_SYS_LBC_LBCR             0x00000000
 129
 130 /*
 131  * FLASH on the Local Bus
 132  */
 133 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 134 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 135
 136
 137 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 138 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 139
 140 #undef CONFIG_SYS_FLASH_CHECKSUM
 141
 142 /*
 143  * BCSR on the Local Bus
 144  */
 145 #define CONFIG_SYS_BCSR                 0xF8000000
 146                                         /* Access window base at BCSR base */
 147
 148
 149 /*
 150  * Windows to access PIB via local bus
 151  */
 152                                         /* PIB window base 0xF8008000 */
 153 #define CONFIG_SYS_PIB_BASE             0xF8008000
 154 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 155
 156 /*
 157  * CS2 on Local Bus, to PIB
 158  */
 159
 160
 161 /*
 162  * CS3 on Local Bus, to PIB
 163  */
 164
 165
 166 /*
 167  * Serial Port
 168  */
 169 #define CONFIG_SYS_NS16550_SERIAL
 170 #define CONFIG_SYS_NS16550_REG_SIZE     1
 171 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 172
 173 #define CONFIG_SYS_BAUDRATE_TABLE  \
 174                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 175
 176 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 177 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 178
 179 /* I2C */
 180 #define CONFIG_SYS_I2C
 181 #define CONFIG_SYS_I2C_FSL
 182 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 183 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 184 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 185 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 186
 187 /*
 188  * Config on-board RTC
 189  */
 190 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 191 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 192
 193 /*
 194  * General PCI
 195  * Addresses are mapped 1-1.
 196  */
 197 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 198 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 199 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 200 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 201 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 202 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 203 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 204 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 205 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 206
 207 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 208 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 209 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 210
 211 #ifdef CONFIG_PCI
 212 #define CONFIG_PCI_INDIRECT_BRIDGE
 213
 214 #define CONFIG_83XX_PCI_STREAMING
 215
 216 #undef CONFIG_EEPRO100
 217 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 218 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 219
 220 #endif  /* CONFIG_PCI */
 221
 222 /*
 223  * QE UEC ethernet configuration
 224  */
 225 #define CONFIG_UEC_ETH
 226 #define CONFIG_ETHPRIME         "UEC0"
 227
 228 #define CONFIG_UEC_ETH1         /* ETH3 */
 229
 230 #ifdef CONFIG_UEC_ETH1
 231 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 232 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 233 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 234 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 235 #define CONFIG_SYS_UEC1_PHY_ADDR        3
 236 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 237 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 238 #endif
 239
 240 #define CONFIG_UEC_ETH2         /* ETH4 */
 241
 242 #ifdef CONFIG_UEC_ETH2
 243 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 244 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 245 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 246 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 247 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 248 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 249 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 250 #endif
 251
 252 /*
 253  * Environment
 254  */
 255 #ifndef CONFIG_SYS_RAMBOOT
 256         #define CONFIG_ENV_ADDR         \
 257                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 258         #define CONFIG_ENV_SECT_SIZE    0x20000
 259         #define CONFIG_ENV_SIZE         0x2000
 260 #else
 261         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 262         #define CONFIG_ENV_SIZE         0x2000
 263 #endif
 264
 265 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 266 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 267
 268 /*
 269  * BOOTP options
 270  */
 271 #define CONFIG_BOOTP_BOOTFILESIZE
 272
 273 /*
 274  * Command line configuration.
 275  */
 276
 277 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 278
 279 /*
 280  * Miscellaneous configurable options
 281  */
 282 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 283
 284 /*
 285  * For booting Linux, the board info and command line data
 286  * have to be in the first 256 MB of memory, since this is
 287  * the maximum mapped by the Linux kernel during initialization.
 288  */
 289                                         /* Initial Memory map for Linux */
 290 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 291 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 292
 293 #if defined(CONFIG_CMD_KGDB)
 294 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 295 #endif
 296
 297 /*
 298  * Environment Configuration
 299  */ #define CONFIG_ENV_OVERWRITE
 300
 301 #if defined(CONFIG_UEC_ETH)
 302 #define CONFIG_HAS_ETH0
 303 #define CONFIG_HAS_ETH1
 304 #endif
 305
 306 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 307
 308 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 309         "netdev=eth0\0"                                                 \
 310         "consoledev=ttyS0\0"                                            \
 311         "ramdiskaddr=1000000\0"                                         \
 312         "ramdiskfile=ramfs.83xx\0"                                      \
 313         "fdtaddr=780000\0"                                              \
 314         "fdtfile=mpc832x_mds.dtb\0"                                     \
 315         ""
 316
 317 #define CONFIG_NFSBOOTCOMMAND                                           \
 318         "setenv bootargs root=/dev/nfs rw "                             \
 319                 "nfsroot=$serverip:$rootpath "                          \
 320                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 321                                                         "$netdev:off "  \
 322                 "console=$consoledev,$baudrate $othbootargs;"           \
 323         "tftp $loadaddr $bootfile;"                                     \
 324         "tftp $fdtaddr $fdtfile;"                                       \
 325         "bootm $loadaddr - $fdtaddr"
 326
 327 #define CONFIG_RAMBOOTCOMMAND                                           \
 328         "setenv bootargs root=/dev/ram rw "                             \
 329                 "console=$consoledev,$baudrate $othbootargs;"           \
 330         "tftp $ramdiskaddr $ramdiskfile;"                               \
 331         "tftp $loadaddr $bootfile;"                                     \
 332         "tftp $fdtaddr $fdtfile;"                                       \
 333         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 334
 335 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 336
 337 #endif  /* __CONFIG_H */