include/configs/MPC832XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * High Level Configuration Options
  11  */
  12 #define CONFIG_E300             1       /* E300 family */
  13 #define CONFIG_QE               1       /* Has QE */
  14 #define CONFIG_MPC832XEMDS      1       /* MPC832XEMDS board specific */
  15
  16 /*
  17  * System Clock Setup
  18  */
  19 #ifdef CONFIG_PCISLAVE
  20 #define CONFIG_83XX_PCICLK      66000000        /* in HZ */
  21 #else
  22 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  23 #endif
  24
  25 #ifndef CONFIG_SYS_CLK_FREQ
  26 #define CONFIG_SYS_CLK_FREQ     66000000
  27 #endif
  28
  29 /*
  30  * Hardware Reset Configuration Word
  31  */
  32 #define CONFIG_SYS_HRCW_LOW (\
  33         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  34         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  35         HRCWL_VCO_1X2 |\
  36         HRCWL_CSB_TO_CLKIN_2X1 |\
  37         HRCWL_CORE_TO_CSB_2X1 |\
  38         HRCWL_CE_PLL_VCO_DIV_2 |\
  39         HRCWL_CE_PLL_DIV_1X1 |\
  40         HRCWL_CE_TO_PLL_1X3)
  41
  42 #ifdef CONFIG_PCISLAVE
  43 #define CONFIG_SYS_HRCW_HIGH (\
  44         HRCWH_PCI_AGENT |\
  45         HRCWH_PCI1_ARBITER_DISABLE |\
  46         HRCWH_CORE_ENABLE |\
  47         HRCWH_FROM_0XFFF00100 |\
  48         HRCWH_BOOTSEQ_DISABLE |\
  49         HRCWH_SW_WATCHDOG_DISABLE |\
  50         HRCWH_ROM_LOC_LOCAL_16BIT |\
  51         HRCWH_BIG_ENDIAN |\
  52         HRCWH_LALE_NORMAL)
  53 #else
  54 #define CONFIG_SYS_HRCW_HIGH (\
  55         HRCWH_PCI_HOST |\
  56         HRCWH_PCI1_ARBITER_ENABLE |\
  57         HRCWH_CORE_ENABLE |\
  58         HRCWH_FROM_0X00000100 |\
  59         HRCWH_BOOTSEQ_DISABLE |\
  60         HRCWH_SW_WATCHDOG_DISABLE |\
  61         HRCWH_ROM_LOC_LOCAL_16BIT |\
  62         HRCWH_BIG_ENDIAN |\
  63         HRCWH_LALE_NORMAL)
  64 #endif
  65
  66 /*
  67  * System IO Config
  68  */
  69 #define CONFIG_SYS_SICRL                0x00000000
  70
  71 /*
  72  * IMMR new address
  73  */
  74 #define CONFIG_SYS_IMMR         0xE0000000
  75
  76 /*
  77  * DDR Setup
  78  */
  79 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  80 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  81 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  82 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  83
  84 #undef CONFIG_SPD_EEPROM
  85 #if defined(CONFIG_SPD_EEPROM)
  86 /* Determine DDR configuration from I2C interface
  87  */
  88 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  89 #else
  90 /* Manually set up DDR parameters
  91  */
  92 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
  93 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  94                                         | CSCONFIG_AP \
  95                                         | CSCONFIG_ODT_WR_CFG \
  96                                         | CSCONFIG_ROW_BIT_13 \
  97                                         | CSCONFIG_COL_BIT_10)
  98                                         /* 0x80840102 */
  99 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
 100                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
 101                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
 102                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
 103                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 104                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 105                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 106                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 107                                         /* 0x00220802 */
 108 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 109                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 110                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 111                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 112                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
 113                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
 114                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 115                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
 116                                         /* 0x3935D322 */
 117 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 118                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 119                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 120                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 121                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 122                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 123                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
 124                                 /* 0x0F9048CA */
 125 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 126 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 127                                         /* 0x02000000 */
 128 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
 129                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
 130                                         /* 0x44400232 */
 131 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 132 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 133                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 134                                         /* 0x03200064 */
 135 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
 136 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 137                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 138                                         | SDRAM_CFG_32_BE)
 139                                         /* 0x43080000 */
 140 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 141 #endif
 142
 143 /*
 144  * Memory test
 145  */
 146 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 147 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
 148 #define CONFIG_SYS_MEMTEST_END          0x00100000
 149
 150 /*
 151  * The reserved memory
 152  */
 153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 154
 155 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 156 #define CONFIG_SYS_RAMBOOT
 157 #else
 158 #undef  CONFIG_SYS_RAMBOOT
 159 #endif
 160
 161 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 162 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 163 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 164
 165 /*
 166  * Initial RAM Base Address Setup
 167  */
 168 #define CONFIG_SYS_INIT_RAM_LOCK        1
 169 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 170 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 171 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 172                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 173
 174 /*
 175  * Local Bus Configuration & Clock Setup
 176  */
 177 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 178 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 179 #define CONFIG_SYS_LBC_LBCR             0x00000000
 180
 181 /*
 182  * FLASH on the Local Bus
 183  */
 184 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 185 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 186
 187                                         /* Window base at flash base */
 188 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 189 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 190
 191 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 192                                 | BR_PS_16      /* 16 bit port */ \
 193                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 194                                 | BR_V)         /* valid */
 195 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 196                                 | OR_GPCM_XAM \
 197                                 | OR_GPCM_CSNT \
 198                                 | OR_GPCM_ACS_DIV2 \
 199                                 | OR_GPCM_XACS \
 200                                 | OR_GPCM_SCY_15 \
 201                                 | OR_GPCM_TRLX_SET \
 202                                 | OR_GPCM_EHTR_SET \
 203                                 | OR_GPCM_EAD)
 204                                 /* 0xfe006ff7 */
 205
 206 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 207 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 208
 209 #undef CONFIG_SYS_FLASH_CHECKSUM
 210
 211 /*
 212  * BCSR on the Local Bus
 213  */
 214 #define CONFIG_SYS_BCSR                 0xF8000000
 215                                         /* Access window base at BCSR base */
 216 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 217 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 218
 219 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 220                                         | BR_PS_8 \
 221                                         | BR_MS_GPCM \
 222                                         | BR_V)
 223 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 224                                         | OR_GPCM_XAM \
 225                                         | OR_GPCM_CSNT \
 226                                         | OR_GPCM_XACS \
 227                                         | OR_GPCM_SCY_15 \
 228                                         | OR_GPCM_TRLX_SET \
 229                                         | OR_GPCM_EHTR_SET \
 230                                         | OR_GPCM_EAD)
 231                                         /* 0xFFFFE9F7 */
 232
 233 /*
 234  * Windows to access PIB via local bus
 235  */
 236                                         /* PIB window base 0xF8008000 */
 237 #define CONFIG_SYS_PIB_BASE             0xF8008000
 238 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 239 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PIB_BASE
 240 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 241
 242 /*
 243  * CS2 on Local Bus, to PIB
 244  */
 245 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_PIB_BASE \
 246                                 | BR_PS_8 \
 247                                 | BR_MS_GPCM \
 248                                 | BR_V)
 249                                 /* 0xF8008801 */
 250 #define CONFIG_SYS_OR2_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 251                                 | OR_GPCM_XAM \
 252                                 | OR_GPCM_CSNT \
 253                                 | OR_GPCM_XACS \
 254                                 | OR_GPCM_SCY_15 \
 255                                 | OR_GPCM_TRLX_SET \
 256                                 | OR_GPCM_EHTR_SET \
 257                                 | OR_GPCM_EAD)
 258                                 /* 0xffffe9f7 */
 259
 260 /*
 261  * CS3 on Local Bus, to PIB
 262  */
 263 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIB_BASE + \
 264                                         CONFIG_SYS_PIB_WINDOW_SIZE) \
 265                                 | BR_PS_8 \
 266                                 | BR_MS_GPCM \
 267                                 | BR_V)
 268                                 /* 0xF8010801 */
 269 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 270                                 | OR_GPCM_XAM \
 271                                 | OR_GPCM_CSNT \
 272                                 | OR_GPCM_XACS \
 273                                 | OR_GPCM_SCY_15 \
 274                                 | OR_GPCM_TRLX_SET \
 275                                 | OR_GPCM_EHTR_SET \
 276                                 | OR_GPCM_EAD)
 277                                 /* 0xffffe9f7 */
 278
 279 /*
 280  * Serial Port
 281  */
 282 #define CONFIG_SYS_NS16550_SERIAL
 283 #define CONFIG_SYS_NS16550_REG_SIZE     1
 284 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 285
 286 #define CONFIG_SYS_BAUDRATE_TABLE  \
 287                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 288
 289 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 290 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 291
 292 /* I2C */
 293 #define CONFIG_SYS_I2C
 294 #define CONFIG_SYS_I2C_FSL
 295 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 296 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 297 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 298 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 299
 300 /*
 301  * Config on-board RTC
 302  */
 303 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 304 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 305
 306 /*
 307  * General PCI
 308  * Addresses are mapped 1-1.
 309  */
 310 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 311 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 312 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 313 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 314 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 315 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 316 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 317 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 318 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 319
 320 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 321 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 322 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 323
 324 #ifdef CONFIG_PCI
 325 #define CONFIG_PCI_INDIRECT_BRIDGE
 326
 327 #define CONFIG_83XX_PCI_STREAMING
 328
 329 #undef CONFIG_EEPRO100
 330 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 331 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 332
 333 #endif  /* CONFIG_PCI */
 334
 335 /*
 336  * QE UEC ethernet configuration
 337  */
 338 #define CONFIG_UEC_ETH
 339 #define CONFIG_ETHPRIME         "UEC0"
 340
 341 #define CONFIG_UEC_ETH1         /* ETH3 */
 342
 343 #ifdef CONFIG_UEC_ETH1
 344 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 345 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 346 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 347 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 348 #define CONFIG_SYS_UEC1_PHY_ADDR        3
 349 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 350 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 351 #endif
 352
 353 #define CONFIG_UEC_ETH2         /* ETH4 */
 354
 355 #ifdef CONFIG_UEC_ETH2
 356 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 357 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 358 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 359 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 360 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 361 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 362 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 363 #endif
 364
 365 /*
 366  * Environment
 367  */
 368 #ifndef CONFIG_SYS_RAMBOOT
 369         #define CONFIG_ENV_ADDR         \
 370                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 371         #define CONFIG_ENV_SECT_SIZE    0x20000
 372         #define CONFIG_ENV_SIZE         0x2000
 373 #else
 374         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 375         #define CONFIG_ENV_SIZE         0x2000
 376 #endif
 377
 378 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 379 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 380
 381 /*
 382  * BOOTP options
 383  */
 384 #define CONFIG_BOOTP_BOOTFILESIZE
 385
 386 /*
 387  * Command line configuration.
 388  */
 389
 390 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 391
 392 /*
 393  * Miscellaneous configurable options
 394  */
 395 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 396
 397 /*
 398  * For booting Linux, the board info and command line data
 399  * have to be in the first 256 MB of memory, since this is
 400  * the maximum mapped by the Linux kernel during initialization.
 401  */
 402                                         /* Initial Memory map for Linux */
 403 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 404 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 405
 406 /*
 407  * Core HID Setup
 408  */
 409 #define CONFIG_SYS_HID0_INIT    0x000000000
 410 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 411                                  HID0_ENABLE_INSTRUCTION_CACHE)
 412 #define CONFIG_SYS_HID2         HID2_HBE
 413
 414 /*
 415  * MMU Setup
 416  */
 417
 418 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 419
 420 /* DDR: cache cacheable */
 421 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 422                                 | BATL_PP_RW \
 423                                 | BATL_MEMCOHERENCE)
 424 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 425                                 | BATU_BL_256M \
 426                                 | BATU_VS \
 427                                 | BATU_VP)
 428 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 429 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 430
 431 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 432 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 433                                 | BATL_PP_RW \
 434                                 | BATL_CACHEINHIBIT \
 435                                 | BATL_GUARDEDSTORAGE)
 436 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 437                                 | BATU_BL_4M \
 438                                 | BATU_VS \
 439                                 | BATU_VP)
 440 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 441 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 442
 443 /* BCSR: cache-inhibit and guarded */
 444 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 445                                 | BATL_PP_RW \
 446                                 | BATL_CACHEINHIBIT \
 447                                 | BATL_GUARDEDSTORAGE)
 448 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 449                                 | BATU_BL_128K \
 450                                 | BATU_VS \
 451                                 | BATU_VP)
 452 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 453 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 454
 455 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 456 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 457                                 | BATL_PP_RW \
 458                                 | BATL_MEMCOHERENCE)
 459 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 460                                 | BATU_BL_32M \
 461                                 | BATU_VS \
 462                                 | BATU_VP)
 463 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 464                                 | BATL_PP_RW \
 465                                 | BATL_CACHEINHIBIT \
 466                                 | BATL_GUARDEDSTORAGE)
 467 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 468
 469 #define CONFIG_SYS_IBAT4L       (0)
 470 #define CONFIG_SYS_IBAT4U       (0)
 471 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 472 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 473
 474 /* Stack in dcache: cacheable, no memory coherence */
 475 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 476 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 477                                 | BATU_BL_128K \
 478                                 | BATU_VS \
 479                                 | BATU_VP)
 480 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 481 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 482
 483 #ifdef CONFIG_PCI
 484 /* PCI MEM space: cacheable */
 485 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 486                                 | BATL_PP_RW \
 487                                 | BATL_MEMCOHERENCE)
 488 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 489                                 | BATU_BL_256M \
 490                                 | BATU_VS \
 491                                 | BATU_VP)
 492 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 493 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 494 /* PCI MMIO space: cache-inhibit and guarded */
 495 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 496                                 | BATL_PP_RW \
 497                                 | BATL_CACHEINHIBIT \
 498                                 | BATL_GUARDEDSTORAGE)
 499 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 500                                 | BATU_BL_256M \
 501                                 | BATU_VS \
 502                                 | BATU_VP)
 503 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 504 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 505 #else
 506 #define CONFIG_SYS_IBAT6L       (0)
 507 #define CONFIG_SYS_IBAT6U       (0)
 508 #define CONFIG_SYS_IBAT7L       (0)
 509 #define CONFIG_SYS_IBAT7U       (0)
 510 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 511 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 512 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 513 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 514 #endif
 515
 516 #if defined(CONFIG_CMD_KGDB)
 517 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 518 #endif
 519
 520 /*
 521  * Environment Configuration
 522  */ #define CONFIG_ENV_OVERWRITE
 523
 524 #if defined(CONFIG_UEC_ETH)
 525 #define CONFIG_HAS_ETH0
 526 #define CONFIG_HAS_ETH1
 527 #endif
 528
 529 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 530
 531 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 532         "netdev=eth0\0"                                                 \
 533         "consoledev=ttyS0\0"                                            \
 534         "ramdiskaddr=1000000\0"                                         \
 535         "ramdiskfile=ramfs.83xx\0"                                      \
 536         "fdtaddr=780000\0"                                              \
 537         "fdtfile=mpc832x_mds.dtb\0"                                     \
 538         ""
 539
 540 #define CONFIG_NFSBOOTCOMMAND                                           \
 541         "setenv bootargs root=/dev/nfs rw "                             \
 542                 "nfsroot=$serverip:$rootpath "                          \
 543                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 544                                                         "$netdev:off "  \
 545                 "console=$consoledev,$baudrate $othbootargs;"           \
 546         "tftp $loadaddr $bootfile;"                                     \
 547         "tftp $fdtaddr $fdtfile;"                                       \
 548         "bootm $loadaddr - $fdtaddr"
 549
 550 #define CONFIG_RAMBOOTCOMMAND                                           \
 551         "setenv bootargs root=/dev/ram rw "                             \
 552                 "console=$consoledev,$baudrate $othbootargs;"           \
 553         "tftp $ramdiskaddr $ramdiskfile;"                               \
 554         "tftp $loadaddr $bootfile;"                                     \
 555         "tftp $fdtaddr $fdtfile;"                                       \
 556         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 557
 558 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 559
 560 #endif  /* __CONFIG_H */