1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
10 * High Level Configuration Options
12 #define CONFIG_E300 1 /* E300 family */
13 #define CONFIG_QE 1 /* Has QE */
18 #define CONFIG_SYS_SICRL 0x00000000
23 #define CONFIG_SYS_IMMR 0xE0000000
28 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
29 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
30 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
31 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
33 #undef CONFIG_SPD_EEPROM
34 #if defined(CONFIG_SPD_EEPROM)
35 /* Determine DDR configuration from I2C interface
37 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
39 /* Manually set up DDR parameters
41 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
42 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
44 | CSCONFIG_ODT_WR_CFG \
45 | CSCONFIG_ROW_BIT_13 \
46 | CSCONFIG_COL_BIT_10)
48 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
49 | (0 << TIMING_CFG0_WRT_SHIFT) \
50 | (0 << TIMING_CFG0_RRT_SHIFT) \
51 | (0 << TIMING_CFG0_WWT_SHIFT) \
52 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
53 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
54 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
55 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
57 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
58 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
59 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
60 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
61 | (13 << TIMING_CFG1_REFREC_SHIFT) \
62 | (3 << TIMING_CFG1_WRREC_SHIFT) \
63 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
64 | (2 << TIMING_CFG1_WRTORD_SHIFT))
66 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
67 | (31 << TIMING_CFG2_CPO_SHIFT) \
68 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
69 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
70 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
71 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
72 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
74 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
75 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
77 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
78 | (0x0232 << SDRAM_MODE_SD_SHIFT))
80 #define CONFIG_SYS_DDR_MODE2 0x8000c000
81 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
82 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
84 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
85 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
86 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
89 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
95 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
96 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
97 #define CONFIG_SYS_MEMTEST_END 0x00100000
100 * The reserved memory
102 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
104 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
105 #define CONFIG_SYS_RAMBOOT
107 #undef CONFIG_SYS_RAMBOOT
110 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
111 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
112 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
115 * Initial RAM Base Address Setup
117 #define CONFIG_SYS_INIT_RAM_LOCK 1
118 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
119 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
120 #define CONFIG_SYS_GBL_DATA_OFFSET \
121 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
124 * Local Bus Configuration & Clock Setup
126 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
127 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
128 #define CONFIG_SYS_LBC_LBCR 0x00000000
131 * FLASH on the Local Bus
133 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
134 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
137 #define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
138 #define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
140 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
141 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
143 #undef CONFIG_SYS_FLASH_CHECKSUM
146 * BCSR on the Local Bus
148 #define CONFIG_SYS_BCSR 0xF8000000
149 /* Access window base at BCSR base */
152 #define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
153 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
156 * Windows to access PIB via local bus
158 /* PIB window base 0xF8008000 */
159 #define CONFIG_SYS_PIB_BASE 0xF8008000
160 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
163 * CS2 on Local Bus, to PIB
167 #define CONFIG_SYS_BR2_PRELIM (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V)
168 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
171 * CS3 on Local Bus, to PIB
175 #define CONFIG_SYS_BR3_PRELIM (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V)
176 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
181 #define CONFIG_SYS_NS16550_SERIAL
182 #define CONFIG_SYS_NS16550_REG_SIZE 1
183 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
185 #define CONFIG_SYS_BAUDRATE_TABLE \
186 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
188 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
189 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
192 #define CONFIG_SYS_I2C
193 #define CONFIG_SYS_I2C_FSL
194 #define CONFIG_SYS_FSL_I2C_SPEED 400000
195 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
196 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
197 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
200 * Config on-board RTC
202 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
203 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
207 * Addresses are mapped 1-1.
209 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
210 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
211 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
212 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
213 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
214 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
215 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
216 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
217 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
219 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
220 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
221 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
224 #define CONFIG_PCI_INDIRECT_BRIDGE
226 #define CONFIG_83XX_PCI_STREAMING
228 #undef CONFIG_EEPRO100
229 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
230 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
232 #endif /* CONFIG_PCI */
235 * QE UEC ethernet configuration
237 #define CONFIG_UEC_ETH
238 #define CONFIG_ETHPRIME "UEC0"
240 #define CONFIG_UEC_ETH1 /* ETH3 */
242 #ifdef CONFIG_UEC_ETH1
243 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
244 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
245 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
246 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
247 #define CONFIG_SYS_UEC1_PHY_ADDR 3
248 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
249 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
252 #define CONFIG_UEC_ETH2 /* ETH4 */
254 #ifdef CONFIG_UEC_ETH2
255 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
256 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
257 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
258 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
259 #define CONFIG_SYS_UEC2_PHY_ADDR 4
260 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
261 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
267 #ifndef CONFIG_SYS_RAMBOOT
268 #define CONFIG_ENV_ADDR \
269 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
270 #define CONFIG_ENV_SECT_SIZE 0x20000
271 #define CONFIG_ENV_SIZE 0x2000
273 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
274 #define CONFIG_ENV_SIZE 0x2000
277 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
278 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
283 #define CONFIG_BOOTP_BOOTFILESIZE
286 * Command line configuration.
289 #undef CONFIG_WATCHDOG /* watchdog disabled */
292 * Miscellaneous configurable options
294 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
297 * For booting Linux, the board info and command line data
298 * have to be in the first 256 MB of memory, since this is
299 * the maximum mapped by the Linux kernel during initialization.
301 /* Initial Memory map for Linux */
302 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
303 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
308 #define CONFIG_SYS_HID0_INIT 0x000000000
309 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
310 HID0_ENABLE_INSTRUCTION_CACHE)
311 #define CONFIG_SYS_HID2 HID2_HBE
313 #if defined(CONFIG_CMD_KGDB)
314 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
318 * Environment Configuration
319 */ #define CONFIG_ENV_OVERWRITE
321 #if defined(CONFIG_UEC_ETH)
322 #define CONFIG_HAS_ETH0
323 #define CONFIG_HAS_ETH1
326 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
328 #define CONFIG_EXTRA_ENV_SETTINGS \
330 "consoledev=ttyS0\0" \
331 "ramdiskaddr=1000000\0" \
332 "ramdiskfile=ramfs.83xx\0" \
334 "fdtfile=mpc832x_mds.dtb\0" \
337 #define CONFIG_NFSBOOTCOMMAND \
338 "setenv bootargs root=/dev/nfs rw " \
339 "nfsroot=$serverip:$rootpath " \
340 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
342 "console=$consoledev,$baudrate $othbootargs;" \
343 "tftp $loadaddr $bootfile;" \
344 "tftp $fdtaddr $fdtfile;" \
345 "bootm $loadaddr - $fdtaddr"
347 #define CONFIG_RAMBOOTCOMMAND \
348 "setenv bootargs root=/dev/ram rw " \
349 "console=$consoledev,$baudrate $othbootargs;" \
350 "tftp $ramdiskaddr $ramdiskfile;" \
351 "tftp $loadaddr $bootfile;" \
352 "tftp $fdtaddr $fdtfile;" \
353 "bootm $loadaddr $ramdiskaddr $fdtaddr"
355 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
357 #endif /* __CONFIG_H */