1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
10 * High Level Configuration Options
12 #define CONFIG_E300 1 /* E300 family */
13 #define CONFIG_QE 1 /* Has QE */
18 #define CONFIG_SYS_SICRL 0x00000000
23 #define CONFIG_SYS_IMMR 0xE0000000
28 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
29 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
30 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
31 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
33 #undef CONFIG_SPD_EEPROM
34 #if defined(CONFIG_SPD_EEPROM)
35 /* Determine DDR configuration from I2C interface
37 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
39 /* Manually set up DDR parameters
41 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
42 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
44 | CSCONFIG_ODT_WR_CFG \
45 | CSCONFIG_ROW_BIT_13 \
46 | CSCONFIG_COL_BIT_10)
48 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
49 | (0 << TIMING_CFG0_WRT_SHIFT) \
50 | (0 << TIMING_CFG0_RRT_SHIFT) \
51 | (0 << TIMING_CFG0_WWT_SHIFT) \
52 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
53 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
54 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
55 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
57 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
58 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
59 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
60 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
61 | (13 << TIMING_CFG1_REFREC_SHIFT) \
62 | (3 << TIMING_CFG1_WRREC_SHIFT) \
63 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
64 | (2 << TIMING_CFG1_WRTORD_SHIFT))
66 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
67 | (31 << TIMING_CFG2_CPO_SHIFT) \
68 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
69 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
70 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
71 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
72 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
74 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
75 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
77 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
78 | (0x0232 << SDRAM_MODE_SD_SHIFT))
80 #define CONFIG_SYS_DDR_MODE2 0x8000c000
81 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
82 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
84 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
85 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
86 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
89 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
95 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
96 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
97 #define CONFIG_SYS_MEMTEST_END 0x00100000
100 * The reserved memory
102 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
104 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
105 #define CONFIG_SYS_RAMBOOT
107 #undef CONFIG_SYS_RAMBOOT
110 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
111 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
112 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
115 * Initial RAM Base Address Setup
117 #define CONFIG_SYS_INIT_RAM_LOCK 1
118 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
119 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
120 #define CONFIG_SYS_GBL_DATA_OFFSET \
121 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
124 * Local Bus Configuration & Clock Setup
126 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
127 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
128 #define CONFIG_SYS_LBC_LBCR 0x00000000
131 * FLASH on the Local Bus
133 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
134 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
136 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
137 | BR_PS_16 /* 16 bit port */ \
138 | BR_MS_GPCM /* MSEL = GPCM */ \
140 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
151 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
152 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
154 #undef CONFIG_SYS_FLASH_CHECKSUM
157 * BCSR on the Local Bus
159 #define CONFIG_SYS_BCSR 0xF8000000
160 /* Access window base at BCSR base */
162 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
166 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
177 * Windows to access PIB via local bus
179 /* PIB window base 0xF8008000 */
180 #define CONFIG_SYS_PIB_BASE 0xF8008000
181 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
184 * CS2 on Local Bus, to PIB
186 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
191 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
202 * CS3 on Local Bus, to PIB
204 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
205 CONFIG_SYS_PIB_WINDOW_SIZE) \
210 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
223 #define CONFIG_SYS_NS16550_SERIAL
224 #define CONFIG_SYS_NS16550_REG_SIZE 1
225 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
227 #define CONFIG_SYS_BAUDRATE_TABLE \
228 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
230 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
231 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
234 #define CONFIG_SYS_I2C
235 #define CONFIG_SYS_I2C_FSL
236 #define CONFIG_SYS_FSL_I2C_SPEED 400000
237 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
238 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
239 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
242 * Config on-board RTC
244 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
245 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
249 * Addresses are mapped 1-1.
251 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
252 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
253 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
254 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
255 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
256 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
257 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
258 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
259 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
261 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
262 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
263 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
266 #define CONFIG_PCI_INDIRECT_BRIDGE
268 #define CONFIG_83XX_PCI_STREAMING
270 #undef CONFIG_EEPRO100
271 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
272 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
274 #endif /* CONFIG_PCI */
277 * QE UEC ethernet configuration
279 #define CONFIG_UEC_ETH
280 #define CONFIG_ETHPRIME "UEC0"
282 #define CONFIG_UEC_ETH1 /* ETH3 */
284 #ifdef CONFIG_UEC_ETH1
285 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
286 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
287 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
288 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
289 #define CONFIG_SYS_UEC1_PHY_ADDR 3
290 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
291 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
294 #define CONFIG_UEC_ETH2 /* ETH4 */
296 #ifdef CONFIG_UEC_ETH2
297 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
298 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
299 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
300 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
301 #define CONFIG_SYS_UEC2_PHY_ADDR 4
302 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
303 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
309 #ifndef CONFIG_SYS_RAMBOOT
310 #define CONFIG_ENV_ADDR \
311 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
312 #define CONFIG_ENV_SECT_SIZE 0x20000
313 #define CONFIG_ENV_SIZE 0x2000
315 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
316 #define CONFIG_ENV_SIZE 0x2000
319 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
320 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
325 #define CONFIG_BOOTP_BOOTFILESIZE
328 * Command line configuration.
331 #undef CONFIG_WATCHDOG /* watchdog disabled */
334 * Miscellaneous configurable options
336 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
339 * For booting Linux, the board info and command line data
340 * have to be in the first 256 MB of memory, since this is
341 * the maximum mapped by the Linux kernel during initialization.
343 /* Initial Memory map for Linux */
344 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
345 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
350 #define CONFIG_SYS_HID0_INIT 0x000000000
351 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
352 HID0_ENABLE_INSTRUCTION_CACHE)
353 #define CONFIG_SYS_HID2 HID2_HBE
355 #if defined(CONFIG_CMD_KGDB)
356 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
360 * Environment Configuration
361 */ #define CONFIG_ENV_OVERWRITE
363 #if defined(CONFIG_UEC_ETH)
364 #define CONFIG_HAS_ETH0
365 #define CONFIG_HAS_ETH1
368 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
370 #define CONFIG_EXTRA_ENV_SETTINGS \
372 "consoledev=ttyS0\0" \
373 "ramdiskaddr=1000000\0" \
374 "ramdiskfile=ramfs.83xx\0" \
376 "fdtfile=mpc832x_mds.dtb\0" \
379 #define CONFIG_NFSBOOTCOMMAND \
380 "setenv bootargs root=/dev/nfs rw " \
381 "nfsroot=$serverip:$rootpath " \
382 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
384 "console=$consoledev,$baudrate $othbootargs;" \
385 "tftp $loadaddr $bootfile;" \
386 "tftp $fdtaddr $fdtfile;" \
387 "bootm $loadaddr - $fdtaddr"
389 #define CONFIG_RAMBOOTCOMMAND \
390 "setenv bootargs root=/dev/ram rw " \
391 "console=$consoledev,$baudrate $othbootargs;" \
392 "tftp $ramdiskaddr $ramdiskfile;" \
393 "tftp $loadaddr $bootfile;" \
394 "tftp $fdtaddr $fdtfile;" \
395 "bootm $loadaddr $ramdiskaddr $fdtaddr"
397 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
399 #endif /* __CONFIG_H */