include/configs/MPC832XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * High Level Configuration Options
  11  */
  12 #define CONFIG_E300             1       /* E300 family */
  13 #define CONFIG_QE               1       /* Has QE */
  14
  15 /*
  16  * System IO Config
  17  */
  18 #define CONFIG_SYS_SICRL                0x00000000
  19
  20 /*
  21  * IMMR new address
  22  */
  23 #define CONFIG_SYS_IMMR         0xE0000000
  24
  25 /*
  26  * DDR Setup
  27  */
  28 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  29 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  30 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  31 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  32
  33 #undef CONFIG_SPD_EEPROM
  34 #if defined(CONFIG_SPD_EEPROM)
  35 /* Determine DDR configuration from I2C interface
  36  */
  37 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  38 #else
  39 /* Manually set up DDR parameters
  40  */
  41 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
  42 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  43                                         | CSCONFIG_AP \
  44                                         | CSCONFIG_ODT_WR_CFG \
  45                                         | CSCONFIG_ROW_BIT_13 \
  46                                         | CSCONFIG_COL_BIT_10)
  47                                         /* 0x80840102 */
  48 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
  49                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
  50                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
  51                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
  52                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  53                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  54                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  55                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  56                                         /* 0x00220802 */
  57 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  58                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  59                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  60                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  61                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
  62                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
  63                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  64                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
  65                                         /* 0x3935D322 */
  66 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  67                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  68                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  69                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  70                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  71                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  72                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
  73                                 /* 0x0F9048CA */
  74 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
  75 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  76                                         /* 0x02000000 */
  77 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  78                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
  79                                         /* 0x44400232 */
  80 #define CONFIG_SYS_DDR_MODE2            0x8000c000
  81 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  82                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  83                                         /* 0x03200064 */
  84 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
  85 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  86                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  87                                         | SDRAM_CFG_32_BE)
  88                                         /* 0x43080000 */
  89 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  90 #endif
  91
  92 /*
  93  * Memory test
  94  */
  95 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  96 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  97 #define CONFIG_SYS_MEMTEST_END          0x00100000
  98
  99 /*
 100  * The reserved memory
 101  */
 102 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 103
 104 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 105 #define CONFIG_SYS_RAMBOOT
 106 #else
 107 #undef  CONFIG_SYS_RAMBOOT
 108 #endif
 109
 110 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 111 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 112 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 113
 114 /*
 115  * Initial RAM Base Address Setup
 116  */
 117 #define CONFIG_SYS_INIT_RAM_LOCK        1
 118 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 119 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 120 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 121                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 122
 123 /*
 124  * Local Bus Configuration & Clock Setup
 125  */
 126 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 127 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 128 #define CONFIG_SYS_LBC_LBCR             0x00000000
 129
 130 /*
 131  * FLASH on the Local Bus
 132  */
 133 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 134 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 135
 136                                         /* Window base at flash base */
 137 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 138 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 139
 140 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 141                                 | BR_PS_16      /* 16 bit port */ \
 142                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 143                                 | BR_V)         /* valid */
 144 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 145                                 | OR_GPCM_XAM \
 146                                 | OR_GPCM_CSNT \
 147                                 | OR_GPCM_ACS_DIV2 \
 148                                 | OR_GPCM_XACS \
 149                                 | OR_GPCM_SCY_15 \
 150                                 | OR_GPCM_TRLX_SET \
 151                                 | OR_GPCM_EHTR_SET \
 152                                 | OR_GPCM_EAD)
 153                                 /* 0xfe006ff7 */
 154
 155 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 156 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 157
 158 #undef CONFIG_SYS_FLASH_CHECKSUM
 159
 160 /*
 161  * BCSR on the Local Bus
 162  */
 163 #define CONFIG_SYS_BCSR                 0xF8000000
 164                                         /* Access window base at BCSR base */
 165 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 166 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 167
 168 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 169                                         | BR_PS_8 \
 170                                         | BR_MS_GPCM \
 171                                         | BR_V)
 172 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 173                                         | OR_GPCM_XAM \
 174                                         | OR_GPCM_CSNT \
 175                                         | OR_GPCM_XACS \
 176                                         | OR_GPCM_SCY_15 \
 177                                         | OR_GPCM_TRLX_SET \
 178                                         | OR_GPCM_EHTR_SET \
 179                                         | OR_GPCM_EAD)
 180                                         /* 0xFFFFE9F7 */
 181
 182 /*
 183  * Windows to access PIB via local bus
 184  */
 185                                         /* PIB window base 0xF8008000 */
 186 #define CONFIG_SYS_PIB_BASE             0xF8008000
 187 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 188 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PIB_BASE
 189 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 190
 191 /*
 192  * CS2 on Local Bus, to PIB
 193  */
 194 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_PIB_BASE \
 195                                 | BR_PS_8 \
 196                                 | BR_MS_GPCM \
 197                                 | BR_V)
 198                                 /* 0xF8008801 */
 199 #define CONFIG_SYS_OR2_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 200                                 | OR_GPCM_XAM \
 201                                 | OR_GPCM_CSNT \
 202                                 | OR_GPCM_XACS \
 203                                 | OR_GPCM_SCY_15 \
 204                                 | OR_GPCM_TRLX_SET \
 205                                 | OR_GPCM_EHTR_SET \
 206                                 | OR_GPCM_EAD)
 207                                 /* 0xffffe9f7 */
 208
 209 /*
 210  * CS3 on Local Bus, to PIB
 211  */
 212 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIB_BASE + \
 213                                         CONFIG_SYS_PIB_WINDOW_SIZE) \
 214                                 | BR_PS_8 \
 215                                 | BR_MS_GPCM \
 216                                 | BR_V)
 217                                 /* 0xF8010801 */
 218 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 219                                 | OR_GPCM_XAM \
 220                                 | OR_GPCM_CSNT \
 221                                 | OR_GPCM_XACS \
 222                                 | OR_GPCM_SCY_15 \
 223                                 | OR_GPCM_TRLX_SET \
 224                                 | OR_GPCM_EHTR_SET \
 225                                 | OR_GPCM_EAD)
 226                                 /* 0xffffe9f7 */
 227
 228 /*
 229  * Serial Port
 230  */
 231 #define CONFIG_SYS_NS16550_SERIAL
 232 #define CONFIG_SYS_NS16550_REG_SIZE     1
 233 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 234
 235 #define CONFIG_SYS_BAUDRATE_TABLE  \
 236                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 237
 238 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 239 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 240
 241 /* I2C */
 242 #define CONFIG_SYS_I2C
 243 #define CONFIG_SYS_I2C_FSL
 244 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 245 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 246 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 247 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 248
 249 /*
 250  * Config on-board RTC
 251  */
 252 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 253 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 254
 255 /*
 256  * General PCI
 257  * Addresses are mapped 1-1.
 258  */
 259 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 260 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 261 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 262 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 263 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 264 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 265 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 266 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 267 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 268
 269 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 270 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 271 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 272
 273 #ifdef CONFIG_PCI
 274 #define CONFIG_PCI_INDIRECT_BRIDGE
 275
 276 #define CONFIG_83XX_PCI_STREAMING
 277
 278 #undef CONFIG_EEPRO100
 279 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 280 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 281
 282 #endif  /* CONFIG_PCI */
 283
 284 /*
 285  * QE UEC ethernet configuration
 286  */
 287 #define CONFIG_UEC_ETH
 288 #define CONFIG_ETHPRIME         "UEC0"
 289
 290 #define CONFIG_UEC_ETH1         /* ETH3 */
 291
 292 #ifdef CONFIG_UEC_ETH1
 293 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 294 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 295 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 296 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 297 #define CONFIG_SYS_UEC1_PHY_ADDR        3
 298 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 299 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 300 #endif
 301
 302 #define CONFIG_UEC_ETH2         /* ETH4 */
 303
 304 #ifdef CONFIG_UEC_ETH2
 305 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 306 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 307 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 308 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 309 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 310 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 311 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 312 #endif
 313
 314 /*
 315  * Environment
 316  */
 317 #ifndef CONFIG_SYS_RAMBOOT
 318         #define CONFIG_ENV_ADDR         \
 319                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 320         #define CONFIG_ENV_SECT_SIZE    0x20000
 321         #define CONFIG_ENV_SIZE         0x2000
 322 #else
 323         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 324         #define CONFIG_ENV_SIZE         0x2000
 325 #endif
 326
 327 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 328 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 329
 330 /*
 331  * BOOTP options
 332  */
 333 #define CONFIG_BOOTP_BOOTFILESIZE
 334
 335 /*
 336  * Command line configuration.
 337  */
 338
 339 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 340
 341 /*
 342  * Miscellaneous configurable options
 343  */
 344 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 345
 346 /*
 347  * For booting Linux, the board info and command line data
 348  * have to be in the first 256 MB of memory, since this is
 349  * the maximum mapped by the Linux kernel during initialization.
 350  */
 351                                         /* Initial Memory map for Linux */
 352 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 353 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 354
 355 /*
 356  * Core HID Setup
 357  */
 358 #define CONFIG_SYS_HID0_INIT    0x000000000
 359 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 360                                  HID0_ENABLE_INSTRUCTION_CACHE)
 361 #define CONFIG_SYS_HID2         HID2_HBE
 362
 363 /*
 364  * MMU Setup
 365  */
 366
 367 /* DDR: cache cacheable */
 368 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 369                                 | BATL_PP_RW \
 370                                 | BATL_MEMCOHERENCE)
 371 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 372                                 | BATU_BL_256M \
 373                                 | BATU_VS \
 374                                 | BATU_VP)
 375 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 376 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 377
 378 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 379 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 380                                 | BATL_PP_RW \
 381                                 | BATL_CACHEINHIBIT \
 382                                 | BATL_GUARDEDSTORAGE)
 383 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 384                                 | BATU_BL_4M \
 385                                 | BATU_VS \
 386                                 | BATU_VP)
 387 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 388 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 389
 390 /* BCSR: cache-inhibit and guarded */
 391 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 392                                 | BATL_PP_RW \
 393                                 | BATL_CACHEINHIBIT \
 394                                 | BATL_GUARDEDSTORAGE)
 395 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 396                                 | BATU_BL_128K \
 397                                 | BATU_VS \
 398                                 | BATU_VP)
 399 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 400 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 401
 402 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 403 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 404                                 | BATL_PP_RW \
 405                                 | BATL_MEMCOHERENCE)
 406 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 407                                 | BATU_BL_32M \
 408                                 | BATU_VS \
 409                                 | BATU_VP)
 410 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 411                                 | BATL_PP_RW \
 412                                 | BATL_CACHEINHIBIT \
 413                                 | BATL_GUARDEDSTORAGE)
 414 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 415
 416 #define CONFIG_SYS_IBAT4L       (0)
 417 #define CONFIG_SYS_IBAT4U       (0)
 418 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 419 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 420
 421 /* Stack in dcache: cacheable, no memory coherence */
 422 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 423 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 424                                 | BATU_BL_128K \
 425                                 | BATU_VS \
 426                                 | BATU_VP)
 427 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 428 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 429
 430 #ifdef CONFIG_PCI
 431 /* PCI MEM space: cacheable */
 432 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 433                                 | BATL_PP_RW \
 434                                 | BATL_MEMCOHERENCE)
 435 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 436                                 | BATU_BL_256M \
 437                                 | BATU_VS \
 438                                 | BATU_VP)
 439 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 440 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 441 /* PCI MMIO space: cache-inhibit and guarded */
 442 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 443                                 | BATL_PP_RW \
 444                                 | BATL_CACHEINHIBIT \
 445                                 | BATL_GUARDEDSTORAGE)
 446 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 447                                 | BATU_BL_256M \
 448                                 | BATU_VS \
 449                                 | BATU_VP)
 450 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 451 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 452 #else
 453 #define CONFIG_SYS_IBAT6L       (0)
 454 #define CONFIG_SYS_IBAT6U       (0)
 455 #define CONFIG_SYS_IBAT7L       (0)
 456 #define CONFIG_SYS_IBAT7U       (0)
 457 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 458 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 459 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 460 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 461 #endif
 462
 463 #if defined(CONFIG_CMD_KGDB)
 464 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 465 #endif
 466
 467 /*
 468  * Environment Configuration
 469  */ #define CONFIG_ENV_OVERWRITE
 470
 471 #if defined(CONFIG_UEC_ETH)
 472 #define CONFIG_HAS_ETH0
 473 #define CONFIG_HAS_ETH1
 474 #endif
 475
 476 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 477
 478 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 479         "netdev=eth0\0"                                                 \
 480         "consoledev=ttyS0\0"                                            \
 481         "ramdiskaddr=1000000\0"                                         \
 482         "ramdiskfile=ramfs.83xx\0"                                      \
 483         "fdtaddr=780000\0"                                              \
 484         "fdtfile=mpc832x_mds.dtb\0"                                     \
 485         ""
 486
 487 #define CONFIG_NFSBOOTCOMMAND                                           \
 488         "setenv bootargs root=/dev/nfs rw "                             \
 489                 "nfsroot=$serverip:$rootpath "                          \
 490                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 491                                                         "$netdev:off "  \
 492                 "console=$consoledev,$baudrate $othbootargs;"           \
 493         "tftp $loadaddr $bootfile;"                                     \
 494         "tftp $fdtaddr $fdtfile;"                                       \
 495         "bootm $loadaddr - $fdtaddr"
 496
 497 #define CONFIG_RAMBOOTCOMMAND                                           \
 498         "setenv bootargs root=/dev/ram rw "                             \
 499                 "console=$consoledev,$baudrate $othbootargs;"           \
 500         "tftp $ramdiskaddr $ramdiskfile;"                               \
 501         "tftp $loadaddr $bootfile;"                                     \
 502         "tftp $fdtaddr $fdtfile;"                                       \
 503         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 504
 505 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 506
 507 #endif  /* __CONFIG_H */