include/configs/MPC832XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * High Level Configuration Options
  11  */
  12 #define CONFIG_E300             1       /* E300 family */
  13 #define CONFIG_QE               1       /* Has QE */
  14
  15 /*
  16  * System Clock Setup
  17  */
  18 #ifdef CONFIG_PCISLAVE
  19 #define CONFIG_83XX_PCICLK      66000000        /* in HZ */
  20 #else
  21 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  22 #endif
  23
  24 #ifndef CONFIG_SYS_CLK_FREQ
  25 #define CONFIG_SYS_CLK_FREQ     66000000
  26 #endif
  27
  28 /*
  29  * Hardware Reset Configuration Word
  30  */
  31 #define CONFIG_SYS_HRCW_LOW (\
  32         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  33         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  34         HRCWL_VCO_1X2 |\
  35         HRCWL_CSB_TO_CLKIN_2X1 |\
  36         HRCWL_CORE_TO_CSB_2X1 |\
  37         HRCWL_CE_PLL_VCO_DIV_2 |\
  38         HRCWL_CE_PLL_DIV_1X1 |\
  39         HRCWL_CE_TO_PLL_1X3)
  40
  41 #ifdef CONFIG_PCISLAVE
  42 #define CONFIG_SYS_HRCW_HIGH (\
  43         HRCWH_PCI_AGENT |\
  44         HRCWH_PCI1_ARBITER_DISABLE |\
  45         HRCWH_CORE_ENABLE |\
  46         HRCWH_FROM_0XFFF00100 |\
  47         HRCWH_BOOTSEQ_DISABLE |\
  48         HRCWH_SW_WATCHDOG_DISABLE |\
  49         HRCWH_ROM_LOC_LOCAL_16BIT |\
  50         HRCWH_BIG_ENDIAN |\
  51         HRCWH_LALE_NORMAL)
  52 #else
  53 #define CONFIG_SYS_HRCW_HIGH (\
  54         HRCWH_PCI_HOST |\
  55         HRCWH_PCI1_ARBITER_ENABLE |\
  56         HRCWH_CORE_ENABLE |\
  57         HRCWH_FROM_0X00000100 |\
  58         HRCWH_BOOTSEQ_DISABLE |\
  59         HRCWH_SW_WATCHDOG_DISABLE |\
  60         HRCWH_ROM_LOC_LOCAL_16BIT |\
  61         HRCWH_BIG_ENDIAN |\
  62         HRCWH_LALE_NORMAL)
  63 #endif
  64
  65 /*
  66  * System IO Config
  67  */
  68 #define CONFIG_SYS_SICRL                0x00000000
  69
  70 /*
  71  * IMMR new address
  72  */
  73 #define CONFIG_SYS_IMMR         0xE0000000
  74
  75 /*
  76  * DDR Setup
  77  */
  78 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  79 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  80 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  81 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  82
  83 #undef CONFIG_SPD_EEPROM
  84 #if defined(CONFIG_SPD_EEPROM)
  85 /* Determine DDR configuration from I2C interface
  86  */
  87 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  88 #else
  89 /* Manually set up DDR parameters
  90  */
  91 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
  92 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  93                                         | CSCONFIG_AP \
  94                                         | CSCONFIG_ODT_WR_CFG \
  95                                         | CSCONFIG_ROW_BIT_13 \
  96                                         | CSCONFIG_COL_BIT_10)
  97                                         /* 0x80840102 */
  98 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
  99                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
 100                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
 101                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
 102                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 103                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 104                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 105                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 106                                         /* 0x00220802 */
 107 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 108                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 109                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 110                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 111                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
 112                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
 113                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 114                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
 115                                         /* 0x3935D322 */
 116 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 117                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 118                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 119                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 120                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 121                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 122                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
 123                                 /* 0x0F9048CA */
 124 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 125 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 126                                         /* 0x02000000 */
 127 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
 128                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
 129                                         /* 0x44400232 */
 130 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 131 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 132                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 133                                         /* 0x03200064 */
 134 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
 135 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 136                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 137                                         | SDRAM_CFG_32_BE)
 138                                         /* 0x43080000 */
 139 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 140 #endif
 141
 142 /*
 143  * Memory test
 144  */
 145 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 146 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
 147 #define CONFIG_SYS_MEMTEST_END          0x00100000
 148
 149 /*
 150  * The reserved memory
 151  */
 152 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 153
 154 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 155 #define CONFIG_SYS_RAMBOOT
 156 #else
 157 #undef  CONFIG_SYS_RAMBOOT
 158 #endif
 159
 160 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 161 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 162 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 163
 164 /*
 165  * Initial RAM Base Address Setup
 166  */
 167 #define CONFIG_SYS_INIT_RAM_LOCK        1
 168 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 169 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 170 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 171                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 172
 173 /*
 174  * Local Bus Configuration & Clock Setup
 175  */
 176 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 177 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 178 #define CONFIG_SYS_LBC_LBCR             0x00000000
 179
 180 /*
 181  * FLASH on the Local Bus
 182  */
 183 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 184 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 185
 186                                         /* Window base at flash base */
 187 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 188 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 189
 190 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 191                                 | BR_PS_16      /* 16 bit port */ \
 192                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 193                                 | BR_V)         /* valid */
 194 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 195                                 | OR_GPCM_XAM \
 196                                 | OR_GPCM_CSNT \
 197                                 | OR_GPCM_ACS_DIV2 \
 198                                 | OR_GPCM_XACS \
 199                                 | OR_GPCM_SCY_15 \
 200                                 | OR_GPCM_TRLX_SET \
 201                                 | OR_GPCM_EHTR_SET \
 202                                 | OR_GPCM_EAD)
 203                                 /* 0xfe006ff7 */
 204
 205 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 206 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 207
 208 #undef CONFIG_SYS_FLASH_CHECKSUM
 209
 210 /*
 211  * BCSR on the Local Bus
 212  */
 213 #define CONFIG_SYS_BCSR                 0xF8000000
 214                                         /* Access window base at BCSR base */
 215 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 216 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 217
 218 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 219                                         | BR_PS_8 \
 220                                         | BR_MS_GPCM \
 221                                         | BR_V)
 222 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 223                                         | OR_GPCM_XAM \
 224                                         | OR_GPCM_CSNT \
 225                                         | OR_GPCM_XACS \
 226                                         | OR_GPCM_SCY_15 \
 227                                         | OR_GPCM_TRLX_SET \
 228                                         | OR_GPCM_EHTR_SET \
 229                                         | OR_GPCM_EAD)
 230                                         /* 0xFFFFE9F7 */
 231
 232 /*
 233  * Windows to access PIB via local bus
 234  */
 235                                         /* PIB window base 0xF8008000 */
 236 #define CONFIG_SYS_PIB_BASE             0xF8008000
 237 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 238 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PIB_BASE
 239 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 240
 241 /*
 242  * CS2 on Local Bus, to PIB
 243  */
 244 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_PIB_BASE \
 245                                 | BR_PS_8 \
 246                                 | BR_MS_GPCM \
 247                                 | BR_V)
 248                                 /* 0xF8008801 */
 249 #define CONFIG_SYS_OR2_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 250                                 | OR_GPCM_XAM \
 251                                 | OR_GPCM_CSNT \
 252                                 | OR_GPCM_XACS \
 253                                 | OR_GPCM_SCY_15 \
 254                                 | OR_GPCM_TRLX_SET \
 255                                 | OR_GPCM_EHTR_SET \
 256                                 | OR_GPCM_EAD)
 257                                 /* 0xffffe9f7 */
 258
 259 /*
 260  * CS3 on Local Bus, to PIB
 261  */
 262 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIB_BASE + \
 263                                         CONFIG_SYS_PIB_WINDOW_SIZE) \
 264                                 | BR_PS_8 \
 265                                 | BR_MS_GPCM \
 266                                 | BR_V)
 267                                 /* 0xF8010801 */
 268 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
 269                                 | OR_GPCM_XAM \
 270                                 | OR_GPCM_CSNT \
 271                                 | OR_GPCM_XACS \
 272                                 | OR_GPCM_SCY_15 \
 273                                 | OR_GPCM_TRLX_SET \
 274                                 | OR_GPCM_EHTR_SET \
 275                                 | OR_GPCM_EAD)
 276                                 /* 0xffffe9f7 */
 277
 278 /*
 279  * Serial Port
 280  */
 281 #define CONFIG_SYS_NS16550_SERIAL
 282 #define CONFIG_SYS_NS16550_REG_SIZE     1
 283 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 284
 285 #define CONFIG_SYS_BAUDRATE_TABLE  \
 286                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 287
 288 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 289 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 290
 291 /* I2C */
 292 #define CONFIG_SYS_I2C
 293 #define CONFIG_SYS_I2C_FSL
 294 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 295 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 296 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 297 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 298
 299 /*
 300  * Config on-board RTC
 301  */
 302 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 303 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 304
 305 /*
 306  * General PCI
 307  * Addresses are mapped 1-1.
 308  */
 309 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 310 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 311 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 312 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 313 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 314 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 315 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 316 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 317 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 318
 319 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 320 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 321 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 322
 323 #ifdef CONFIG_PCI
 324 #define CONFIG_PCI_INDIRECT_BRIDGE
 325
 326 #define CONFIG_83XX_PCI_STREAMING
 327
 328 #undef CONFIG_EEPRO100
 329 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 330 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 331
 332 #endif  /* CONFIG_PCI */
 333
 334 /*
 335  * QE UEC ethernet configuration
 336  */
 337 #define CONFIG_UEC_ETH
 338 #define CONFIG_ETHPRIME         "UEC0"
 339
 340 #define CONFIG_UEC_ETH1         /* ETH3 */
 341
 342 #ifdef CONFIG_UEC_ETH1
 343 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 344 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 345 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 346 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 347 #define CONFIG_SYS_UEC1_PHY_ADDR        3
 348 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 349 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 350 #endif
 351
 352 #define CONFIG_UEC_ETH2         /* ETH4 */
 353
 354 #ifdef CONFIG_UEC_ETH2
 355 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 356 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 357 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 358 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 359 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 360 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 361 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 362 #endif
 363
 364 /*
 365  * Environment
 366  */
 367 #ifndef CONFIG_SYS_RAMBOOT
 368         #define CONFIG_ENV_ADDR         \
 369                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 370         #define CONFIG_ENV_SECT_SIZE    0x20000
 371         #define CONFIG_ENV_SIZE         0x2000
 372 #else
 373         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 374         #define CONFIG_ENV_SIZE         0x2000
 375 #endif
 376
 377 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 378 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 379
 380 /*
 381  * BOOTP options
 382  */
 383 #define CONFIG_BOOTP_BOOTFILESIZE
 384
 385 /*
 386  * Command line configuration.
 387  */
 388
 389 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 390
 391 /*
 392  * Miscellaneous configurable options
 393  */
 394 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 395
 396 /*
 397  * For booting Linux, the board info and command line data
 398  * have to be in the first 256 MB of memory, since this is
 399  * the maximum mapped by the Linux kernel during initialization.
 400  */
 401                                         /* Initial Memory map for Linux */
 402 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 403 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 404
 405 /*
 406  * Core HID Setup
 407  */
 408 #define CONFIG_SYS_HID0_INIT    0x000000000
 409 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 410                                  HID0_ENABLE_INSTRUCTION_CACHE)
 411 #define CONFIG_SYS_HID2         HID2_HBE
 412
 413 /*
 414  * MMU Setup
 415  */
 416
 417 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 418
 419 /* DDR: cache cacheable */
 420 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 421                                 | BATL_PP_RW \
 422                                 | BATL_MEMCOHERENCE)
 423 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 424                                 | BATU_BL_256M \
 425                                 | BATU_VS \
 426                                 | BATU_VP)
 427 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 428 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 429
 430 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 431 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 432                                 | BATL_PP_RW \
 433                                 | BATL_CACHEINHIBIT \
 434                                 | BATL_GUARDEDSTORAGE)
 435 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 436                                 | BATU_BL_4M \
 437                                 | BATU_VS \
 438                                 | BATU_VP)
 439 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 440 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 441
 442 /* BCSR: cache-inhibit and guarded */
 443 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 444                                 | BATL_PP_RW \
 445                                 | BATL_CACHEINHIBIT \
 446                                 | BATL_GUARDEDSTORAGE)
 447 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 448                                 | BATU_BL_128K \
 449                                 | BATU_VS \
 450                                 | BATU_VP)
 451 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 452 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 453
 454 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 455 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 456                                 | BATL_PP_RW \
 457                                 | BATL_MEMCOHERENCE)
 458 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 459                                 | BATU_BL_32M \
 460                                 | BATU_VS \
 461                                 | BATU_VP)
 462 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 463                                 | BATL_PP_RW \
 464                                 | BATL_CACHEINHIBIT \
 465                                 | BATL_GUARDEDSTORAGE)
 466 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 467
 468 #define CONFIG_SYS_IBAT4L       (0)
 469 #define CONFIG_SYS_IBAT4U       (0)
 470 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 471 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 472
 473 /* Stack in dcache: cacheable, no memory coherence */
 474 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 475 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 476                                 | BATU_BL_128K \
 477                                 | BATU_VS \
 478                                 | BATU_VP)
 479 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 480 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 481
 482 #ifdef CONFIG_PCI
 483 /* PCI MEM space: cacheable */
 484 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 485                                 | BATL_PP_RW \
 486                                 | BATL_MEMCOHERENCE)
 487 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 488                                 | BATU_BL_256M \
 489                                 | BATU_VS \
 490                                 | BATU_VP)
 491 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 492 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 493 /* PCI MMIO space: cache-inhibit and guarded */
 494 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 495                                 | BATL_PP_RW \
 496                                 | BATL_CACHEINHIBIT \
 497                                 | BATL_GUARDEDSTORAGE)
 498 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 499                                 | BATU_BL_256M \
 500                                 | BATU_VS \
 501                                 | BATU_VP)
 502 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 503 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 504 #else
 505 #define CONFIG_SYS_IBAT6L       (0)
 506 #define CONFIG_SYS_IBAT6U       (0)
 507 #define CONFIG_SYS_IBAT7L       (0)
 508 #define CONFIG_SYS_IBAT7U       (0)
 509 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 510 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 511 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 512 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 513 #endif
 514
 515 #if defined(CONFIG_CMD_KGDB)
 516 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 517 #endif
 518
 519 /*
 520  * Environment Configuration
 521  */ #define CONFIG_ENV_OVERWRITE
 522
 523 #if defined(CONFIG_UEC_ETH)
 524 #define CONFIG_HAS_ETH0
 525 #define CONFIG_HAS_ETH1
 526 #endif
 527
 528 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 529
 530 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 531         "netdev=eth0\0"                                                 \
 532         "consoledev=ttyS0\0"                                            \
 533         "ramdiskaddr=1000000\0"                                         \
 534         "ramdiskfile=ramfs.83xx\0"                                      \
 535         "fdtaddr=780000\0"                                              \
 536         "fdtfile=mpc832x_mds.dtb\0"                                     \
 537         ""
 538
 539 #define CONFIG_NFSBOOTCOMMAND                                           \
 540         "setenv bootargs root=/dev/nfs rw "                             \
 541                 "nfsroot=$serverip:$rootpath "                          \
 542                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 543                                                         "$netdev:off "  \
 544                 "console=$consoledev,$baudrate $othbootargs;"           \
 545         "tftp $loadaddr $bootfile;"                                     \
 546         "tftp $fdtaddr $fdtfile;"                                       \
 547         "bootm $loadaddr - $fdtaddr"
 548
 549 #define CONFIG_RAMBOOTCOMMAND                                           \
 550         "setenv bootargs root=/dev/ram rw "                             \
 551                 "console=$consoledev,$baudrate $othbootargs;"           \
 552         "tftp $ramdiskaddr $ramdiskfile;"                               \
 553         "tftp $loadaddr $bootfile;"                                     \
 554         "tftp $fdtaddr $fdtfile;"                                       \
 555         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 556
 557 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 558
 559 #endif  /* __CONFIG_H */