include/configs/MPC832XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * High Level Configuration Options
  11  */
  12 #define CONFIG_E300             1       /* E300 family */
  13 #define CONFIG_QE               1       /* Has QE */
  14
  15 /*
  16  * System IO Config
  17  */
  18 #define CONFIG_SYS_SICRL                0x00000000
  19
  20 /*
  21  * DDR Setup
  22  */
  23 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  24 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  25 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  26 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  27
  28 #undef CONFIG_SPD_EEPROM
  29 #if defined(CONFIG_SPD_EEPROM)
  30 /* Determine DDR configuration from I2C interface
  31  */
  32 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  33 #else
  34 /* Manually set up DDR parameters
  35  */
  36 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
  37 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  38                                         | CSCONFIG_AP \
  39                                         | CSCONFIG_ODT_WR_CFG \
  40                                         | CSCONFIG_ROW_BIT_13 \
  41                                         | CSCONFIG_COL_BIT_10)
  42                                         /* 0x80840102 */
  43 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
  44                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
  45                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
  46                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
  47                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  48                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  49                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  50                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  51                                         /* 0x00220802 */
  52 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  53                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  54                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  55                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  56                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
  57                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
  58                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  59                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
  60                                         /* 0x3935D322 */
  61 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  62                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  63                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  64                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  65                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  66                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  67                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
  68                                 /* 0x0F9048CA */
  69 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
  70 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  71                                         /* 0x02000000 */
  72 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  73                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
  74                                         /* 0x44400232 */
  75 #define CONFIG_SYS_DDR_MODE2            0x8000c000
  76 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  77                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  78                                         /* 0x03200064 */
  79 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
  80 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  81                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  82                                         | SDRAM_CFG_32_BE)
  83                                         /* 0x43080000 */
  84 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  85 #endif
  86
  87 /*
  88  * Memory test
  89  */
  90 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  91 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  92 #define CONFIG_SYS_MEMTEST_END          0x00100000
  93
  94 /*
  95  * The reserved memory
  96  */
  97 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  98
  99 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 100 #define CONFIG_SYS_RAMBOOT
 101 #else
 102 #undef  CONFIG_SYS_RAMBOOT
 103 #endif
 104
 105 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 106 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 107 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 108
 109 /*
 110  * Initial RAM Base Address Setup
 111  */
 112 #define CONFIG_SYS_INIT_RAM_LOCK        1
 113 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 114 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 115 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 116                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 117
 118 /*
 119  * Local Bus Configuration & Clock Setup
 120  */
 121 #define CONFIG_SYS_LBC_LBCR             0x00000000
 122
 123 /*
 124  * FLASH on the Local Bus
 125  */
 126 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 127 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 128
 129
 130 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 131 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 132
 133 #undef CONFIG_SYS_FLASH_CHECKSUM
 134
 135 /*
 136  * BCSR on the Local Bus
 137  */
 138 #define CONFIG_SYS_BCSR                 0xF8000000
 139                                         /* Access window base at BCSR base */
 140
 141
 142 /*
 143  * Windows to access PIB via local bus
 144  */
 145                                         /* PIB window base 0xF8008000 */
 146 #define CONFIG_SYS_PIB_BASE             0xF8008000
 147 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 148
 149 /*
 150  * CS2 on Local Bus, to PIB
 151  */
 152
 153
 154 /*
 155  * CS3 on Local Bus, to PIB
 156  */
 157
 158
 159 /*
 160  * Serial Port
 161  */
 162 #define CONFIG_SYS_NS16550_SERIAL
 163 #define CONFIG_SYS_NS16550_REG_SIZE     1
 164 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 165
 166 #define CONFIG_SYS_BAUDRATE_TABLE  \
 167                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 168
 169 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 170 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 171
 172 /* I2C */
 173 #define CONFIG_SYS_I2C
 174 #define CONFIG_SYS_I2C_FSL
 175 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 176 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 177 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 178 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 179
 180 /*
 181  * Config on-board RTC
 182  */
 183 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 184 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 185
 186 /*
 187  * General PCI
 188  * Addresses are mapped 1-1.
 189  */
 190 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 191 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 192 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 193 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 194 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 195 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 196 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 197 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 198 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 199
 200 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 201 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 202 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 203
 204 #ifdef CONFIG_PCI
 205 #define CONFIG_PCI_INDIRECT_BRIDGE
 206
 207 #define CONFIG_83XX_PCI_STREAMING
 208
 209 #undef CONFIG_EEPRO100
 210 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 211 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 212
 213 #endif  /* CONFIG_PCI */
 214
 215 /*
 216  * QE UEC ethernet configuration
 217  */
 218 #define CONFIG_UEC_ETH
 219 #define CONFIG_ETHPRIME         "UEC0"
 220
 221 #define CONFIG_UEC_ETH1         /* ETH3 */
 222
 223 #ifdef CONFIG_UEC_ETH1
 224 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 225 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 226 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 227 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 228 #define CONFIG_SYS_UEC1_PHY_ADDR        3
 229 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 230 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 231 #endif
 232
 233 #define CONFIG_UEC_ETH2         /* ETH4 */
 234
 235 #ifdef CONFIG_UEC_ETH2
 236 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 237 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 238 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 239 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 240 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 241 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 242 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 243 #endif
 244
 245 /*
 246  * Environment
 247  */
 248 #ifndef CONFIG_SYS_RAMBOOT
 249         #define CONFIG_ENV_ADDR         \
 250                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 251         #define CONFIG_ENV_SECT_SIZE    0x20000
 252         #define CONFIG_ENV_SIZE         0x2000
 253 #else
 254         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 255         #define CONFIG_ENV_SIZE         0x2000
 256 #endif
 257
 258 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 259 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 260
 261 /*
 262  * BOOTP options
 263  */
 264 #define CONFIG_BOOTP_BOOTFILESIZE
 265
 266 /*
 267  * Command line configuration.
 268  */
 269
 270 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 271
 272 /*
 273  * Miscellaneous configurable options
 274  */
 275 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 276
 277 /*
 278  * For booting Linux, the board info and command line data
 279  * have to be in the first 256 MB of memory, since this is
 280  * the maximum mapped by the Linux kernel during initialization.
 281  */
 282                                         /* Initial Memory map for Linux */
 283 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 284 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 285
 286 #if defined(CONFIG_CMD_KGDB)
 287 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 288 #endif
 289
 290 /*
 291  * Environment Configuration
 292  */ #define CONFIG_ENV_OVERWRITE
 293
 294 #if defined(CONFIG_UEC_ETH)
 295 #define CONFIG_HAS_ETH0
 296 #define CONFIG_HAS_ETH1
 297 #endif
 298
 299 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 300
 301 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 302         "netdev=eth0\0"                                                 \
 303         "consoledev=ttyS0\0"                                            \
 304         "ramdiskaddr=1000000\0"                                         \
 305         "ramdiskfile=ramfs.83xx\0"                                      \
 306         "fdtaddr=780000\0"                                              \
 307         "fdtfile=mpc832x_mds.dtb\0"                                     \
 308         ""
 309
 310 #define CONFIG_NFSBOOTCOMMAND                                           \
 311         "setenv bootargs root=/dev/nfs rw "                             \
 312                 "nfsroot=$serverip:$rootpath "                          \
 313                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 314                                                         "$netdev:off "  \
 315                 "console=$consoledev,$baudrate $othbootargs;"           \
 316         "tftp $loadaddr $bootfile;"                                     \
 317         "tftp $fdtaddr $fdtfile;"                                       \
 318         "bootm $loadaddr - $fdtaddr"
 319
 320 #define CONFIG_RAMBOOTCOMMAND                                           \
 321         "setenv bootargs root=/dev/ram rw "                             \
 322                 "console=$consoledev,$baudrate $othbootargs;"           \
 323         "tftp $ramdiskaddr $ramdiskfile;"                               \
 324         "tftp $loadaddr $bootfile;"                                     \
 325         "tftp $fdtaddr $fdtfile;"                                       \
 326         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 327
 328 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 329
 330 #endif  /* __CONFIG_H */