1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
10 * High Level Configuration Options
12 #define CONFIG_E300 1 /* E300 family */
13 #define CONFIG_QE 1 /* Has QE */
18 #define CONFIG_SYS_SICRL 0x00000000
23 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
24 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
25 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
26 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
28 #undef CONFIG_SPD_EEPROM
29 #if defined(CONFIG_SPD_EEPROM)
30 /* Determine DDR configuration from I2C interface
32 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
34 /* Manually set up DDR parameters
36 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
37 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
39 | CSCONFIG_ODT_WR_CFG \
40 | CSCONFIG_ROW_BIT_13 \
41 | CSCONFIG_COL_BIT_10)
43 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
44 | (0 << TIMING_CFG0_WRT_SHIFT) \
45 | (0 << TIMING_CFG0_RRT_SHIFT) \
46 | (0 << TIMING_CFG0_WWT_SHIFT) \
47 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
48 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
49 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
50 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
52 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
53 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
54 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
55 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
56 | (13 << TIMING_CFG1_REFREC_SHIFT) \
57 | (3 << TIMING_CFG1_WRREC_SHIFT) \
58 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
59 | (2 << TIMING_CFG1_WRTORD_SHIFT))
61 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
62 | (31 << TIMING_CFG2_CPO_SHIFT) \
63 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
64 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
65 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
66 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
67 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
69 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
70 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
72 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
73 | (0x0232 << SDRAM_MODE_SD_SHIFT))
75 #define CONFIG_SYS_DDR_MODE2 0x8000c000
76 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
77 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
79 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
80 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
81 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
84 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
90 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
91 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
92 #define CONFIG_SYS_MEMTEST_END 0x00100000
97 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
99 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
100 #define CONFIG_SYS_RAMBOOT
102 #undef CONFIG_SYS_RAMBOOT
105 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
106 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
107 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
110 * Initial RAM Base Address Setup
112 #define CONFIG_SYS_INIT_RAM_LOCK 1
113 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
114 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
115 #define CONFIG_SYS_GBL_DATA_OFFSET \
116 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
119 * Local Bus Configuration & Clock Setup
121 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
122 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
123 #define CONFIG_SYS_LBC_LBCR 0x00000000
126 * FLASH on the Local Bus
128 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
129 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
132 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
133 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
135 #undef CONFIG_SYS_FLASH_CHECKSUM
138 * BCSR on the Local Bus
140 #define CONFIG_SYS_BCSR 0xF8000000
141 /* Access window base at BCSR base */
145 * Windows to access PIB via local bus
147 /* PIB window base 0xF8008000 */
148 #define CONFIG_SYS_PIB_BASE 0xF8008000
149 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
152 * CS2 on Local Bus, to PIB
157 * CS3 on Local Bus, to PIB
164 #define CONFIG_SYS_NS16550_SERIAL
165 #define CONFIG_SYS_NS16550_REG_SIZE 1
166 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
168 #define CONFIG_SYS_BAUDRATE_TABLE \
169 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
171 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
172 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
175 #define CONFIG_SYS_I2C
176 #define CONFIG_SYS_I2C_FSL
177 #define CONFIG_SYS_FSL_I2C_SPEED 400000
178 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
179 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
180 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
183 * Config on-board RTC
185 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
186 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
190 * Addresses are mapped 1-1.
192 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
193 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
194 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
195 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
196 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
197 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
198 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
199 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
200 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
202 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
203 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
204 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
207 #define CONFIG_PCI_INDIRECT_BRIDGE
209 #define CONFIG_83XX_PCI_STREAMING
211 #undef CONFIG_EEPRO100
212 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
213 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
215 #endif /* CONFIG_PCI */
218 * QE UEC ethernet configuration
220 #define CONFIG_UEC_ETH
221 #define CONFIG_ETHPRIME "UEC0"
223 #define CONFIG_UEC_ETH1 /* ETH3 */
225 #ifdef CONFIG_UEC_ETH1
226 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
227 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
228 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
229 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
230 #define CONFIG_SYS_UEC1_PHY_ADDR 3
231 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
232 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
235 #define CONFIG_UEC_ETH2 /* ETH4 */
237 #ifdef CONFIG_UEC_ETH2
238 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
239 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
240 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
241 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
242 #define CONFIG_SYS_UEC2_PHY_ADDR 4
243 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
244 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
250 #ifndef CONFIG_SYS_RAMBOOT
251 #define CONFIG_ENV_ADDR \
252 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
253 #define CONFIG_ENV_SECT_SIZE 0x20000
254 #define CONFIG_ENV_SIZE 0x2000
256 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
257 #define CONFIG_ENV_SIZE 0x2000
260 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
261 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
266 #define CONFIG_BOOTP_BOOTFILESIZE
269 * Command line configuration.
272 #undef CONFIG_WATCHDOG /* watchdog disabled */
275 * Miscellaneous configurable options
277 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
280 * For booting Linux, the board info and command line data
281 * have to be in the first 256 MB of memory, since this is
282 * the maximum mapped by the Linux kernel during initialization.
284 /* Initial Memory map for Linux */
285 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
286 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
288 #if defined(CONFIG_CMD_KGDB)
289 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
293 * Environment Configuration
294 */ #define CONFIG_ENV_OVERWRITE
296 #if defined(CONFIG_UEC_ETH)
297 #define CONFIG_HAS_ETH0
298 #define CONFIG_HAS_ETH1
301 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
303 #define CONFIG_EXTRA_ENV_SETTINGS \
305 "consoledev=ttyS0\0" \
306 "ramdiskaddr=1000000\0" \
307 "ramdiskfile=ramfs.83xx\0" \
309 "fdtfile=mpc832x_mds.dtb\0" \
312 #define CONFIG_NFSBOOTCOMMAND \
313 "setenv bootargs root=/dev/nfs rw " \
314 "nfsroot=$serverip:$rootpath " \
315 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
317 "console=$consoledev,$baudrate $othbootargs;" \
318 "tftp $loadaddr $bootfile;" \
319 "tftp $fdtaddr $fdtfile;" \
320 "bootm $loadaddr - $fdtaddr"
322 #define CONFIG_RAMBOOTCOMMAND \
323 "setenv bootargs root=/dev/ram rw " \
324 "console=$consoledev,$baudrate $othbootargs;" \
325 "tftp $ramdiskaddr $ramdiskfile;" \
326 "tftp $loadaddr $bootfile;" \
327 "tftp $fdtaddr $fdtfile;" \
328 "bootm $loadaddr $ramdiskaddr $fdtaddr"
330 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
332 #endif /* __CONFIG_H */