include/configs/MPC832XEMDS.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_E300             1       /* E300 family */
  27 #define CONFIG_QE               1       /* Has QE */
  28 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  29 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
  30 #define CONFIG_MPC832XEMDS      1       /* MPC832XEMDS board specific */
  31
  32 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  33
  34 /*
  35  * System Clock Setup
  36  */
  37 #ifdef CONFIG_PCISLAVE
  38 #define CONFIG_83XX_PCICLK      66000000        /* in HZ */
  39 #else
  40 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  41 #endif
  42
  43 #ifndef CONFIG_SYS_CLK_FREQ
  44 #define CONFIG_SYS_CLK_FREQ     66000000
  45 #endif
  46
  47 /*
  48  * Hardware Reset Configuration Word
  49  */
  50 #define CONFIG_SYS_HRCW_LOW (\
  51         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  52         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  53         HRCWL_VCO_1X2 |\
  54         HRCWL_CSB_TO_CLKIN_2X1 |\
  55         HRCWL_CORE_TO_CSB_2X1 |\
  56         HRCWL_CE_PLL_VCO_DIV_2 |\
  57         HRCWL_CE_PLL_DIV_1X1 |\
  58         HRCWL_CE_TO_PLL_1X3)
  59
  60 #ifdef CONFIG_PCISLAVE
  61 #define CONFIG_SYS_HRCW_HIGH (\
  62         HRCWH_PCI_AGENT |\
  63         HRCWH_PCI1_ARBITER_DISABLE |\
  64         HRCWH_CORE_ENABLE |\
  65         HRCWH_FROM_0XFFF00100 |\
  66         HRCWH_BOOTSEQ_DISABLE |\
  67         HRCWH_SW_WATCHDOG_DISABLE |\
  68         HRCWH_ROM_LOC_LOCAL_16BIT |\
  69         HRCWH_BIG_ENDIAN |\
  70         HRCWH_LALE_NORMAL)
  71 #else
  72 #define CONFIG_SYS_HRCW_HIGH (\
  73         HRCWH_PCI_HOST |\
  74         HRCWH_PCI1_ARBITER_ENABLE |\
  75         HRCWH_CORE_ENABLE |\
  76         HRCWH_FROM_0X00000100 |\
  77         HRCWH_BOOTSEQ_DISABLE |\
  78         HRCWH_SW_WATCHDOG_DISABLE |\
  79         HRCWH_ROM_LOC_LOCAL_16BIT |\
  80         HRCWH_BIG_ENDIAN |\
  81         HRCWH_LALE_NORMAL)
  82 #endif
  83
  84 /*
  85  * System IO Config
  86  */
  87 #define CONFIG_SYS_SICRL                0x00000000
  88
  89 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_pre_init */
  90 #define CONFIG_BOARD_EARLY_INIT_R
  91
  92 /*
  93  * IMMR new address
  94  */
  95 #define CONFIG_SYS_IMMR         0xE0000000
  96
  97 /*
  98  * DDR Setup
  99  */
 100 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
 101 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
 102 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 103 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
 104
 105 #undef CONFIG_SPD_EEPROM
 106 #if defined(CONFIG_SPD_EEPROM)
 107 /* Determine DDR configuration from I2C interface
 108  */
 109 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
 110 #else
 111 /* Manually set up DDR parameters
 112  */
 113 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
 114 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 115                                         | CSCONFIG_AP \
 116                                         | CSCONFIG_ODT_WR_CFG \
 117                                         | CSCONFIG_ROW_BIT_13 \
 118                                         | CSCONFIG_COL_BIT_10)
 119                                         /* 0x80840102 */
 120 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
 121                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
 122                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
 123                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
 124                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 125                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 126                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 127                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 128                                         /* 0x00220802 */
 129 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 130                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 131                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 132                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 133                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
 134                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
 135                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 136                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
 137                                         /* 0x3935D322 */
 138 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 139                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 140                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 141                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 142                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 143                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 144                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
 145                                 /* 0x0F9048CA */
 146 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 147 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 148                                         /* 0x02000000 */
 149 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
 150                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
 151                                         /* 0x44400232 */
 152 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 153 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 154                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 155                                         /* 0x03200064 */
 156 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
 157 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 158                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 159                                         | SDRAM_CFG_32_BE)
 160                                         /* 0x43080000 */
 161 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 162 #endif
 163
 164 /*
 165  * Memory test
 166  */
 167 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 168 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
 169 #define CONFIG_SYS_MEMTEST_END          0x00100000
 170
 171 /*
 172  * The reserved memory
 173  */
 174 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 175
 176 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 177 #define CONFIG_SYS_RAMBOOT
 178 #else
 179 #undef  CONFIG_SYS_RAMBOOT
 180 #endif
 181
 182 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 183 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
 184 #define CONFIG_SYS_MALLOC_LEN   (128 * 1024)    /* Reserved for malloc */
 185
 186 /*
 187  * Initial RAM Base Address Setup
 188  */
 189 #define CONFIG_SYS_INIT_RAM_LOCK        1
 190 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 191 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 192 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 193                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 194
 195 /*
 196  * Local Bus Configuration & Clock Setup
 197  */
 198 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 199 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 200 #define CONFIG_SYS_LBC_LBCR             0x00000000
 201
 202 /*
 203  * FLASH on the Local Bus
 204  */
 205 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 206 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 207 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 208 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 209 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 210
 211                                         /* Window base at flash base */
 212 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 213 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018      /* 32MB window size */
 214
 215 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 216                                 | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
 217                                 | BR_V)                 /* valid */
 218 #define CONFIG_SYS_OR0_PRELIM   0xfe006ff7              /* 16MB Flash size */
 219
 220 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 221 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 222
 223 #undef CONFIG_SYS_FLASH_CHECKSUM
 224
 225 /*
 226  * BCSR on the Local Bus
 227  */
 228 #define CONFIG_SYS_BCSR                 0xF8000000
 229                                         /* Access window base at BCSR base */
 230 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 231                                         /* Access window size 32K */
 232 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E
 233
 234                                         /* Port size=8bit, MSEL=GPCM */
 235 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR|0x00000801)
 236 #define CONFIG_SYS_OR1_PRELIM           0xFFFFE9f7      /* length 32K */
 237
 238 /*
 239  * SDRAM on the Local Bus
 240  */
 241 #undef CONFIG_SYS_LB_SDRAM      /* The board has not SRDAM on local bus */
 242
 243 #ifdef CONFIG_SYS_LB_SDRAM
 244 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* SDRAM base address */
 245 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 246
 247 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 248 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019      /* 64MB */
 249
 250 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 251 /*
 252  * Base Register 2 and Option Register 2 configure SDRAM.
 253  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 254  *
 255  * For BR2, need:
 256  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 257  *    port size = 32-bits = BR2[19:20] = 11
 258  *    no parity checking = BR2[21:22] = 00
 259  *    SDRAM for MSEL = BR2[24:26] = 011
 260  *    Valid = BR[31] = 1
 261  *
 262  * 0    4    8    12   16   20   24   28
 263  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 264  *
 265  * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 266  * the top 17 bits of BR2.
 267  */
 268
 269 #define CONFIG_SYS_BR2_PRELIM   0xf0001861      /*Port size=32bit, MSEL=SDRAM */
 270
 271 /*
 272  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 273  *
 274  * For OR2, need:
 275  *    64MB mask for AM, OR2[0:7] = 1111 1100
 276  *                 XAM, OR2[17:18] = 11
 277  *    9 columns OR2[19-21] = 010
 278  *    13 rows   OR2[23-25] = 100
 279  *    EAD set for extra time OR[31] = 1
 280  *
 281  * 0    4    8    12   16   20   24   28
 282  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 283  */
 284
 285 #define CONFIG_SYS_OR2_PRELIM   0xfc006901
 286
 287                                 /* LB sdram refresh timer, about 6us */
 288 #define CONFIG_SYS_LBC_LSRT     0x32000000
 289                                 /* LB refresh timer prescal, 266MHz/32 */
 290 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 291
 292 #define CONFIG_SYS_LBC_LSDMR_COMMON     0x0063b723
 293
 294 #endif
 295
 296 /*
 297  * Windows to access PIB via local bus
 298  */
 299                                         /* windows base 0xf8008000 */
 300 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0xf8008000
 301                                         /* windows size 64KB */
 302 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000f
 303
 304 /*
 305  * CS2 on Local Bus, to PIB
 306  */
 307                                 /* CS2 base address at 0xf8008000 */
 308 #define CONFIG_SYS_BR2_PRELIM   0xf8008801
 309                                 /* size 32KB, port size 8bit, GPCM */
 310 #define CONFIG_SYS_OR2_PRELIM   0xffffe9f7
 311
 312 /*
 313  * CS3 on Local Bus, to PIB
 314  */
 315                                 /* CS3 base address at 0xf8010000 */
 316 #define CONFIG_SYS_BR3_PRELIM   0xf8010801
 317                                 /* size 32KB, port size 8bit, GPCM */
 318 #define CONFIG_SYS_OR3_PRELIM   0xffffe9f7
 319
 320 /*
 321  * Serial Port
 322  */
 323 #define CONFIG_CONS_INDEX       1
 324 #define CONFIG_SYS_NS16550
 325 #define CONFIG_SYS_NS16550_SERIAL
 326 #define CONFIG_SYS_NS16550_REG_SIZE     1
 327 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 328
 329 #define CONFIG_SYS_BAUDRATE_TABLE  \
 330                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 331
 332 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 333 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 334
 335 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 336 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 337 /* Use the HUSH parser */
 338 #define CONFIG_SYS_HUSH_PARSER
 339 #ifdef CONFIG_SYS_HUSH_PARSER
 340 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 341 #endif
 342
 343 /* pass open firmware flat tree */
 344 #define CONFIG_OF_LIBFDT        1
 345 #define CONFIG_OF_BOARD_SETUP   1
 346 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 347
 348 /* I2C */
 349 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 350 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 351 #define CONFIG_FSL_I2C
 352 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 353 #define CONFIG_SYS_I2C_SLAVE    0x7F
 354 #define CONFIG_SYS_I2C_NOPROBES {0x51}  /* Don't probe these addrs */
 355 #define CONFIG_SYS_I2C_OFFSET   0x3000
 356
 357 /*
 358  * Config on-board RTC
 359  */
 360 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 361 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 362
 363 /*
 364  * General PCI
 365  * Addresses are mapped 1-1.
 366  */
 367 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 368 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 369 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 370 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 371 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 372 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 373 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 374 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 375 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 376
 377 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 378 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 379 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 380
 381
 382 #ifdef CONFIG_PCI
 383
 384 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 385 #define CONFIG_83XX_PCI_STREAMING
 386
 387 #undef CONFIG_EEPRO100
 388 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 389 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 390
 391 #endif  /* CONFIG_PCI */
 392
 393 /*
 394  * QE UEC ethernet configuration
 395  */
 396 #define CONFIG_UEC_ETH
 397 #define CONFIG_ETHPRIME         "UEC0"
 398
 399 #define CONFIG_UEC_ETH1         /* ETH3 */
 400
 401 #ifdef CONFIG_UEC_ETH1
 402 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 403 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 404 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 405 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 406 #define CONFIG_SYS_UEC1_PHY_ADDR        3
 407 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 408 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 409 #endif
 410
 411 #define CONFIG_UEC_ETH2         /* ETH4 */
 412
 413 #ifdef CONFIG_UEC_ETH2
 414 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 415 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 416 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 417 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 418 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 419 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 420 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 421 #endif
 422
 423 /*
 424  * Environment
 425  */
 426 #ifndef CONFIG_SYS_RAMBOOT
 427         #define CONFIG_ENV_IS_IN_FLASH  1
 428         #define CONFIG_ENV_ADDR         \
 429                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 430         #define CONFIG_ENV_SECT_SIZE    0x20000
 431         #define CONFIG_ENV_SIZE         0x2000
 432 #else
 433         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 434         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 435         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 436         #define CONFIG_ENV_SIZE         0x2000
 437 #endif
 438
 439 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 440 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 441
 442 /*
 443  * BOOTP options
 444  */
 445 #define CONFIG_BOOTP_BOOTFILESIZE
 446 #define CONFIG_BOOTP_BOOTPATH
 447 #define CONFIG_BOOTP_GATEWAY
 448 #define CONFIG_BOOTP_HOSTNAME
 449
 450
 451 /*
 452  * Command line configuration.
 453  */
 454 #include <config_cmd_default.h>
 455
 456 #define CONFIG_CMD_PING
 457 #define CONFIG_CMD_I2C
 458 #define CONFIG_CMD_ASKENV
 459
 460 #if defined(CONFIG_PCI)
 461     #define CONFIG_CMD_PCI
 462 #endif
 463
 464 #if defined(CONFIG_SYS_RAMBOOT)
 465     #undef CONFIG_CMD_SAVEENV
 466     #undef CONFIG_CMD_LOADS
 467 #endif
 468
 469
 470 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 471
 472 /*
 473  * Miscellaneous configurable options
 474  */
 475 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 476 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 477 #define CONFIG_SYS_PROMPT       "=> "   /* Monitor Command Prompt */
 478
 479 #if defined(CONFIG_CMD_KGDB)
 480         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 481 #else
 482         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 483 #endif
 484
 485                                 /* Print Buffer Size */
 486 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 487 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 488                                 /* Boot Argument Buffer Size */
 489 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 490 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 491
 492 /*
 493  * For booting Linux, the board info and command line data
 494  * have to be in the first 256 MB of memory, since this is
 495  * the maximum mapped by the Linux kernel during initialization.
 496  */
 497                                         /* Initial Memory map for Linux */
 498 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 499
 500 /*
 501  * Core HID Setup
 502  */
 503 #define CONFIG_SYS_HID0_INIT    0x000000000
 504 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 505                                  HID0_ENABLE_INSTRUCTION_CACHE)
 506 #define CONFIG_SYS_HID2         HID2_HBE
 507
 508 /*
 509  * MMU Setup
 510  */
 511
 512 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 513
 514 /* DDR: cache cacheable */
 515 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 516                                 | BATL_PP_RW \
 517                                 | BATL_MEMCOHERENCE)
 518 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 519                                 | BATU_BL_256M \
 520                                 | BATU_VS \
 521                                 | BATU_VP)
 522 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 523 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 524
 525 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 526 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 527                                 | BATL_PP_RW \
 528                                 | BATL_CACHEINHIBIT \
 529                                 | BATL_GUARDEDSTORAGE)
 530 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 531                                 | BATU_BL_4M \
 532                                 | BATU_VS \
 533                                 | BATU_VP)
 534 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 535 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 536
 537 /* BCSR: cache-inhibit and guarded */
 538 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 539                                 | BATL_PP_RW \
 540                                 | BATL_CACHEINHIBIT \
 541                                 | BATL_GUARDEDSTORAGE)
 542 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 543                                 | BATU_BL_128K \
 544                                 | BATU_VS \
 545                                 | BATU_VP)
 546 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 547 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 548
 549 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 550 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 551                                 | BATL_PP_RW \
 552                                 | BATL_MEMCOHERENCE)
 553 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 554                                 | BATU_BL_32M \
 555                                 | BATU_VS \
 556                                 | BATU_VP)
 557 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 558                                 | BATL_PP_RW \
 559                                 | BATL_CACHEINHIBIT \
 560                                 | BATL_GUARDEDSTORAGE)
 561 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 562
 563 #define CONFIG_SYS_IBAT4L       (0)
 564 #define CONFIG_SYS_IBAT4U       (0)
 565 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 566 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 567
 568 /* Stack in dcache: cacheable, no memory coherence */
 569 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 570 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 571                                 | BATU_BL_128K \
 572                                 | BATU_VS \
 573                                 | BATU_VP)
 574 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 575 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 576
 577 #ifdef CONFIG_PCI
 578 /* PCI MEM space: cacheable */
 579 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 580                                 | BATL_PP_RW \
 581                                 | BATL_MEMCOHERENCE)
 582 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 583                                 | BATU_BL_256M \
 584                                 | BATU_VS \
 585                                 | BATU_VP)
 586 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 587 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 588 /* PCI MMIO space: cache-inhibit and guarded */
 589 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 590                                 | BATL_PP_RW \
 591                                 | BATL_CACHEINHIBIT \
 592                                 | BATL_GUARDEDSTORAGE)
 593 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 594                                 | BATU_BL_256M \
 595                                 | BATU_VS \
 596                                 | BATU_VP)
 597 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 598 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 599 #else
 600 #define CONFIG_SYS_IBAT6L       (0)
 601 #define CONFIG_SYS_IBAT6U       (0)
 602 #define CONFIG_SYS_IBAT7L       (0)
 603 #define CONFIG_SYS_IBAT7U       (0)
 604 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 605 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 606 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 607 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 608 #endif
 609
 610 #if defined(CONFIG_CMD_KGDB)
 611 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 612 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 613 #endif
 614
 615 /*
 616  * Environment Configuration
 617  */ #define CONFIG_ENV_OVERWRITE
 618
 619 #if defined(CONFIG_UEC_ETH)
 620 #define CONFIG_HAS_ETH0
 621 #define CONFIG_HAS_ETH1
 622 #endif
 623
 624 #define CONFIG_BAUDRATE 115200
 625
 626 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 627
 628 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 629 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 630
 631 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 632         "netdev=eth0\0"                                                 \
 633         "consoledev=ttyS0\0"                                            \
 634         "ramdiskaddr=1000000\0"                                         \
 635         "ramdiskfile=ramfs.83xx\0"                                      \
 636         "fdtaddr=780000\0"                                              \
 637         "fdtfile=mpc832x_mds.dtb\0"                                     \
 638         ""
 639
 640 #define CONFIG_NFSBOOTCOMMAND                                           \
 641         "setenv bootargs root=/dev/nfs rw "                             \
 642                 "nfsroot=$serverip:$rootpath "                          \
 643                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 644                                                         "$netdev:off "  \
 645                 "console=$consoledev,$baudrate $othbootargs;"           \
 646         "tftp $loadaddr $bootfile;"                                     \
 647         "tftp $fdtaddr $fdtfile;"                                       \
 648         "bootm $loadaddr - $fdtaddr"
 649
 650 #define CONFIG_RAMBOOTCOMMAND                                           \
 651         "setenv bootargs root=/dev/ram rw "                             \
 652                 "console=$consoledev,$baudrate $othbootargs;"           \
 653         "tftp $ramdiskaddr $ramdiskfile;"                               \
 654         "tftp $loadaddr $bootfile;"                                     \
 655         "tftp $fdtaddr $fdtfile;"                                       \
 656         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 657
 658
 659 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 660
 661 #endif  /* __CONFIG_H */