Move CONFIG_OF_LIBFDT to Kconfig
[platform/kernel/u-boot.git] / include / configs / MPC8323ERDB.h
1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of the GNU General Public License version 2 as published
6  * by the Free Software Foundation.
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #define CONFIG_DISPLAY_BOARDINFO
13
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_E300             1       /* E300 family */
18 #define CONFIG_QE               1       /* Has QE */
19 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
20
21 #define CONFIG_SYS_TEXT_BASE    0xFE000000
22
23 #define CONFIG_PCI              1
24
25 /*
26  * System Clock Setup
27  */
28 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
29
30 #ifndef CONFIG_SYS_CLK_FREQ
31 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
32 #endif
33
34 /*
35  * Hardware Reset Configuration Word
36  */
37 #define CONFIG_SYS_HRCW_LOW (\
38         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
39         HRCWL_DDR_TO_SCB_CLK_2X1 |\
40         HRCWL_VCO_1X2 |\
41         HRCWL_CSB_TO_CLKIN_2X1 |\
42         HRCWL_CORE_TO_CSB_2_5X1 |\
43         HRCWL_CE_PLL_VCO_DIV_2 |\
44         HRCWL_CE_PLL_DIV_1X1 |\
45         HRCWL_CE_TO_PLL_1X3)
46
47 #define CONFIG_SYS_HRCW_HIGH (\
48         HRCWH_PCI_HOST |\
49         HRCWH_PCI1_ARBITER_ENABLE |\
50         HRCWH_CORE_ENABLE |\
51         HRCWH_FROM_0X00000100 |\
52         HRCWH_BOOTSEQ_DISABLE |\
53         HRCWH_SW_WATCHDOG_DISABLE |\
54         HRCWH_ROM_LOC_LOCAL_16BIT |\
55         HRCWH_BIG_ENDIAN |\
56         HRCWH_LALE_NORMAL)
57
58 /*
59  * System IO Config
60  */
61 #define CONFIG_SYS_SICRL                0x00000000
62
63 /*
64  * IMMR new address
65  */
66 #define CONFIG_SYS_IMMR         0xE0000000
67
68 /*
69  * System performance
70  */
71 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
72 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
73 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
74 #define CONFIG_SYS_SPCR_OPT     1
75
76 /*
77  * DDR Setup
78  */
79 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
80 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
81 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
82
83 #undef CONFIG_SPD_EEPROM
84 #if defined(CONFIG_SPD_EEPROM)
85 /* Determine DDR configuration from I2C interface
86  */
87 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
88 #else
89 /* Manually set up DDR parameters
90  */
91 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
92 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
93                                 | CSCONFIG_ROW_BIT_13 \
94                                 | CSCONFIG_COL_BIT_9)
95                                 /* 0x80010101 */
96 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
97                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
98                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
99                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
100                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
101                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
102                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
103                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
104                                 /* 0x00220802 */
105 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
106                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
107                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
108                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
109                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
110                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
111                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
112                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
113                                 /* 0x26253222 */
114 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
115                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
116                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
117                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
118                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
119                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
120                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
121                                 /* 0x1f9048c7 */
122 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
123 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
124                                 /* 0x02000000 */
125 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
126                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
127                                 /* 0x44480232 */
128 #define CONFIG_SYS_DDR_MODE2    0x8000c000
129 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
130                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
131                                 /* 0x03200064 */
132 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
133 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
134                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
135                                 | SDRAM_CFG_32_BE)
136                                 /* 0x43080000 */
137 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
138 #endif
139
140 /*
141  * Memory test
142  */
143 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
144 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
145 #define CONFIG_SYS_MEMTEST_END          0x03f00000
146
147 /*
148  * The reserved memory
149  */
150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
151
152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
153 #define CONFIG_SYS_RAMBOOT
154 #else
155 #undef  CONFIG_SYS_RAMBOOT
156 #endif
157
158 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
159 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
160 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
161
162 /*
163  * Initial RAM Base Address Setup
164  */
165 #define CONFIG_SYS_INIT_RAM_LOCK        1
166 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
167 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
168 #define CONFIG_SYS_GBL_DATA_OFFSET      \
169                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
170
171 /*
172  * Local Bus Configuration & Clock Setup
173  */
174 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
175 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
176 #define CONFIG_SYS_LBC_LBCR             0x00000000
177
178 /*
179  * FLASH on the Local Bus
180  */
181 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
182 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
183 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
184 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
185 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
186
187                                         /* Window base at flash base */
188 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
189 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
190
191 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
192                                 | BR_PS_16      /* 16 bit port */ \
193                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
194                                 | BR_V)         /* valid */
195 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
196                                 | OR_GPCM_XAM \
197                                 | OR_GPCM_CSNT \
198                                 | OR_GPCM_ACS_DIV2 \
199                                 | OR_GPCM_XACS \
200                                 | OR_GPCM_SCY_15 \
201                                 | OR_GPCM_TRLX_SET \
202                                 | OR_GPCM_EHTR_SET \
203                                 | OR_GPCM_EAD)
204                                 /* 0xFE006FF7 */
205
206 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
207 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
208
209 #undef CONFIG_SYS_FLASH_CHECKSUM
210
211 /*
212  * Serial Port
213  */
214 #define CONFIG_CONS_INDEX       1
215 #define CONFIG_SYS_NS16550_SERIAL
216 #define CONFIG_SYS_NS16550_REG_SIZE     1
217 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
218
219 #define CONFIG_SYS_BAUDRATE_TABLE  \
220                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
221
222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
223 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
224
225 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
226 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
227 /* Use the HUSH parser */
228 #define CONFIG_SYS_HUSH_PARSER
229
230 /* pass open firmware flat tree */
231 #define CONFIG_OF_BOARD_SETUP   1
232 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
233
234 /* I2C */
235 #define CONFIG_SYS_I2C
236 #define CONFIG_SYS_I2C_FSL
237 #define CONFIG_SYS_FSL_I2C_SPEED        400000
238 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
239 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
240 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
241
242 /*
243  * Config on-board EEPROM
244  */
245 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
246 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
247 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
248 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
249
250 /*
251  * General PCI
252  * Addresses are mapped 1-1.
253  */
254 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
255 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
256 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
257 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
258 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
259 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
260 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
261 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
262 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
263
264 #ifdef CONFIG_PCI
265 #define CONFIG_PCI_INDIRECT_BRIDGE
266 #define CONFIG_PCI_SKIP_HOST_BRIDGE
267 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
268
269 #undef CONFIG_EEPRO100
270 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
271 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
272
273 #endif  /* CONFIG_PCI */
274
275 /*
276  * QE UEC ethernet configuration
277  */
278 #define CONFIG_UEC_ETH
279 #define CONFIG_ETHPRIME         "UEC0"
280
281 #define CONFIG_UEC_ETH1         /* ETH3 */
282
283 #ifdef CONFIG_UEC_ETH1
284 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
285 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
286 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
287 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
288 #define CONFIG_SYS_UEC1_PHY_ADDR        4
289 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
290 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
291 #endif
292
293 #define CONFIG_UEC_ETH2         /* ETH4 */
294
295 #ifdef CONFIG_UEC_ETH2
296 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
297 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
298 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
299 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
300 #define CONFIG_SYS_UEC2_PHY_ADDR        0
301 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
302 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
303 #endif
304
305 /*
306  * Environment
307  */
308 #ifndef CONFIG_SYS_RAMBOOT
309         #define CONFIG_ENV_IS_IN_FLASH  1
310         #define CONFIG_ENV_ADDR         \
311                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
312         #define CONFIG_ENV_SECT_SIZE    0x20000
313         #define CONFIG_ENV_SIZE         0x2000
314 #else
315         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
316         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
317         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
318         #define CONFIG_ENV_SIZE         0x2000
319 #endif
320
321 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
322 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
323
324 /*
325  * BOOTP options
326  */
327 #define CONFIG_BOOTP_BOOTFILESIZE
328 #define CONFIG_BOOTP_BOOTPATH
329 #define CONFIG_BOOTP_GATEWAY
330 #define CONFIG_BOOTP_HOSTNAME
331
332 /*
333  * Command line configuration.
334  */
335 #define CONFIG_CMD_PING
336 #define CONFIG_CMD_I2C
337 #define CONFIG_CMD_EEPROM
338 #define CONFIG_CMD_ASKENV
339
340 #if defined(CONFIG_PCI)
341         #define CONFIG_CMD_PCI
342 #endif
343
344 #undef CONFIG_WATCHDOG          /* watchdog disabled */
345
346 /*
347  * Miscellaneous configurable options
348  */
349 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
350 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
351
352 #if (CONFIG_CMD_KGDB)
353         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
354 #else
355         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
356 #endif
357
358                                 /* Print Buffer Size */
359 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
360 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
361                                 /* Boot Argument Buffer Size */
362 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
363
364 /*
365  * For booting Linux, the board info and command line data
366  * have to be in the first 256 MB of memory, since this is
367  * the maximum mapped by the Linux kernel during initialization.
368  */
369                                         /* Initial Memory map for Linux */
370 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
371
372 /*
373  * Core HID Setup
374  */
375 #define CONFIG_SYS_HID0_INIT    0x000000000
376 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
377                                  HID0_ENABLE_INSTRUCTION_CACHE)
378 #define CONFIG_SYS_HID2         HID2_HBE
379
380 /*
381  * MMU Setup
382  */
383 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
384
385 /* DDR: cache cacheable */
386 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
387                                 | BATL_PP_RW \
388                                 | BATL_MEMCOHERENCE)
389 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
390                                 | BATU_BL_256M \
391                                 | BATU_VS \
392                                 | BATU_VP)
393 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
394 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
395
396 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
397 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
398                                 | BATL_PP_RW \
399                                 | BATL_CACHEINHIBIT \
400                                 | BATL_GUARDEDSTORAGE)
401 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
402                                 | BATU_BL_4M \
403                                 | BATU_VS \
404                                 | BATU_VP)
405 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
406 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
407
408 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
409 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
410                                 | BATL_PP_RW \
411                                 | BATL_MEMCOHERENCE)
412 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
413                                 | BATU_BL_32M \
414                                 | BATU_VS \
415                                 | BATU_VP)
416 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
417                                 | BATL_PP_RW \
418                                 | BATL_CACHEINHIBIT \
419                                 | BATL_GUARDEDSTORAGE)
420 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
421
422 #define CONFIG_SYS_IBAT3L       (0)
423 #define CONFIG_SYS_IBAT3U       (0)
424 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
425 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
426
427 /* Stack in dcache: cacheable, no memory coherence */
428 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
429 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR \
430                                 | BATU_BL_128K \
431                                 | BATU_VS \
432                                 | BATU_VP)
433 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
434 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
435
436 #ifdef CONFIG_PCI
437 /* PCI MEM space: cacheable */
438 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_MEM_PHYS \
439                                 | BATL_PP_RW \
440                                 | BATL_MEMCOHERENCE)
441 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_MEM_PHYS \
442                                 | BATU_BL_256M \
443                                 | BATU_VS \
444                                 | BATU_VP)
445 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
446 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
447 /* PCI MMIO space: cache-inhibit and guarded */
448 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MMIO_PHYS \
449                                 | BATL_PP_RW \
450                                 | BATL_CACHEINHIBIT \
451                                 | BATL_GUARDEDSTORAGE)
452 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MMIO_PHYS \
453                                 | BATU_BL_256M \
454                                 | BATU_VS \
455                                 | BATU_VP)
456 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
457 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
458 #else
459 #define CONFIG_SYS_IBAT5L       (0)
460 #define CONFIG_SYS_IBAT5U       (0)
461 #define CONFIG_SYS_IBAT6L       (0)
462 #define CONFIG_SYS_IBAT6U       (0)
463 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
464 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
465 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
466 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
467 #endif
468
469 /* Nothing in BAT7 */
470 #define CONFIG_SYS_IBAT7L       (0)
471 #define CONFIG_SYS_IBAT7U       (0)
472 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
473 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
474
475 #if (CONFIG_CMD_KGDB)
476 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
477 #endif
478
479 /*
480  * Environment Configuration
481  */
482 #define CONFIG_ENV_OVERWRITE
483
484 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
485 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
486
487 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
488  * (see CONFIG_SYS_I2C_EEPROM) */
489                                         /* MAC address offset in I2C EEPROM */
490 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
491
492 #define CONFIG_NETDEV           "eth1"
493
494 #define CONFIG_HOSTNAME         mpc8323erdb
495 #define CONFIG_ROOTPATH         "/nfsroot"
496 #define CONFIG_BOOTFILE         "uImage"
497                                 /* U-Boot image on TFTP server */
498 #define CONFIG_UBOOTPATH        "u-boot.bin"
499 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
500 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
501
502                                 /* default location for tftp and bootm */
503 #define CONFIG_LOADADDR         800000
504 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
505 #define CONFIG_BAUDRATE         115200
506
507 #define CONFIG_EXTRA_ENV_SETTINGS \
508         "netdev=" CONFIG_NETDEV "\0"                                    \
509         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
510         "tftpflash=tftp $loadaddr $uboot;"                              \
511                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
512                         " +$filesize; " \
513                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
514                         " +$filesize; " \
515                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
516                         " $filesize; "  \
517                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
518                         " +$filesize; " \
519                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
520                         " $filesize\0"  \
521         "fdtaddr=780000\0"                                              \
522         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
523         "ramdiskaddr=1000000\0"                                         \
524         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
525         "console=ttyS0\0"                                               \
526         "setbootargs=setenv bootargs "                                  \
527                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
528         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
529                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
530                                                                 "$netdev:off "\
531                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
532
533 #define CONFIG_NFSBOOTCOMMAND                                           \
534         "setenv rootdev /dev/nfs;"                                      \
535         "run setbootargs;"                                              \
536         "run setipargs;"                                                \
537         "tftp $loadaddr $bootfile;"                                     \
538         "tftp $fdtaddr $fdtfile;"                                       \
539         "bootm $loadaddr - $fdtaddr"
540
541 #define CONFIG_RAMBOOTCOMMAND                                           \
542         "setenv rootdev /dev/ram;"                                      \
543         "run setbootargs;"                                              \
544         "tftp $ramdiskaddr $ramdiskfile;"                               \
545         "tftp $loadaddr $bootfile;"                                     \
546         "tftp $fdtaddr $fdtfile;"                                       \
547         "bootm $loadaddr $ramdiskaddr $fdtaddr"
548
549 #endif  /* __CONFIG_H */