include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
  18
  19 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  20
  21 /*
  22  * System Clock Setup
  23  */
  24 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  25
  26 #ifndef CONFIG_SYS_CLK_FREQ
  27 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  28 #endif
  29
  30 /*
  31  * Hardware Reset Configuration Word
  32  */
  33 #define CONFIG_SYS_HRCW_LOW (\
  34         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  35         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  36         HRCWL_VCO_1X2 |\
  37         HRCWL_CSB_TO_CLKIN_2X1 |\
  38         HRCWL_CORE_TO_CSB_2_5X1 |\
  39         HRCWL_CE_PLL_VCO_DIV_2 |\
  40         HRCWL_CE_PLL_DIV_1X1 |\
  41         HRCWL_CE_TO_PLL_1X3)
  42
  43 #define CONFIG_SYS_HRCW_HIGH (\
  44         HRCWH_PCI_HOST |\
  45         HRCWH_PCI1_ARBITER_ENABLE |\
  46         HRCWH_CORE_ENABLE |\
  47         HRCWH_FROM_0X00000100 |\
  48         HRCWH_BOOTSEQ_DISABLE |\
  49         HRCWH_SW_WATCHDOG_DISABLE |\
  50         HRCWH_ROM_LOC_LOCAL_16BIT |\
  51         HRCWH_BIG_ENDIAN |\
  52         HRCWH_LALE_NORMAL)
  53
  54 /*
  55  * System IO Config
  56  */
  57 #define CONFIG_SYS_SICRL                0x00000000
  58
  59 /*
  60  * IMMR new address
  61  */
  62 #define CONFIG_SYS_IMMR         0xE0000000
  63
  64 /*
  65  * System performance
  66  */
  67 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  68 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  69 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  70 #define CONFIG_SYS_SPCR_OPT     1
  71
  72 /*
  73  * DDR Setup
  74  */
  75 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  76 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  77 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  78
  79 #undef CONFIG_SPD_EEPROM
  80 #if defined(CONFIG_SPD_EEPROM)
  81 /* Determine DDR configuration from I2C interface
  82  */
  83 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  84 #else
  85 /* Manually set up DDR parameters
  86  */
  87 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  88 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  89                                 | CSCONFIG_ROW_BIT_13 \
  90                                 | CSCONFIG_COL_BIT_9)
  91                                 /* 0x80010101 */
  92 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  93                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  94                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  95                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  96                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  97                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  98                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  99                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 100                                 /* 0x00220802 */
 101 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 102                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 103                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 104                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 105                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
 106                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 107                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 108                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 109                                 /* 0x26253222 */
 110 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 111                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 112                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 113                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 114                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 115                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 116                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
 117                                 /* 0x1f9048c7 */
 118 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 119 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 120                                 /* 0x02000000 */
 121 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 122                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 123                                 /* 0x44480232 */
 124 #define CONFIG_SYS_DDR_MODE2    0x8000c000
 125 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 126                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 127                                 /* 0x03200064 */
 128 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
 129 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 130                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 131                                 | SDRAM_CFG_32_BE)
 132                                 /* 0x43080000 */
 133 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 134 #endif
 135
 136 /*
 137  * Memory test
 138  */
 139 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 140 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 141 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 142
 143 /*
 144  * The reserved memory
 145  */
 146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 147
 148 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 149 #define CONFIG_SYS_RAMBOOT
 150 #else
 151 #undef  CONFIG_SYS_RAMBOOT
 152 #endif
 153
 154 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 155 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 156 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 157
 158 /*
 159  * Initial RAM Base Address Setup
 160  */
 161 #define CONFIG_SYS_INIT_RAM_LOCK        1
 162 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 163 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 164 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 165                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 166
 167 /*
 168  * Local Bus Configuration & Clock Setup
 169  */
 170 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 171 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 172 #define CONFIG_SYS_LBC_LBCR             0x00000000
 173
 174 /*
 175  * FLASH on the Local Bus
 176  */
 177 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 178 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 179 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 180 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 181 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 182
 183                                         /* Window base at flash base */
 184 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 185 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 186
 187 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 188                                 | BR_PS_16      /* 16 bit port */ \
 189                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 190                                 | BR_V)         /* valid */
 191 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 192                                 | OR_GPCM_XAM \
 193                                 | OR_GPCM_CSNT \
 194                                 | OR_GPCM_ACS_DIV2 \
 195                                 | OR_GPCM_XACS \
 196                                 | OR_GPCM_SCY_15 \
 197                                 | OR_GPCM_TRLX_SET \
 198                                 | OR_GPCM_EHTR_SET \
 199                                 | OR_GPCM_EAD)
 200                                 /* 0xFE006FF7 */
 201
 202 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 203 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 204
 205 #undef CONFIG_SYS_FLASH_CHECKSUM
 206
 207 /*
 208  * Serial Port
 209  */
 210 #define CONFIG_CONS_INDEX       1
 211 #define CONFIG_SYS_NS16550_SERIAL
 212 #define CONFIG_SYS_NS16550_REG_SIZE     1
 213 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 214
 215 #define CONFIG_SYS_BAUDRATE_TABLE  \
 216                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 217
 218 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 219 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 220
 221 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 222 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 223
 224 /* I2C */
 225 #define CONFIG_SYS_I2C
 226 #define CONFIG_SYS_I2C_FSL
 227 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 228 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 229 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 230 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 231
 232 /*
 233  * Config on-board EEPROM
 234  */
 235 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 236 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 239
 240 /*
 241  * General PCI
 242  * Addresses are mapped 1-1.
 243  */
 244 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 245 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 246 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 247 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 248 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 249 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 250 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 251 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 252 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 253
 254 #ifdef CONFIG_PCI
 255 #define CONFIG_PCI_INDIRECT_BRIDGE
 256 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 257
 258 #undef CONFIG_EEPRO100
 259 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 260 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 261
 262 #endif  /* CONFIG_PCI */
 263
 264 /*
 265  * QE UEC ethernet configuration
 266  */
 267 #define CONFIG_UEC_ETH
 268 #define CONFIG_ETHPRIME         "UEC0"
 269
 270 #define CONFIG_UEC_ETH1         /* ETH3 */
 271
 272 #ifdef CONFIG_UEC_ETH1
 273 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 274 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 275 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 276 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 277 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 278 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 279 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 280 #endif
 281
 282 #define CONFIG_UEC_ETH2         /* ETH4 */
 283
 284 #ifdef CONFIG_UEC_ETH2
 285 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 286 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 287 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 288 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 289 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 290 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 291 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 292 #endif
 293
 294 /*
 295  * Environment
 296  */
 297 #ifndef CONFIG_SYS_RAMBOOT
 298         #define CONFIG_ENV_IS_IN_FLASH  1
 299         #define CONFIG_ENV_ADDR         \
 300                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 301         #define CONFIG_ENV_SECT_SIZE    0x20000
 302         #define CONFIG_ENV_SIZE         0x2000
 303 #else
 304         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 305         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 306         #define CONFIG_ENV_SIZE         0x2000
 307 #endif
 308
 309 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 310 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 311
 312 /*
 313  * BOOTP options
 314  */
 315 #define CONFIG_BOOTP_BOOTFILESIZE
 316 #define CONFIG_BOOTP_BOOTPATH
 317 #define CONFIG_BOOTP_GATEWAY
 318 #define CONFIG_BOOTP_HOSTNAME
 319
 320 /*
 321  * Command line configuration.
 322  */
 323 #define CONFIG_CMD_EEPROM
 324
 325 #if defined(CONFIG_PCI)
 326         #define CONFIG_CMD_PCI
 327 #endif
 328
 329 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 330
 331 /*
 332  * Miscellaneous configurable options
 333  */
 334 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 335 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 336
 337 #if (CONFIG_CMD_KGDB)
 338         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 339 #else
 340         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 341 #endif
 342
 343                                 /* Print Buffer Size */
 344 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 345 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 346                                 /* Boot Argument Buffer Size */
 347 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 348
 349 /*
 350  * For booting Linux, the board info and command line data
 351  * have to be in the first 256 MB of memory, since this is
 352  * the maximum mapped by the Linux kernel during initialization.
 353  */
 354                                         /* Initial Memory map for Linux */
 355 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 356 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 357
 358 /*
 359  * Core HID Setup
 360  */
 361 #define CONFIG_SYS_HID0_INIT    0x000000000
 362 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 363                                  HID0_ENABLE_INSTRUCTION_CACHE)
 364 #define CONFIG_SYS_HID2         HID2_HBE
 365
 366 /*
 367  * MMU Setup
 368  */
 369 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 370
 371 /* DDR: cache cacheable */
 372 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 373                                 | BATL_PP_RW \
 374                                 | BATL_MEMCOHERENCE)
 375 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 376                                 | BATU_BL_256M \
 377                                 | BATU_VS \
 378                                 | BATU_VP)
 379 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 380 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 381
 382 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 383 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 384                                 | BATL_PP_RW \
 385                                 | BATL_CACHEINHIBIT \
 386                                 | BATL_GUARDEDSTORAGE)
 387 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 388                                 | BATU_BL_4M \
 389                                 | BATU_VS \
 390                                 | BATU_VP)
 391 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 392 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 393
 394 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 395 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 396                                 | BATL_PP_RW \
 397                                 | BATL_MEMCOHERENCE)
 398 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 399                                 | BATU_BL_32M \
 400                                 | BATU_VS \
 401                                 | BATU_VP)
 402 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 403                                 | BATL_PP_RW \
 404                                 | BATL_CACHEINHIBIT \
 405                                 | BATL_GUARDEDSTORAGE)
 406 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 407
 408 #define CONFIG_SYS_IBAT3L       (0)
 409 #define CONFIG_SYS_IBAT3U       (0)
 410 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 411 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 412
 413 /* Stack in dcache: cacheable, no memory coherence */
 414 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 415 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR \
 416                                 | BATU_BL_128K \
 417                                 | BATU_VS \
 418                                 | BATU_VP)
 419 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 420 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 421
 422 #ifdef CONFIG_PCI
 423 /* PCI MEM space: cacheable */
 424 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_MEM_PHYS \
 425                                 | BATL_PP_RW \
 426                                 | BATL_MEMCOHERENCE)
 427 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_MEM_PHYS \
 428                                 | BATU_BL_256M \
 429                                 | BATU_VS \
 430                                 | BATU_VP)
 431 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 432 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 433 /* PCI MMIO space: cache-inhibit and guarded */
 434 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 435                                 | BATL_PP_RW \
 436                                 | BATL_CACHEINHIBIT \
 437                                 | BATL_GUARDEDSTORAGE)
 438 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 439                                 | BATU_BL_256M \
 440                                 | BATU_VS \
 441                                 | BATU_VP)
 442 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 443 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 444 #else
 445 #define CONFIG_SYS_IBAT5L       (0)
 446 #define CONFIG_SYS_IBAT5U       (0)
 447 #define CONFIG_SYS_IBAT6L       (0)
 448 #define CONFIG_SYS_IBAT6U       (0)
 449 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 450 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 451 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 452 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 453 #endif
 454
 455 /* Nothing in BAT7 */
 456 #define CONFIG_SYS_IBAT7L       (0)
 457 #define CONFIG_SYS_IBAT7U       (0)
 458 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 459 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 460
 461 #if (CONFIG_CMD_KGDB)
 462 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 463 #endif
 464
 465 /*
 466  * Environment Configuration
 467  */
 468 #define CONFIG_ENV_OVERWRITE
 469
 470 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 471 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 472
 473 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 474  * (see CONFIG_SYS_I2C_EEPROM) */
 475                                         /* MAC address offset in I2C EEPROM */
 476 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 477
 478 #define CONFIG_NETDEV           "eth1"
 479
 480 #define CONFIG_HOSTNAME         mpc8323erdb
 481 #define CONFIG_ROOTPATH         "/nfsroot"
 482 #define CONFIG_BOOTFILE         "uImage"
 483                                 /* U-Boot image on TFTP server */
 484 #define CONFIG_UBOOTPATH        "u-boot.bin"
 485 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 486 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 487
 488                                 /* default location for tftp and bootm */
 489 #define CONFIG_LOADADDR         800000
 490
 491 #define CONFIG_EXTRA_ENV_SETTINGS \
 492         "netdev=" CONFIG_NETDEV "\0"                                    \
 493         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 494         "tftpflash=tftp $loadaddr $uboot;"                              \
 495                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 496                         " +$filesize; " \
 497                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 498                         " +$filesize; " \
 499                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 500                         " $filesize; "  \
 501                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 502                         " +$filesize; " \
 503                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 504                         " $filesize\0"  \
 505         "fdtaddr=780000\0"                                              \
 506         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 507         "ramdiskaddr=1000000\0"                                         \
 508         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 509         "console=ttyS0\0"                                               \
 510         "setbootargs=setenv bootargs "                                  \
 511                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 512         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 513                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 514                                                                 "$netdev:off "\
 515                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 516
 517 #define CONFIG_NFSBOOTCOMMAND                                           \
 518         "setenv rootdev /dev/nfs;"                                      \
 519         "run setbootargs;"                                              \
 520         "run setipargs;"                                                \
 521         "tftp $loadaddr $bootfile;"                                     \
 522         "tftp $fdtaddr $fdtfile;"                                       \
 523         "bootm $loadaddr - $fdtaddr"
 524
 525 #define CONFIG_RAMBOOTCOMMAND                                           \
 526         "setenv rootdev /dev/ram;"                                      \
 527         "run setbootargs;"                                              \
 528         "tftp $ramdiskaddr $ramdiskfile;"                               \
 529         "tftp $loadaddr $bootfile;"                                     \
 530         "tftp $fdtaddr $fdtfile;"                                       \
 531         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 532
 533 #endif  /* __CONFIG_H */