include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17
  18 /*
  19  * System IO Config
  20  */
  21 #define CONFIG_SYS_SICRL                0x00000000
  22
  23 /*
  24  * IMMR new address
  25  */
  26 #define CONFIG_SYS_IMMR         0xE0000000
  27
  28 /*
  29  * System performance
  30  */
  31 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  32 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  33 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  34 #define CONFIG_SYS_SPCR_OPT     1
  35
  36 /*
  37  * DDR Setup
  38  */
  39 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  40 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  41 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  42
  43 #undef CONFIG_SPD_EEPROM
  44 #if defined(CONFIG_SPD_EEPROM)
  45 /* Determine DDR configuration from I2C interface
  46  */
  47 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  48 #else
  49 /* Manually set up DDR parameters
  50  */
  51 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  52 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  53                                 | CSCONFIG_ROW_BIT_13 \
  54                                 | CSCONFIG_COL_BIT_9)
  55                                 /* 0x80010101 */
  56 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  57                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  58                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  59                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  60                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  61                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  62                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  63                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  64                                 /* 0x00220802 */
  65 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  66                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  67                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  68                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  69                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
  70                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  71                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  72                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  73                                 /* 0x26253222 */
  74 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  75                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  76                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  77                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  78                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  79                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  80                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  81                                 /* 0x1f9048c7 */
  82 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  83 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  84                                 /* 0x02000000 */
  85 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  86                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  87                                 /* 0x44480232 */
  88 #define CONFIG_SYS_DDR_MODE2    0x8000c000
  89 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  90                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  91                                 /* 0x03200064 */
  92 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  93 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  94                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  95                                 | SDRAM_CFG_32_BE)
  96                                 /* 0x43080000 */
  97 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  98 #endif
  99
 100 /*
 101  * Memory test
 102  */
 103 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 104 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 105 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 106
 107 /*
 108  * The reserved memory
 109  */
 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 111
 112 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 113 #define CONFIG_SYS_RAMBOOT
 114 #else
 115 #undef  CONFIG_SYS_RAMBOOT
 116 #endif
 117
 118 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 119 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 120 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 121
 122 /*
 123  * Initial RAM Base Address Setup
 124  */
 125 #define CONFIG_SYS_INIT_RAM_LOCK        1
 126 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 127 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 128 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 129                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 130
 131 /*
 132  * Local Bus Configuration & Clock Setup
 133  */
 134 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 135 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 136 #define CONFIG_SYS_LBC_LBCR             0x00000000
 137
 138 /*
 139  * FLASH on the Local Bus
 140  */
 141 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 142 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 143
 144
 145
 146 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 147 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 148
 149 #undef CONFIG_SYS_FLASH_CHECKSUM
 150
 151 /*
 152  * Serial Port
 153  */
 154 #define CONFIG_SYS_NS16550_SERIAL
 155 #define CONFIG_SYS_NS16550_REG_SIZE     1
 156 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 157
 158 #define CONFIG_SYS_BAUDRATE_TABLE  \
 159                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 160
 161 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 162 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 163
 164 /* I2C */
 165 #define CONFIG_SYS_I2C
 166 #define CONFIG_SYS_I2C_FSL
 167 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 168 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 169 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 170 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 171
 172 /*
 173  * Config on-board EEPROM
 174  */
 175 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 176 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 177 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 178 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 179
 180 /*
 181  * General PCI
 182  * Addresses are mapped 1-1.
 183  */
 184 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 185 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 186 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 187 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 188 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 189 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 190 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 191 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 192 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 193
 194 #ifdef CONFIG_PCI
 195 #define CONFIG_PCI_INDIRECT_BRIDGE
 196 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 197
 198 #undef CONFIG_EEPRO100
 199 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 200 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 201
 202 #endif  /* CONFIG_PCI */
 203
 204 /*
 205  * QE UEC ethernet configuration
 206  */
 207 #define CONFIG_UEC_ETH
 208 #define CONFIG_ETHPRIME         "UEC0"
 209
 210 #define CONFIG_UEC_ETH1         /* ETH3 */
 211
 212 #ifdef CONFIG_UEC_ETH1
 213 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 214 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 215 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 216 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 217 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 218 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 219 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 220 #endif
 221
 222 #define CONFIG_UEC_ETH2         /* ETH4 */
 223
 224 #ifdef CONFIG_UEC_ETH2
 225 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 226 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 227 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 228 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 229 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 230 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 231 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 232 #endif
 233
 234 /*
 235  * Environment
 236  */
 237 #ifndef CONFIG_SYS_RAMBOOT
 238         #define CONFIG_ENV_ADDR         \
 239                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 240         #define CONFIG_ENV_SECT_SIZE    0x20000
 241         #define CONFIG_ENV_SIZE         0x2000
 242 #else
 243         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 244         #define CONFIG_ENV_SIZE         0x2000
 245 #endif
 246
 247 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 248 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 249
 250 /*
 251  * BOOTP options
 252  */
 253 #define CONFIG_BOOTP_BOOTFILESIZE
 254
 255 /*
 256  * Command line configuration.
 257  */
 258
 259 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 260
 261 /*
 262  * Miscellaneous configurable options
 263  */
 264 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 265
 266 /*
 267  * For booting Linux, the board info and command line data
 268  * have to be in the first 256 MB of memory, since this is
 269  * the maximum mapped by the Linux kernel during initialization.
 270  */
 271                                         /* Initial Memory map for Linux */
 272 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 273 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 274
 275 /*
 276  * Core HID Setup
 277  */
 278 #define CONFIG_SYS_HID0_INIT    0x000000000
 279 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 280                                  HID0_ENABLE_INSTRUCTION_CACHE)
 281 #define CONFIG_SYS_HID2         HID2_HBE
 282
 283 #if (CONFIG_CMD_KGDB)
 284 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 285 #endif
 286
 287 /*
 288  * Environment Configuration
 289  */
 290 #define CONFIG_ENV_OVERWRITE
 291
 292 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 293 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 294
 295 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 296  * (see CONFIG_SYS_I2C_EEPROM) */
 297                                         /* MAC address offset in I2C EEPROM */
 298 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 299
 300 #define CONFIG_NETDEV           "eth1"
 301
 302 #define CONFIG_HOSTNAME         "mpc8323erdb"
 303 #define CONFIG_ROOTPATH         "/nfsroot"
 304 #define CONFIG_BOOTFILE         "uImage"
 305                                 /* U-Boot image on TFTP server */
 306 #define CONFIG_UBOOTPATH        "u-boot.bin"
 307 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 308 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 309
 310                                 /* default location for tftp and bootm */
 311 #define CONFIG_LOADADDR         800000
 312
 313 #define CONFIG_EXTRA_ENV_SETTINGS \
 314         "netdev=" CONFIG_NETDEV "\0"                                    \
 315         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 316         "tftpflash=tftp $loadaddr $uboot;"                              \
 317                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 318                         " +$filesize; " \
 319                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 320                         " +$filesize; " \
 321                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 322                         " $filesize; "  \
 323                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 324                         " +$filesize; " \
 325                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 326                         " $filesize\0"  \
 327         "fdtaddr=780000\0"                                              \
 328         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 329         "ramdiskaddr=1000000\0"                                         \
 330         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 331         "console=ttyS0\0"                                               \
 332         "setbootargs=setenv bootargs "                                  \
 333                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 334         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 335                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 336                                                                 "$netdev:off "\
 337                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 338
 339 #define CONFIG_NFSBOOTCOMMAND                                           \
 340         "setenv rootdev /dev/nfs;"                                      \
 341         "run setbootargs;"                                              \
 342         "run setipargs;"                                                \
 343         "tftp $loadaddr $bootfile;"                                     \
 344         "tftp $fdtaddr $fdtfile;"                                       \
 345         "bootm $loadaddr - $fdtaddr"
 346
 347 #define CONFIG_RAMBOOTCOMMAND                                           \
 348         "setenv rootdev /dev/ram;"                                      \
 349         "run setbootargs;"                                              \
 350         "tftp $ramdiskaddr $ramdiskfile;"                               \
 351         "tftp $loadaddr $bootfile;"                                     \
 352         "tftp $fdtaddr $fdtfile;"                                       \
 353         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 354
 355 #endif  /* __CONFIG_H */