include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17
  18 /*
  19  * System Clock Setup
  20  */
  21 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  22
  23 #ifndef CONFIG_SYS_CLK_FREQ
  24 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  25 #endif
  26
  27 /*
  28  * Hardware Reset Configuration Word
  29  */
  30 #define CONFIG_SYS_HRCW_LOW (\
  31         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  32         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  33         HRCWL_VCO_1X2 |\
  34         HRCWL_CSB_TO_CLKIN_2X1 |\
  35         HRCWL_CORE_TO_CSB_2_5X1 |\
  36         HRCWL_CE_PLL_VCO_DIV_2 |\
  37         HRCWL_CE_PLL_DIV_1X1 |\
  38         HRCWL_CE_TO_PLL_1X3)
  39
  40 #define CONFIG_SYS_HRCW_HIGH (\
  41         HRCWH_PCI_HOST |\
  42         HRCWH_PCI1_ARBITER_ENABLE |\
  43         HRCWH_CORE_ENABLE |\
  44         HRCWH_FROM_0X00000100 |\
  45         HRCWH_BOOTSEQ_DISABLE |\
  46         HRCWH_SW_WATCHDOG_DISABLE |\
  47         HRCWH_ROM_LOC_LOCAL_16BIT |\
  48         HRCWH_BIG_ENDIAN |\
  49         HRCWH_LALE_NORMAL)
  50
  51 /*
  52  * System IO Config
  53  */
  54 #define CONFIG_SYS_SICRL                0x00000000
  55
  56 /*
  57  * IMMR new address
  58  */
  59 #define CONFIG_SYS_IMMR         0xE0000000
  60
  61 /*
  62  * System performance
  63  */
  64 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  65 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  66 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  67 #define CONFIG_SYS_SPCR_OPT     1
  68
  69 /*
  70  * DDR Setup
  71  */
  72 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  73 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  74 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  75
  76 #undef CONFIG_SPD_EEPROM
  77 #if defined(CONFIG_SPD_EEPROM)
  78 /* Determine DDR configuration from I2C interface
  79  */
  80 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  81 #else
  82 /* Manually set up DDR parameters
  83  */
  84 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  85 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  86                                 | CSCONFIG_ROW_BIT_13 \
  87                                 | CSCONFIG_COL_BIT_9)
  88                                 /* 0x80010101 */
  89 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  90                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  91                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  92                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  93                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  94                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  95                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  96                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  97                                 /* 0x00220802 */
  98 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  99                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 100                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 101                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 102                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
 103                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 104                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 105                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 106                                 /* 0x26253222 */
 107 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 108                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 109                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 110                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 111                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 112                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 113                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
 114                                 /* 0x1f9048c7 */
 115 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 116 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 117                                 /* 0x02000000 */
 118 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 119                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 120                                 /* 0x44480232 */
 121 #define CONFIG_SYS_DDR_MODE2    0x8000c000
 122 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 123                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 124                                 /* 0x03200064 */
 125 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
 126 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 127                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 128                                 | SDRAM_CFG_32_BE)
 129                                 /* 0x43080000 */
 130 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 131 #endif
 132
 133 /*
 134  * Memory test
 135  */
 136 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 137 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 138 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 139
 140 /*
 141  * The reserved memory
 142  */
 143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 144
 145 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 146 #define CONFIG_SYS_RAMBOOT
 147 #else
 148 #undef  CONFIG_SYS_RAMBOOT
 149 #endif
 150
 151 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 152 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 153 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 154
 155 /*
 156  * Initial RAM Base Address Setup
 157  */
 158 #define CONFIG_SYS_INIT_RAM_LOCK        1
 159 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 160 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 161 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 162                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 163
 164 /*
 165  * Local Bus Configuration & Clock Setup
 166  */
 167 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 168 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 169 #define CONFIG_SYS_LBC_LBCR             0x00000000
 170
 171 /*
 172  * FLASH on the Local Bus
 173  */
 174 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 175 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 176
 177                                         /* Window base at flash base */
 178 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 179 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 180
 181 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 182                                 | BR_PS_16      /* 16 bit port */ \
 183                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 184                                 | BR_V)         /* valid */
 185 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 186                                 | OR_GPCM_XAM \
 187                                 | OR_GPCM_CSNT \
 188                                 | OR_GPCM_ACS_DIV2 \
 189                                 | OR_GPCM_XACS \
 190                                 | OR_GPCM_SCY_15 \
 191                                 | OR_GPCM_TRLX_SET \
 192                                 | OR_GPCM_EHTR_SET \
 193                                 | OR_GPCM_EAD)
 194                                 /* 0xFE006FF7 */
 195
 196 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 197 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 198
 199 #undef CONFIG_SYS_FLASH_CHECKSUM
 200
 201 /*
 202  * Serial Port
 203  */
 204 #define CONFIG_SYS_NS16550_SERIAL
 205 #define CONFIG_SYS_NS16550_REG_SIZE     1
 206 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 207
 208 #define CONFIG_SYS_BAUDRATE_TABLE  \
 209                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 210
 211 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 212 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 213
 214 /* I2C */
 215 #define CONFIG_SYS_I2C
 216 #define CONFIG_SYS_I2C_FSL
 217 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 218 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 219 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 220 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 221
 222 /*
 223  * Config on-board EEPROM
 224  */
 225 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 226 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 229
 230 /*
 231  * General PCI
 232  * Addresses are mapped 1-1.
 233  */
 234 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 235 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 236 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 237 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 238 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 239 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 240 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 241 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 242 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 243
 244 #ifdef CONFIG_PCI
 245 #define CONFIG_PCI_INDIRECT_BRIDGE
 246 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 247
 248 #undef CONFIG_EEPRO100
 249 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 250 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 251
 252 #endif  /* CONFIG_PCI */
 253
 254 /*
 255  * QE UEC ethernet configuration
 256  */
 257 #define CONFIG_UEC_ETH
 258 #define CONFIG_ETHPRIME         "UEC0"
 259
 260 #define CONFIG_UEC_ETH1         /* ETH3 */
 261
 262 #ifdef CONFIG_UEC_ETH1
 263 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 264 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 265 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 266 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 267 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 268 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 269 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 270 #endif
 271
 272 #define CONFIG_UEC_ETH2         /* ETH4 */
 273
 274 #ifdef CONFIG_UEC_ETH2
 275 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 276 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 277 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 278 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 279 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 280 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 281 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 282 #endif
 283
 284 /*
 285  * Environment
 286  */
 287 #ifndef CONFIG_SYS_RAMBOOT
 288         #define CONFIG_ENV_ADDR         \
 289                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 290         #define CONFIG_ENV_SECT_SIZE    0x20000
 291         #define CONFIG_ENV_SIZE         0x2000
 292 #else
 293         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 294         #define CONFIG_ENV_SIZE         0x2000
 295 #endif
 296
 297 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 298 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 299
 300 /*
 301  * BOOTP options
 302  */
 303 #define CONFIG_BOOTP_BOOTFILESIZE
 304
 305 /*
 306  * Command line configuration.
 307  */
 308
 309 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 310
 311 /*
 312  * Miscellaneous configurable options
 313  */
 314 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 315
 316 /*
 317  * For booting Linux, the board info and command line data
 318  * have to be in the first 256 MB of memory, since this is
 319  * the maximum mapped by the Linux kernel during initialization.
 320  */
 321                                         /* Initial Memory map for Linux */
 322 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 323 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 324
 325 /*
 326  * Core HID Setup
 327  */
 328 #define CONFIG_SYS_HID0_INIT    0x000000000
 329 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 330                                  HID0_ENABLE_INSTRUCTION_CACHE)
 331 #define CONFIG_SYS_HID2         HID2_HBE
 332
 333 /*
 334  * MMU Setup
 335  */
 336 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 337
 338 /* DDR: cache cacheable */
 339 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 340                                 | BATL_PP_RW \
 341                                 | BATL_MEMCOHERENCE)
 342 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 343                                 | BATU_BL_256M \
 344                                 | BATU_VS \
 345                                 | BATU_VP)
 346 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 347 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 348
 349 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 350 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 351                                 | BATL_PP_RW \
 352                                 | BATL_CACHEINHIBIT \
 353                                 | BATL_GUARDEDSTORAGE)
 354 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 355                                 | BATU_BL_4M \
 356                                 | BATU_VS \
 357                                 | BATU_VP)
 358 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 359 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 360
 361 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 362 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 363                                 | BATL_PP_RW \
 364                                 | BATL_MEMCOHERENCE)
 365 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 366                                 | BATU_BL_32M \
 367                                 | BATU_VS \
 368                                 | BATU_VP)
 369 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 370                                 | BATL_PP_RW \
 371                                 | BATL_CACHEINHIBIT \
 372                                 | BATL_GUARDEDSTORAGE)
 373 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 374
 375 #define CONFIG_SYS_IBAT3L       (0)
 376 #define CONFIG_SYS_IBAT3U       (0)
 377 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 378 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 379
 380 /* Stack in dcache: cacheable, no memory coherence */
 381 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 382 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR \
 383                                 | BATU_BL_128K \
 384                                 | BATU_VS \
 385                                 | BATU_VP)
 386 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 387 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 388
 389 #ifdef CONFIG_PCI
 390 /* PCI MEM space: cacheable */
 391 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_MEM_PHYS \
 392                                 | BATL_PP_RW \
 393                                 | BATL_MEMCOHERENCE)
 394 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_MEM_PHYS \
 395                                 | BATU_BL_256M \
 396                                 | BATU_VS \
 397                                 | BATU_VP)
 398 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 399 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 400 /* PCI MMIO space: cache-inhibit and guarded */
 401 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 402                                 | BATL_PP_RW \
 403                                 | BATL_CACHEINHIBIT \
 404                                 | BATL_GUARDEDSTORAGE)
 405 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 406                                 | BATU_BL_256M \
 407                                 | BATU_VS \
 408                                 | BATU_VP)
 409 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 410 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 411 #else
 412 #define CONFIG_SYS_IBAT5L       (0)
 413 #define CONFIG_SYS_IBAT5U       (0)
 414 #define CONFIG_SYS_IBAT6L       (0)
 415 #define CONFIG_SYS_IBAT6U       (0)
 416 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 417 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 418 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 419 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 420 #endif
 421
 422 /* Nothing in BAT7 */
 423 #define CONFIG_SYS_IBAT7L       (0)
 424 #define CONFIG_SYS_IBAT7U       (0)
 425 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 426 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 427
 428 #if (CONFIG_CMD_KGDB)
 429 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 430 #endif
 431
 432 /*
 433  * Environment Configuration
 434  */
 435 #define CONFIG_ENV_OVERWRITE
 436
 437 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 438 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 439
 440 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 441  * (see CONFIG_SYS_I2C_EEPROM) */
 442                                         /* MAC address offset in I2C EEPROM */
 443 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 444
 445 #define CONFIG_NETDEV           "eth1"
 446
 447 #define CONFIG_HOSTNAME         "mpc8323erdb"
 448 #define CONFIG_ROOTPATH         "/nfsroot"
 449 #define CONFIG_BOOTFILE         "uImage"
 450                                 /* U-Boot image on TFTP server */
 451 #define CONFIG_UBOOTPATH        "u-boot.bin"
 452 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 453 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 454
 455                                 /* default location for tftp and bootm */
 456 #define CONFIG_LOADADDR         800000
 457
 458 #define CONFIG_EXTRA_ENV_SETTINGS \
 459         "netdev=" CONFIG_NETDEV "\0"                                    \
 460         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 461         "tftpflash=tftp $loadaddr $uboot;"                              \
 462                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 463                         " +$filesize; " \
 464                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 465                         " +$filesize; " \
 466                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 467                         " $filesize; "  \
 468                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 469                         " +$filesize; " \
 470                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 471                         " $filesize\0"  \
 472         "fdtaddr=780000\0"                                              \
 473         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 474         "ramdiskaddr=1000000\0"                                         \
 475         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 476         "console=ttyS0\0"                                               \
 477         "setbootargs=setenv bootargs "                                  \
 478                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 479         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 480                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 481                                                                 "$netdev:off "\
 482                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 483
 484 #define CONFIG_NFSBOOTCOMMAND                                           \
 485         "setenv rootdev /dev/nfs;"                                      \
 486         "run setbootargs;"                                              \
 487         "run setipargs;"                                                \
 488         "tftp $loadaddr $bootfile;"                                     \
 489         "tftp $fdtaddr $fdtfile;"                                       \
 490         "bootm $loadaddr - $fdtaddr"
 491
 492 #define CONFIG_RAMBOOTCOMMAND                                           \
 493         "setenv rootdev /dev/ram;"                                      \
 494         "run setbootargs;"                                              \
 495         "tftp $ramdiskaddr $ramdiskfile;"                               \
 496         "tftp $loadaddr $bootfile;"                                     \
 497         "tftp $fdtaddr $fdtfile;"                                       \
 498         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 499
 500 #endif  /* __CONFIG_H */