include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17
  18 /*
  19  * System IO Config
  20  */
  21 #define CONFIG_SYS_SICRL                0x00000000
  22
  23 /*
  24  * DDR Setup
  25  */
  26 #define CONFIG_SYS_SDRAM_BASE   0x00000000      /* DDR is system memory */
  27
  28 #undef CONFIG_SPD_EEPROM
  29 #if defined(CONFIG_SPD_EEPROM)
  30 /* Determine DDR configuration from I2C interface
  31  */
  32 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  33 #else
  34 /* Manually set up DDR parameters
  35  */
  36 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  37 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  38                                 | CSCONFIG_ROW_BIT_13 \
  39                                 | CSCONFIG_COL_BIT_9)
  40                                 /* 0x80010101 */
  41 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  42                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  43                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  44                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  45                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  46                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  47                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  48                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  49                                 /* 0x00220802 */
  50 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  51                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  52                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  53                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  54                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
  55                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  56                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  57                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  58                                 /* 0x26253222 */
  59 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  60                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  61                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  62                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  63                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  64                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  65                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  66                                 /* 0x1f9048c7 */
  67 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  68 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  69                                 /* 0x02000000 */
  70 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  71                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  72                                 /* 0x44480232 */
  73 #define CONFIG_SYS_DDR_MODE2    0x8000c000
  74 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  75                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  76                                 /* 0x03200064 */
  77 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  78 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  79                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  80                                 | SDRAM_CFG_32_BE)
  81                                 /* 0x43080000 */
  82 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  83 #endif
  84
  85 /*
  86  * Memory test
  87  */
  88 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  89 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
  90 #define CONFIG_SYS_MEMTEST_END          0x03f00000
  91
  92 /*
  93  * The reserved memory
  94  */
  95 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  96
  97 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  98 #define CONFIG_SYS_RAMBOOT
  99 #else
 100 #undef  CONFIG_SYS_RAMBOOT
 101 #endif
 102
 103 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 104 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 105 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 106
 107 /*
 108  * Initial RAM Base Address Setup
 109  */
 110 #define CONFIG_SYS_INIT_RAM_LOCK        1
 111 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 112 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 113 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 114                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 115
 116 /*
 117  * FLASH on the Local Bus
 118  */
 119 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 120 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 121
 122
 123
 124 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 125 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 126
 127 #undef CONFIG_SYS_FLASH_CHECKSUM
 128
 129 /*
 130  * Serial Port
 131  */
 132 #define CONFIG_SYS_NS16550_SERIAL
 133 #define CONFIG_SYS_NS16550_REG_SIZE     1
 134 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 135
 136 #define CONFIG_SYS_BAUDRATE_TABLE  \
 137                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 138
 139 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 140 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 141
 142 /* I2C */
 143 #define CONFIG_SYS_I2C
 144 #define CONFIG_SYS_I2C_FSL
 145 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 146 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 147 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 148 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 149
 150 /*
 151  * Config on-board EEPROM
 152  */
 153 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 157
 158 /*
 159  * General PCI
 160  * Addresses are mapped 1-1.
 161  */
 162 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 163 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 164 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 165 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 166 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 167 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 168 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 169 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 170 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 171
 172 #ifdef CONFIG_PCI
 173 #define CONFIG_PCI_INDIRECT_BRIDGE
 174 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 175
 176 #undef CONFIG_EEPRO100
 177 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 178 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 179
 180 #endif  /* CONFIG_PCI */
 181
 182 /*
 183  * QE UEC ethernet configuration
 184  */
 185 #define CONFIG_UEC_ETH
 186 #define CONFIG_ETHPRIME         "UEC0"
 187
 188 #define CONFIG_UEC_ETH1         /* ETH3 */
 189
 190 #ifdef CONFIG_UEC_ETH1
 191 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 192 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 193 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 194 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 195 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 196 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 197 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 198 #endif
 199
 200 #define CONFIG_UEC_ETH2         /* ETH4 */
 201
 202 #ifdef CONFIG_UEC_ETH2
 203 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 204 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 205 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 206 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 207 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 208 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 209 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 210 #endif
 211
 212 /*
 213  * Environment
 214  */
 215 #ifndef CONFIG_SYS_RAMBOOT
 216         #define CONFIG_ENV_ADDR         \
 217                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 218         #define CONFIG_ENV_SECT_SIZE    0x20000
 219         #define CONFIG_ENV_SIZE         0x2000
 220 #else
 221         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 222         #define CONFIG_ENV_SIZE         0x2000
 223 #endif
 224
 225 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 226 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 227
 228 /*
 229  * BOOTP options
 230  */
 231 #define CONFIG_BOOTP_BOOTFILESIZE
 232
 233 /*
 234  * Command line configuration.
 235  */
 236
 237 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 238
 239 /*
 240  * Miscellaneous configurable options
 241  */
 242 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 243
 244 /*
 245  * For booting Linux, the board info and command line data
 246  * have to be in the first 256 MB of memory, since this is
 247  * the maximum mapped by the Linux kernel during initialization.
 248  */
 249                                         /* Initial Memory map for Linux */
 250 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 251 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 252
 253 #if (CONFIG_CMD_KGDB)
 254 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 255 #endif
 256
 257 /*
 258  * Environment Configuration
 259  */
 260 #define CONFIG_ENV_OVERWRITE
 261
 262 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 263 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 264
 265 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 266  * (see CONFIG_SYS_I2C_EEPROM) */
 267                                         /* MAC address offset in I2C EEPROM */
 268 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 269
 270 #define CONFIG_NETDEV           "eth1"
 271
 272 #define CONFIG_HOSTNAME         "mpc8323erdb"
 273 #define CONFIG_ROOTPATH         "/nfsroot"
 274 #define CONFIG_BOOTFILE         "uImage"
 275                                 /* U-Boot image on TFTP server */
 276 #define CONFIG_UBOOTPATH        "u-boot.bin"
 277 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 278 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 279
 280                                 /* default location for tftp and bootm */
 281 #define CONFIG_LOADADDR         800000
 282
 283 #define CONFIG_EXTRA_ENV_SETTINGS \
 284         "netdev=" CONFIG_NETDEV "\0"                                    \
 285         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 286         "tftpflash=tftp $loadaddr $uboot;"                              \
 287                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 288                         " +$filesize; " \
 289                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 290                         " +$filesize; " \
 291                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 292                         " $filesize; "  \
 293                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 294                         " +$filesize; " \
 295                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 296                         " $filesize\0"  \
 297         "fdtaddr=780000\0"                                              \
 298         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 299         "ramdiskaddr=1000000\0"                                         \
 300         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 301         "console=ttyS0\0"                                               \
 302         "setbootargs=setenv bootargs "                                  \
 303                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 304         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 305                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 306                                                                 "$netdev:off "\
 307                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 308
 309 #define CONFIG_NFSBOOTCOMMAND                                           \
 310         "setenv rootdev /dev/nfs;"                                      \
 311         "run setbootargs;"                                              \
 312         "run setipargs;"                                                \
 313         "tftp $loadaddr $bootfile;"                                     \
 314         "tftp $fdtaddr $fdtfile;"                                       \
 315         "bootm $loadaddr - $fdtaddr"
 316
 317 #define CONFIG_RAMBOOTCOMMAND                                           \
 318         "setenv rootdev /dev/ram;"                                      \
 319         "run setbootargs;"                                              \
 320         "tftp $ramdiskaddr $ramdiskfile;"                               \
 321         "tftp $loadaddr $bootfile;"                                     \
 322         "tftp $fdtaddr $fdtfile;"                                       \
 323         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 324
 325 #endif  /* __CONFIG_H */