include/configs/MPC8315ERDB.h

   1 /*
   2  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  13 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  14 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  15 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  16 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  17
  18 #ifndef CONFIG_SYS_TEXT_BASE
  19 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  20 #endif
  21
  22 #ifndef CONFIG_SYS_MONITOR_BASE
  23 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  24 #endif
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_E300             1 /* E300 family */
  30 #define CONFIG_MPC831x          1 /* MPC831x CPU family */
  31 #define CONFIG_MPC8315          1 /* MPC8315 CPU specific */
  32 #define CONFIG_MPC8315ERDB      1 /* MPC8315ERDB board specific */
  33
  34 /*
  35  * System Clock Setup
  36  */
  37 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  38 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  39
  40 /*
  41  * Hardware Reset Configuration Word
  42  * if CLKIN is 66.66MHz, then
  43  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  44  */
  45 #define CONFIG_SYS_HRCW_LOW (\
  46         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  47         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  48         HRCWL_SVCOD_DIV_2 |\
  49         HRCWL_CSB_TO_CLKIN_2X1 |\
  50         HRCWL_CORE_TO_CSB_3X1)
  51 #define CONFIG_SYS_HRCW_HIGH_BASE (\
  52         HRCWH_PCI_HOST |\
  53         HRCWH_PCI1_ARBITER_ENABLE |\
  54         HRCWH_CORE_ENABLE |\
  55         HRCWH_BOOTSEQ_DISABLE |\
  56         HRCWH_SW_WATCHDOG_DISABLE |\
  57         HRCWH_TSEC1M_IN_RGMII |\
  58         HRCWH_TSEC2M_IN_RGMII |\
  59         HRCWH_BIG_ENDIAN |\
  60         HRCWH_LALE_NORMAL)
  61
  62 #ifdef CONFIG_NAND_SPL
  63 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  64                        HRCWH_FROM_0XFFF00100 |\
  65                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
  66                        HRCWH_RL_EXT_NAND)
  67 #else
  68 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  69                        HRCWH_FROM_0X00000100 |\
  70                        HRCWH_ROM_LOC_LOCAL_16BIT |\
  71                        HRCWH_RL_EXT_LEGACY)
  72 #endif
  73
  74 /*
  75  * System IO Config
  76  */
  77 #define CONFIG_SYS_SICRH                0x00000000
  78 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  79
  80 #define CONFIG_HWCONFIG
  81
  82 /*
  83  * IMMR new address
  84  */
  85 #define CONFIG_SYS_IMMR         0xE0000000
  86
  87 /*
  88  * Arbiter Setup
  89  */
  90 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  91 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  92 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  93
  94 /*
  95  * DDR Setup
  96  */
  97 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  98 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  99 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 100 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 101 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 102                                 | DDRCDR_PZ_LOZ \
 103                                 | DDRCDR_NZ_LOZ \
 104                                 | DDRCDR_ODT \
 105                                 | DDRCDR_Q_DRN)
 106                                 /* 0x7b880001 */
 107 /*
 108  * Manually set up DDR parameters
 109  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 110  */
 111 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 112 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 113 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 114                                 | CSCONFIG_ODT_RD_NEVER \
 115                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 116                                 | CSCONFIG_ROW_BIT_13 \
 117                                 | CSCONFIG_COL_BIT_10)
 118                                 /* 0x80010102 */
 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 120 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 121                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 122                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 123                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 124                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 125                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 126                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 127                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 128                                 /* 0x00220802 */
 129 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 130                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 131                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 132                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 133                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 134                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 135                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 136                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 137                                 /* 0x27256222 */
 138 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 139                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 140                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 141                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 142                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 143                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 144                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 145                                 /* 0x121048c5 */
 146 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 147                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 148                                 /* 0x03600100 */
 149 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 150                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 151                                 | SDRAM_CFG_DBW_32)
 152                                 /* 0x43080000 */
 153 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 154 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 155                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 156                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 157 #define CONFIG_SYS_DDR_MODE2    0x00000000
 158
 159 /*
 160  * Memory test
 161  */
 162 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 163 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 164 #define CONFIG_SYS_MEMTEST_END          0x00140000
 165
 166 /*
 167  * The reserved memory
 168  */
 169 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 170 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 171
 172 /*
 173  * Initial RAM Base Address Setup
 174  */
 175 #define CONFIG_SYS_INIT_RAM_LOCK        1
 176 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 177 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 178 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 179                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 180
 181 /*
 182  * Local Bus Configuration & Clock Setup
 183  */
 184 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 185 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 186 #define CONFIG_SYS_LBC_LBCR             0x00040000
 187 #define CONFIG_FSL_ELBC         1
 188
 189 /*
 190  * FLASH on the Local Bus
 191  */
 192 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 193 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 194 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 195
 196 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 197 #define CONFIG_SYS_FLASH_SIZE           8       /* FLASH size is 8M */
 198 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 199
 200                                         /* Window base at flash base */
 201 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 202 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 203
 204 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 205                                         | BR_PS_16      /* 16 bit port */ \
 206                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 207                                         | BR_V)         /* valid */
 208 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 209                                         | OR_UPM_XAM \
 210                                         | OR_GPCM_CSNT \
 211                                         | OR_GPCM_ACS_DIV2 \
 212                                         | OR_GPCM_XACS \
 213                                         | OR_GPCM_SCY_15 \
 214                                         | OR_GPCM_TRLX_SET \
 215                                         | OR_GPCM_EHTR_SET \
 216                                         | OR_GPCM_EAD)
 217
 218 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 219 /* 127 64KB sectors and 8 8KB top sectors per device */
 220 #define CONFIG_SYS_MAX_FLASH_SECT       135
 221
 222 #undef CONFIG_SYS_FLASH_CHECKSUM
 223 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 224 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 225
 226 /*
 227  * NAND Flash on the Local Bus
 228  */
 229
 230 #ifdef CONFIG_NAND_SPL
 231 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 232 #else
 233 #define CONFIG_SYS_NAND_BASE            0xE0600000
 234 #endif
 235
 236 #define CONFIG_MTD_DEVICE
 237 #define CONFIG_MTD_PARTITION
 238
 239 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 240 #define CONFIG_NAND_FSL_ELBC            1
 241 #define CONFIG_SYS_NAND_BLOCK_SIZE      16384
 242 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 243
 244 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 245 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 246 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 247 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 248 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 249
 250 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 251                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 252                                 | BR_PS_8               /* 8 bit port */ \
 253                                 | BR_MS_FCM             /* MSEL = FCM */ \
 254                                 | BR_V)                 /* valid */
 255 #define CONFIG_SYS_NAND_OR_PRELIM       \
 256                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 257                                 | OR_FCM_CSCT \
 258                                 | OR_FCM_CST \
 259                                 | OR_FCM_CHT \
 260                                 | OR_FCM_SCY_1 \
 261                                 | OR_FCM_TRLX \
 262                                 | OR_FCM_EHTR)
 263                                 /* 0xFFFF8396 */
 264
 265 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 266 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 267 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 268 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 269
 270 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 271 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 272
 273 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 274 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 275
 276 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 277         !defined(CONFIG_NAND_SPL)
 278 #define CONFIG_SYS_RAMBOOT
 279 #else
 280 #undef CONFIG_SYS_RAMBOOT
 281 #endif
 282
 283 /*
 284  * Serial Port
 285  */
 286 #define CONFIG_CONS_INDEX       1
 287 #define CONFIG_SYS_NS16550_SERIAL
 288 #define CONFIG_SYS_NS16550_REG_SIZE     1
 289 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
 290
 291 #define CONFIG_SYS_BAUDRATE_TABLE  \
 292                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 293
 294 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 295 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 296
 297 /* I2C */
 298 #define CONFIG_SYS_I2C
 299 #define CONFIG_SYS_I2C_FSL
 300 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 301 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 302 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 303 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 304
 305 /*
 306  * Board info - revision and where boot from
 307  */
 308 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 309
 310 /*
 311  * Config on-board RTC
 312  */
 313 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 314 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 315
 316 /*
 317  * General PCI
 318  * Addresses are mapped 1-1.
 319  */
 320 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 321 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 322 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 323 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 324 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 325 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 326 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 327 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 328 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 329
 330 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 331 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 332 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 333
 334 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 335 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 336 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 337 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 338 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 339 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 340 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 341 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 342 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 343
 344 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 345 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 346 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 347 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 348 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 349 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 350 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 351 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 352 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 353
 354 #define CONFIG_PCI_INDIRECT_BRIDGE
 355 #define CONFIG_PCIE
 356
 357 #define CONFIG_EEPRO100
 358 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 359 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 360
 361 #define CONFIG_HAS_FSL_DR_USB
 362 #define CONFIG_SYS_SCCR_USBDRCM         3
 363
 364 #define CONFIG_USB_EHCI_FSL
 365 #define CONFIG_USB_PHY_TYPE     "utmi"
 366 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 367
 368 /*
 369  * TSEC
 370  */
 371 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 372 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 373 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 374 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 375 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 376
 377 /*
 378  * TSEC ethernet configuration
 379  */
 380 #define CONFIG_MII              1 /* MII PHY management */
 381 #define CONFIG_TSEC1            1
 382 #define CONFIG_TSEC1_NAME       "eTSEC0"
 383 #define CONFIG_TSEC2            1
 384 #define CONFIG_TSEC2_NAME       "eTSEC1"
 385 #define TSEC1_PHY_ADDR          0
 386 #define TSEC2_PHY_ADDR          1
 387 #define TSEC1_PHYIDX            0
 388 #define TSEC2_PHYIDX            0
 389 #define TSEC1_FLAGS             TSEC_GIGABIT
 390 #define TSEC2_FLAGS             TSEC_GIGABIT
 391
 392 /* Options are: eTSEC[0-1] */
 393 #define CONFIG_ETHPRIME         "eTSEC1"
 394
 395 /*
 396  * SATA
 397  */
 398 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 399 #define CONFIG_SATA1
 400 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 401 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 402 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 403 #define CONFIG_SATA2
 404 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 405 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 406 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 407
 408 #ifdef CONFIG_FSL_SATA
 409 #define CONFIG_LBA48
 410 #endif
 411
 412 /*
 413  * Environment
 414  */
 415 #if !defined(CONFIG_SYS_RAMBOOT)
 416         #define CONFIG_ENV_ADDR         \
 417                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 418         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 419         #define CONFIG_ENV_SIZE         0x2000
 420 #else
 421         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 422         #define CONFIG_ENV_SIZE         0x2000
 423 #endif
 424
 425 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 426 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 427
 428 /*
 429  * BOOTP options
 430  */
 431 #define CONFIG_BOOTP_BOOTFILESIZE
 432 #define CONFIG_BOOTP_BOOTPATH
 433 #define CONFIG_BOOTP_GATEWAY
 434 #define CONFIG_BOOTP_HOSTNAME
 435
 436 /*
 437  * Command line configuration.
 438  */
 439
 440 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 441 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 442
 443 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 444
 445 /*
 446  * Miscellaneous configurable options
 447  */
 448 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 449 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 450
 451 /*
 452  * For booting Linux, the board info and command line data
 453  * have to be in the first 256 MB of memory, since this is
 454  * the maximum mapped by the Linux kernel during initialization.
 455  */
 456 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 457 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 458
 459 /*
 460  * Core HID Setup
 461  */
 462 #define CONFIG_SYS_HID0_INIT    0x000000000
 463 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 464                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 465                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 466 #define CONFIG_SYS_HID2         HID2_HBE
 467
 468 /*
 469  * MMU Setup
 470  */
 471 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 472
 473 /* DDR: cache cacheable */
 474 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 475                                 | BATL_PP_RW \
 476                                 | BATL_MEMCOHERENCE)
 477 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 478                                 | BATU_BL_128M \
 479                                 | BATU_VS \
 480                                 | BATU_VP)
 481 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 482 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 483
 484 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 485 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 486                                 | BATL_PP_RW \
 487                                 | BATL_CACHEINHIBIT \
 488                                 | BATL_GUARDEDSTORAGE)
 489 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 490                                 | BATU_BL_8M \
 491                                 | BATU_VS \
 492                                 | BATU_VP)
 493 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 494 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 495
 496 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 497 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 498                                 | BATL_PP_RW \
 499                                 | BATL_MEMCOHERENCE)
 500 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 501                                 | BATU_BL_32M \
 502                                 | BATU_VS \
 503                                 | BATU_VP)
 504 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 505                                 | BATL_PP_RW \
 506                                 | BATL_CACHEINHIBIT \
 507                                 | BATL_GUARDEDSTORAGE)
 508 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 509
 510 /* Stack in dcache: cacheable, no memory coherence */
 511 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 512 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR \
 513                                 | BATU_BL_128K \
 514                                 | BATU_VS \
 515                                 | BATU_VP)
 516 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 517 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 518
 519 /* PCI MEM space: cacheable */
 520 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI_MEM_PHYS \
 521                                 | BATL_PP_RW \
 522                                 | BATL_MEMCOHERENCE)
 523 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI_MEM_PHYS \
 524                                 | BATU_BL_256M \
 525                                 | BATU_VS \
 526                                 | BATU_VP)
 527 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 528 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 529
 530 /* PCI MMIO space: cache-inhibit and guarded */
 531 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI_MMIO_PHYS \
 532                                 | BATL_PP_RW \
 533                                 | BATL_CACHEINHIBIT \
 534                                 | BATL_GUARDEDSTORAGE)
 535 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI_MMIO_PHYS \
 536                                 | BATU_BL_256M \
 537                                 | BATU_VS \
 538                                 | BATU_VP)
 539 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 540 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 541
 542 #define CONFIG_SYS_IBAT6L       0
 543 #define CONFIG_SYS_IBAT6U       0
 544 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 545 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 546
 547 #define CONFIG_SYS_IBAT7L       0
 548 #define CONFIG_SYS_IBAT7U       0
 549 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 550 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 551
 552 #if defined(CONFIG_CMD_KGDB)
 553 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 554 #endif
 555
 556 /*
 557  * Environment Configuration
 558  */
 559
 560 #define CONFIG_ENV_OVERWRITE
 561
 562 #if defined(CONFIG_TSEC_ENET)
 563 #define CONFIG_HAS_ETH0
 564 #define CONFIG_HAS_ETH1
 565 #endif
 566
 567 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 568
 569 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 570         "netdev=eth0\0"                                                 \
 571         "consoledev=ttyS0\0"                                            \
 572         "ramdiskaddr=1000000\0"                                         \
 573         "ramdiskfile=ramfs.83xx\0"                                      \
 574         "fdtaddr=780000\0"                                              \
 575         "fdtfile=mpc8315erdb.dtb\0"                                     \
 576         "usb_phy_type=utmi\0"                                           \
 577         ""
 578
 579 #define CONFIG_NFSBOOTCOMMAND                                           \
 580         "setenv bootargs root=/dev/nfs rw "                             \
 581                 "nfsroot=$serverip:$rootpath "                          \
 582                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 583                                                         "$netdev:off "  \
 584                 "console=$consoledev,$baudrate $othbootargs;"           \
 585         "tftp $loadaddr $bootfile;"                                     \
 586         "tftp $fdtaddr $fdtfile;"                                       \
 587         "bootm $loadaddr - $fdtaddr"
 588
 589 #define CONFIG_RAMBOOTCOMMAND                                           \
 590         "setenv bootargs root=/dev/ram rw "                             \
 591                 "console=$consoledev,$baudrate $othbootargs;"           \
 592         "tftp $ramdiskaddr $ramdiskfile;"                               \
 593         "tftp $loadaddr $bootfile;"                                     \
 594         "tftp $fdtaddr $fdtfile;"                                       \
 595         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 596
 597 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 598
 599 #endif  /* __CONFIG_H */