include/configs/MPC8315ERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  12 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  13 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  14 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  15 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 /*
  22  * High Level Configuration Options
  23  */
  24 #define CONFIG_E300             1 /* E300 family */
  25
  26 /*
  27  * System IO Config
  28  */
  29 #define CONFIG_SYS_SICRH                0x00000000
  30 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  31
  32 #define CONFIG_HWCONFIG
  33
  34 /*
  35  * DDR Setup
  36  */
  37 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  38 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  39 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  40 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  41 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  42                                 | DDRCDR_PZ_LOZ \
  43                                 | DDRCDR_NZ_LOZ \
  44                                 | DDRCDR_ODT \
  45                                 | DDRCDR_Q_DRN)
  46                                 /* 0x7b880001 */
  47 /*
  48  * Manually set up DDR parameters
  49  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  50  */
  51 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  52 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  53 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  54                                 | CSCONFIG_ODT_RD_NEVER \
  55                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  56                                 | CSCONFIG_ROW_BIT_13 \
  57                                 | CSCONFIG_COL_BIT_10)
  58                                 /* 0x80010102 */
  59 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  60 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  61                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  62                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  63                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  64                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  65                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  66                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  67                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  68                                 /* 0x00220802 */
  69 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  70                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  71                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  72                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  73                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  74                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  75                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  76                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  77                                 /* 0x27256222 */
  78 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  79                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  80                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  81                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  82                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  83                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  84                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  85                                 /* 0x121048c5 */
  86 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
  87                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  88                                 /* 0x03600100 */
  89 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  90                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  91                                 | SDRAM_CFG_DBW_32)
  92                                 /* 0x43080000 */
  93 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
  94 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
  95                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  96                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
  97 #define CONFIG_SYS_DDR_MODE2    0x00000000
  98
  99 /*
 100  * Memory test
 101  */
 102 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 103 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 104 #define CONFIG_SYS_MEMTEST_END          0x00140000
 105
 106 /*
 107  * The reserved memory
 108  */
 109 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 110 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 111
 112 /*
 113  * Initial RAM Base Address Setup
 114  */
 115 #define CONFIG_SYS_INIT_RAM_LOCK        1
 116 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 117 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 118 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 119                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 120
 121 /*
 122  * Local Bus Configuration & Clock Setup
 123  */
 124 #define CONFIG_SYS_LBC_LBCR             0x00040000
 125 #define CONFIG_FSL_ELBC         1
 126
 127 /*
 128  * FLASH on the Local Bus
 129  */
 130 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 131
 132 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 133 #define CONFIG_SYS_FLASH_SIZE           8       /* FLASH size is 8M */
 134
 135 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 136 /* 127 64KB sectors and 8 8KB top sectors per device */
 137 #define CONFIG_SYS_MAX_FLASH_SECT       135
 138
 139 #undef CONFIG_SYS_FLASH_CHECKSUM
 140 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 141 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 142
 143 /*
 144  * NAND Flash on the Local Bus
 145  */
 146
 147 #ifdef CONFIG_NAND_SPL
 148 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 149 #else
 150 #define CONFIG_SYS_NAND_BASE            0xE0600000
 151 #endif
 152
 153 #define CONFIG_MTD_PARTITION
 154
 155 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 156 #define CONFIG_NAND_FSL_ELBC            1
 157 #define CONFIG_SYS_NAND_BLOCK_SIZE      16384
 158 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 159
 160 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 161 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 162 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 163 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 164 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 165
 166
 167
 168 /* Still needed for spl_minimal.c */
 169 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 170 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 171
 172 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 173         !defined(CONFIG_NAND_SPL)
 174 #define CONFIG_SYS_RAMBOOT
 175 #else
 176 #undef CONFIG_SYS_RAMBOOT
 177 #endif
 178
 179 /*
 180  * Serial Port
 181  */
 182 #define CONFIG_SYS_NS16550_SERIAL
 183 #define CONFIG_SYS_NS16550_REG_SIZE     1
 184 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
 185
 186 #define CONFIG_SYS_BAUDRATE_TABLE  \
 187                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 188
 189 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 190 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 191
 192 /* I2C */
 193 #define CONFIG_SYS_I2C
 194 #define CONFIG_SYS_I2C_FSL
 195 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 196 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 197 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 198 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 199
 200 /*
 201  * Board info - revision and where boot from
 202  */
 203 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 204
 205 /*
 206  * Config on-board RTC
 207  */
 208 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 209 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 210
 211 /*
 212  * General PCI
 213  * Addresses are mapped 1-1.
 214  */
 215 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 216 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 217 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 218 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 219 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 220 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 221 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 222 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 223 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 224
 225 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 226 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 227 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 228
 229 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 230 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 231 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 232 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 233 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 234 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 235 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 236 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 237 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 238
 239 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 240 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 241 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 242 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 243 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 244 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 245 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 246 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 247 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 248
 249 #define CONFIG_PCI_INDIRECT_BRIDGE
 250 #define CONFIG_PCIE
 251
 252 #define CONFIG_EEPRO100
 253 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 254 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 255
 256 #define CONFIG_HAS_FSL_DR_USB
 257 #define CONFIG_SYS_SCCR_USBDRCM         3
 258
 259 #define CONFIG_USB_EHCI_FSL
 260 #define CONFIG_USB_PHY_TYPE     "utmi"
 261 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 262
 263 /*
 264  * TSEC
 265  */
 266 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 267 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 268 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 269 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 270
 271 /*
 272  * TSEC ethernet configuration
 273  */
 274 #define CONFIG_TSEC1            1
 275 #define CONFIG_TSEC1_NAME       "eTSEC0"
 276 #define CONFIG_TSEC2            1
 277 #define CONFIG_TSEC2_NAME       "eTSEC1"
 278 #define TSEC1_PHY_ADDR          0
 279 #define TSEC2_PHY_ADDR          1
 280 #define TSEC1_PHYIDX            0
 281 #define TSEC2_PHYIDX            0
 282 #define TSEC1_FLAGS             TSEC_GIGABIT
 283 #define TSEC2_FLAGS             TSEC_GIGABIT
 284
 285 /* Options are: eTSEC[0-1] */
 286 #define CONFIG_ETHPRIME         "eTSEC1"
 287
 288 /*
 289  * SATA
 290  */
 291 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 292 #define CONFIG_SATA1
 293 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 294 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 295 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 296 #define CONFIG_SATA2
 297 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 298 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 299 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 300
 301 #ifdef CONFIG_FSL_SATA
 302 #define CONFIG_LBA48
 303 #endif
 304
 305 /*
 306  * Environment
 307  */
 308 #if !defined(CONFIG_SYS_RAMBOOT)
 309         #define CONFIG_ENV_ADDR         \
 310                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 311         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 312         #define CONFIG_ENV_SIZE         0x2000
 313 #else
 314         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 315         #define CONFIG_ENV_SIZE         0x2000
 316 #endif
 317
 318 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 319 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 320
 321 /*
 322  * BOOTP options
 323  */
 324 #define CONFIG_BOOTP_BOOTFILESIZE
 325
 326 /*
 327  * Command line configuration.
 328  */
 329
 330 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 331
 332 /*
 333  * Miscellaneous configurable options
 334  */
 335 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 336
 337 /*
 338  * For booting Linux, the board info and command line data
 339  * have to be in the first 256 MB of memory, since this is
 340  * the maximum mapped by the Linux kernel during initialization.
 341  */
 342 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 343 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 344
 345 /*
 346  * MMU Setup
 347  */
 348
 349 #if defined(CONFIG_CMD_KGDB)
 350 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 351 #endif
 352
 353 /*
 354  * Environment Configuration
 355  */
 356
 357 #define CONFIG_ENV_OVERWRITE
 358
 359 #if defined(CONFIG_TSEC_ENET)
 360 #define CONFIG_HAS_ETH0
 361 #define CONFIG_HAS_ETH1
 362 #endif
 363
 364 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 365
 366 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 367         "netdev=eth0\0"                                                 \
 368         "consoledev=ttyS0\0"                                            \
 369         "ramdiskaddr=1000000\0"                                         \
 370         "ramdiskfile=ramfs.83xx\0"                                      \
 371         "fdtaddr=780000\0"                                              \
 372         "fdtfile=mpc8315erdb.dtb\0"                                     \
 373         "usb_phy_type=utmi\0"                                           \
 374         ""
 375
 376 #define CONFIG_NFSBOOTCOMMAND                                           \
 377         "setenv bootargs root=/dev/nfs rw "                             \
 378                 "nfsroot=$serverip:$rootpath "                          \
 379                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 380                                                         "$netdev:off "  \
 381                 "console=$consoledev,$baudrate $othbootargs;"           \
 382         "tftp $loadaddr $bootfile;"                                     \
 383         "tftp $fdtaddr $fdtfile;"                                       \
 384         "bootm $loadaddr - $fdtaddr"
 385
 386 #define CONFIG_RAMBOOTCOMMAND                                           \
 387         "setenv bootargs root=/dev/ram rw "                             \
 388                 "console=$consoledev,$baudrate $othbootargs;"           \
 389         "tftp $ramdiskaddr $ramdiskfile;"                               \
 390         "tftp $loadaddr $bootfile;"                                     \
 391         "tftp $fdtaddr $fdtfile;"                                       \
 392         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 393
 394 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 395
 396 #endif  /* __CONFIG_H */