include/configs/MPC8313ERDB_NOR.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 #define CONFIG_PCI_INDIRECT_BRIDGE
  22 #define CONFIG_FSL_ELBC 1
  23
  24 /*
  25  * On-board devices
  26  *
  27  * TSEC1 is VSC switch
  28  * TSEC2 is SoC TSEC
  29  */
  30 #define CONFIG_VSC7385_ENET
  31 #define CONFIG_TSEC2
  32
  33 #define CONFIG_SYS_IMMR         0xE0000000
  34
  35 #define CONFIG_SYS_MEMTEST_START        0x00001000
  36 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  37
  38 /* Early revs of this board will lock up hard when attempting
  39  * to access the PMC registers, unless a JTAG debugger is
  40  * connected, or some resistor modifications are made.
  41  */
  42 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  43
  44 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  45 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  46
  47 /*
  48  * Device configurations
  49  */
  50
  51 /* Vitesse 7385 */
  52
  53 #ifdef CONFIG_VSC7385_ENET
  54
  55 #define CONFIG_TSEC1
  56
  57 /* The flash address and size of the VSC7385 firmware image */
  58 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  59 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  60
  61 #endif
  62
  63 /*
  64  * DDR Setup
  65  */
  66 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  67 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  69
  70 /*
  71  * Manually set up DDR parameters, as this board does not
  72  * seem to have the SPD connected to I2C.
  73  */
  74 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
  75 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  76                                 | CSCONFIG_ODT_RD_NEVER \
  77                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  78                                 | CSCONFIG_ROW_BIT_13 \
  79                                 | CSCONFIG_COL_BIT_10)
  80                                 /* 0x80010102 */
  81
  82 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  83 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  84                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  85                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  86                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  87                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  88                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  89                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  90                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  91                                 /* 0x00220802 */
  92 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  93                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  94                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  95                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  96                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
  97                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  98                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  99                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 100                                 /* 0x3835a322 */
 101 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 102                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 103                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 104                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 105                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 106                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 107                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 108                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 109 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 110                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 111                                 /* 0x05100500 */
 112 #if defined(CONFIG_DDR_2T_TIMING)
 113 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 114                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 115                                 | SDRAM_CFG_DBW_32 \
 116                                 | SDRAM_CFG_2T_EN)
 117                                 /* 0x43088000 */
 118 #else
 119 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 120                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 121                                 | SDRAM_CFG_DBW_32)
 122                                 /* 0x43080000 */
 123 #endif
 124 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 125 /* set burst length to 8 for 32-bit data path */
 126 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 127                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 128                                 /* 0x44480632 */
 129 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 130
 131 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 132                                 /*0x02000000*/
 133 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 134                                 | DDRCDR_PZ_NOMZ \
 135                                 | DDRCDR_NZ_NOMZ \
 136                                 | DDRCDR_M_ODR)
 137
 138 /*
 139  * FLASH on the Local Bus
 140  */
 141 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 142 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 143 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 144 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 145
 146 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 147                                         | BR_PS_16      /* 16 bit port */ \
 148                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 149                                         | BR_V)         /* valid */
 150 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 151                                 | OR_GPCM_XACS \
 152                                 | OR_GPCM_SCY_9 \
 153                                 | OR_GPCM_EHTR \
 154                                 | OR_GPCM_EAD)
 155                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 156                                         /* window base at flash base */
 157 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 158                                         /* 16 MB window size */
 159 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 160
 161 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 162 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 163
 164 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 165 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 166
 167 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 168         !defined(CONFIG_SPL_BUILD)
 169 #define CONFIG_SYS_RAMBOOT
 170 #endif
 171
 172 #define CONFIG_SYS_INIT_RAM_LOCK        1
 173 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 174 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 175
 176 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 177                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 178 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 179
 180 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 181 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 182 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 183
 184 /*
 185  * Local Bus LCRR and LBCR regs
 186  */
 187 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 188 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 189 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 190                                 | (0xFF << LBCR_BMT_SHIFT) \
 191                                 | 0xF)  /* 0x0004ff0f */
 192
 193                                 /* LB refresh timer prescal, 266MHz/32 */
 194 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 195
 196 /* drivers/mtd/nand/nand.c */
 197 #define CONFIG_SYS_NAND_BASE            0xE2800000
 198
 199 #define CONFIG_MTD_PARTITION
 200
 201 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 202 #define CONFIG_NAND_FSL_ELBC 1
 203 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 204 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 205
 206 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 207                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 208                                 | BR_PS_8               /* 8 bit port */ \
 209                                 | BR_MS_FCM             /* MSEL = FCM */ \
 210                                 | BR_V)                 /* valid */
 211 #define CONFIG_SYS_OR1_PRELIM   \
 212                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 213                                 | OR_FCM_CSCT \
 214                                 | OR_FCM_CST \
 215                                 | OR_FCM_CHT \
 216                                 | OR_FCM_SCY_1 \
 217                                 | OR_FCM_TRLX \
 218                                 | OR_FCM_EHTR)
 219                                 /* 0xFFFF8396 */
 220
 221 /* Still needed for spl_minimal.c */
 222 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 223 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 224
 225 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 226 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 227
 228 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 229 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 230
 231 /* local bus write LED / read status buffer (BCSR) mapping */
 232 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 233 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 234                                         /* map at 0xFA000000 on LCS3 */
 235 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
 236                                         | BR_PS_8       /* 8 bit port */ \
 237                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 238                                         | BR_V)         /* valid */
 239                                         /* 0xFA000801 */
 240 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
 241                                         | OR_GPCM_CSNT \
 242                                         | OR_GPCM_ACS_DIV2 \
 243                                         | OR_GPCM_XACS \
 244                                         | OR_GPCM_SCY_15 \
 245                                         | OR_GPCM_TRLX_SET \
 246                                         | OR_GPCM_EHTR_SET \
 247                                         | OR_GPCM_EAD)
 248                                         /* 0xFFFF8FF7 */
 249 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
 250 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 251
 252 /* Vitesse 7385 */
 253
 254 #ifdef CONFIG_VSC7385_ENET
 255
 256                                         /* VSC7385 Base address on LCS2 */
 257 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 258 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 259
 260 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 261                                         | BR_PS_8       /* 8 bit port */ \
 262                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 263                                         | BR_V)         /* valid */
 264 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 265                                         | OR_GPCM_CSNT \
 266                                         | OR_GPCM_XACS \
 267                                         | OR_GPCM_SCY_15 \
 268                                         | OR_GPCM_SETA \
 269                                         | OR_GPCM_TRLX_SET \
 270                                         | OR_GPCM_EHTR_SET \
 271                                         | OR_GPCM_EAD)
 272                                         /* 0xFFFE09FF */
 273
 274                                         /* Access window base at VSC7385 base */
 275 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 276 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 277
 278 #endif
 279
 280 #define CONFIG_MPC83XX_GPIO 1
 281
 282 /*
 283  * Serial Port
 284  */
 285 #define CONFIG_SYS_NS16550_SERIAL
 286 #define CONFIG_SYS_NS16550_REG_SIZE     1
 287
 288 #define CONFIG_SYS_BAUDRATE_TABLE       \
 289         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 290
 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 293
 294 /* I2C */
 295 #define CONFIG_SYS_I2C
 296 #define CONFIG_SYS_I2C_FSL
 297 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 298 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 299 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 300 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 301 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 302 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 303 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 304
 305 /*
 306  * General PCI
 307  * Addresses are mapped 1-1.
 308  */
 309 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 310 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 311 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 312 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 313 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 314 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 315 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 316 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 317 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 318
 319 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 320
 321 /*
 322  * TSEC
 323  */
 324
 325 #define CONFIG_GMII                     /* MII PHY management */
 326
 327 #ifdef CONFIG_TSEC1
 328 #define CONFIG_HAS_ETH0
 329 #define CONFIG_TSEC1_NAME       "TSEC0"
 330 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 331 #define TSEC1_PHY_ADDR          0x1c
 332 #define TSEC1_FLAGS             TSEC_GIGABIT
 333 #define TSEC1_PHYIDX            0
 334 #endif
 335
 336 #ifdef CONFIG_TSEC2
 337 #define CONFIG_HAS_ETH1
 338 #define CONFIG_TSEC2_NAME       "TSEC1"
 339 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 340 #define TSEC2_PHY_ADDR          4
 341 #define TSEC2_FLAGS             TSEC_GIGABIT
 342 #define TSEC2_PHYIDX            0
 343 #endif
 344
 345 /* Options are: TSEC[0-1] */
 346 #define CONFIG_ETHPRIME                 "TSEC1"
 347
 348 /*
 349  * Configure on-board RTC
 350  */
 351 #define CONFIG_RTC_DS1337
 352 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 353
 354 /*
 355  * Environment
 356  */
 357 #if !defined(CONFIG_SYS_RAMBOOT)
 358         #define CONFIG_ENV_ADDR         \
 359                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 360         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 361         #define CONFIG_ENV_SIZE         0x2000
 362
 363 /* Address and size of Redundant Environment Sector */
 364 #else
 365         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 366         #define CONFIG_ENV_SIZE         0x2000
 367 #endif
 368
 369 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 370 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 371
 372 /*
 373  * BOOTP options
 374  */
 375 #define CONFIG_BOOTP_BOOTFILESIZE
 376
 377 /*
 378  * Command line configuration.
 379  */
 380
 381 /*
 382  * Miscellaneous configurable options
 383  */
 384 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 385 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 386
 387                                 /* Boot Argument Buffer Size */
 388 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 389
 390 /*
 391  * For booting Linux, the board info and command line data
 392  * have to be in the first 256 MB of memory, since this is
 393  * the maximum mapped by the Linux kernel during initialization.
 394  */
 395                                 /* Initial Memory map for Linux*/
 396 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 397 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 398
 399 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 400
 401 #ifdef CONFIG_SYS_66MHZ
 402
 403 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 404 /* 0x62040000 */
 405 #define CONFIG_SYS_HRCW_LOW (\
 406         0x20000000 /* reserved, must be set */ |\
 407         HRCWL_DDRCM |\
 408         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 409         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 410         HRCWL_CSB_TO_CLKIN_2X1 |\
 411         HRCWL_CORE_TO_CSB_2X1)
 412
 413 #elif defined(CONFIG_SYS_33MHZ)
 414
 415 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 416 /* 0x65040000 */
 417 #define CONFIG_SYS_HRCW_LOW (\
 418         0x20000000 /* reserved, must be set */ |\
 419         HRCWL_DDRCM |\
 420         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 421         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 422         HRCWL_CSB_TO_CLKIN_5X1 |\
 423         HRCWL_CORE_TO_CSB_2X1)
 424
 425 #endif
 426
 427 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 428         HRCWH_PCI_HOST |\
 429         HRCWH_PCI1_ARBITER_ENABLE |\
 430         HRCWH_CORE_ENABLE |\
 431         HRCWH_BOOTSEQ_DISABLE |\
 432         HRCWH_SW_WATCHDOG_DISABLE |\
 433         HRCWH_TSEC1M_IN_RGMII |\
 434         HRCWH_TSEC2M_IN_RGMII |\
 435         HRCWH_BIG_ENDIAN)
 436
 437 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 438                        HRCWH_FROM_0X00000100 |\
 439                        HRCWH_ROM_LOC_LOCAL_16BIT |\
 440                        HRCWH_RL_EXT_LEGACY)
 441 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 442
 443 /* System IO Config */
 444 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 445                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 446 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 447
 448 #define CONFIG_SYS_HID0_INIT    0x000000000
 449 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 450                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 451                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 452
 453 #define CONFIG_SYS_HID2 HID2_HBE
 454
 455 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 456
 457 /* DDR @ 0x00000000 */
 458 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 459 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 460                                 | BATU_BL_256M \
 461                                 | BATU_VS \
 462                                 | BATU_VP)
 463
 464 /* PCI @ 0x80000000 */
 465 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 466 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 467                                 | BATU_BL_256M \
 468                                 | BATU_VS \
 469                                 | BATU_VP)
 470 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 471                                 | BATL_PP_RW \
 472                                 | BATL_CACHEINHIBIT \
 473                                 | BATL_GUARDEDSTORAGE)
 474 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 475                                 | BATU_BL_256M \
 476                                 | BATU_VS \
 477                                 | BATU_VP)
 478
 479 /* PCI2 not supported on 8313 */
 480 #define CONFIG_SYS_IBAT3L       (0)
 481 #define CONFIG_SYS_IBAT3U       (0)
 482 #define CONFIG_SYS_IBAT4L       (0)
 483 #define CONFIG_SYS_IBAT4U       (0)
 484
 485 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 486 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 487                                 | BATL_PP_RW \
 488                                 | BATL_CACHEINHIBIT \
 489                                 | BATL_GUARDEDSTORAGE)
 490 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 491                                 | BATU_BL_256M \
 492                                 | BATU_VS \
 493                                 | BATU_VP)
 494
 495 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 496 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 497 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 498
 499 #define CONFIG_SYS_IBAT7L       (0)
 500 #define CONFIG_SYS_IBAT7U       (0)
 501
 502 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 503 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 504 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 505 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 506 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 507 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 508 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 509 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 510 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 511 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 512 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 513 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 514 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 515 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 516 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 517 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 518
 519 /*
 520  * Environment Configuration
 521  */
 522 #define CONFIG_ENV_OVERWRITE
 523
 524 #define CONFIG_NETDEV           "eth1"
 525
 526 #define CONFIG_HOSTNAME         "mpc8313erdb"
 527 #define CONFIG_ROOTPATH         "/nfs/root/path"
 528 #define CONFIG_BOOTFILE         "uImage"
 529                                 /* U-Boot image on TFTP server */
 530 #define CONFIG_UBOOTPATH        "u-boot.bin"
 531 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 532
 533                                 /* default location for tftp and bootm */
 534 #define CONFIG_LOADADDR         800000
 535
 536 #define CONFIG_EXTRA_ENV_SETTINGS \
 537         "netdev=" CONFIG_NETDEV "\0"                                    \
 538         "ethprime=TSEC1\0"                                              \
 539         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 540         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 541                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 542                         " +$filesize; " \
 543                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 544                         " +$filesize; " \
 545                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 546                         " $filesize; "  \
 547                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 548                         " +$filesize; " \
 549                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 550                         " $filesize\0"  \
 551         "fdtaddr=780000\0"                                              \
 552         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 553         "console=ttyS0\0"                                               \
 554         "setbootargs=setenv bootargs "                                  \
 555                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 556         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 557                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 558                                                         "$netdev:off " \
 559                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 560
 561 #define CONFIG_NFSBOOTCOMMAND                                           \
 562         "setenv rootdev /dev/nfs;"                                      \
 563         "run setbootargs;"                                              \
 564         "run setipargs;"                                                \
 565         "tftp $loadaddr $bootfile;"                                     \
 566         "tftp $fdtaddr $fdtfile;"                                       \
 567         "bootm $loadaddr - $fdtaddr"
 568
 569 #define CONFIG_RAMBOOTCOMMAND                                           \
 570         "setenv rootdev /dev/ram;"                                      \
 571         "run setbootargs;"                                              \
 572         "tftp $ramdiskaddr $ramdiskfile;"                               \
 573         "tftp $loadaddr $bootfile;"                                     \
 574         "tftp $fdtaddr $fdtfile;"                                       \
 575         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 576
 577 #endif  /* __CONFIG_H */