include/configs/MPC8313ERDB_NAND.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16
  17 #define CONFIG_SPL_INIT_MINIMAL
  18 #define CONFIG_SPL_FLUSH_IMAGE
  19 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  20 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  21
  22 #ifdef CONFIG_SPL_BUILD
  23 #define CONFIG_NS16550_MIN_FUNCTIONS
  24 #endif
  25
  26 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  27 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
  28 #define CONFIG_SPL_PAD_TO       0x4000
  29
  30 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  31 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  33 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  34 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  35 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  36
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  39 #endif
  40
  41 #ifndef CONFIG_SYS_MONITOR_BASE
  42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  43 #endif
  44
  45 #define CONFIG_PCI_INDIRECT_BRIDGE
  46 #define CONFIG_FSL_ELBC 1
  47
  48 /*
  49  * On-board devices
  50  *
  51  * TSEC1 is VSC switch
  52  * TSEC2 is SoC TSEC
  53  */
  54 #define CONFIG_VSC7385_ENET
  55 #define CONFIG_TSEC2
  56
  57 #define CONFIG_SYS_IMMR         0xE0000000
  58
  59 #if !defined(CONFIG_SPL_BUILD)
  60 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  61 #endif
  62
  63 #define CONFIG_SYS_MEMTEST_START        0x00001000
  64 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  65
  66 /* Early revs of this board will lock up hard when attempting
  67  * to access the PMC registers, unless a JTAG debugger is
  68  * connected, or some resistor modifications are made.
  69  */
  70 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  71
  72 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  73 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  74
  75 /*
  76  * Device configurations
  77  */
  78
  79 /* Vitesse 7385 */
  80
  81 #ifdef CONFIG_VSC7385_ENET
  82
  83 #define CONFIG_TSEC1
  84
  85 /* The flash address and size of the VSC7385 firmware image */
  86 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  87 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  88
  89 #endif
  90
  91 /*
  92  * DDR Setup
  93  */
  94 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  95 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  97
  98 /*
  99  * Manually set up DDR parameters, as this board does not
 100  * seem to have the SPD connected to I2C.
 101  */
 102 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
 103 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 104                                 | CSCONFIG_ODT_RD_NEVER \
 105                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 106                                 | CSCONFIG_ROW_BIT_13 \
 107                                 | CSCONFIG_COL_BIT_10)
 108                                 /* 0x80010102 */
 109
 110 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 111 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 112                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 113                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 114                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 115                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 116                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 117                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 118                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 119                                 /* 0x00220802 */
 120 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 121                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 122                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 123                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 124                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 125                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 126                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 127                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 128                                 /* 0x3835a322 */
 129 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 130                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 131                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 132                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 133                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 134                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 135                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 136                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 137 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 138                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 139                                 /* 0x05100500 */
 140 #if defined(CONFIG_DDR_2T_TIMING)
 141 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 142                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 143                                 | SDRAM_CFG_DBW_32 \
 144                                 | SDRAM_CFG_2T_EN)
 145                                 /* 0x43088000 */
 146 #else
 147 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 148                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 149                                 | SDRAM_CFG_DBW_32)
 150                                 /* 0x43080000 */
 151 #endif
 152 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 153 /* set burst length to 8 for 32-bit data path */
 154 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 155                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 156                                 /* 0x44480632 */
 157 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 158
 159 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 160                                 /*0x02000000*/
 161 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 162                                 | DDRCDR_PZ_NOMZ \
 163                                 | DDRCDR_NZ_NOMZ \
 164                                 | DDRCDR_M_ODR)
 165
 166 /*
 167  * FLASH on the Local Bus
 168  */
 169 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 170 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 171 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 172
 173 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE \
 174                                         | BR_PS_16      /* 16 bit port */ \
 175                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 176                                         | BR_V)         /* valid */
 177 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 178                                 | OR_GPCM_XACS \
 179                                 | OR_GPCM_SCY_9 \
 180                                 | OR_GPCM_EHTR \
 181                                 | OR_GPCM_EAD)
 182                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 183                                         /* window base at flash base */
 184 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 185                                         /* 16 MB window size */
 186 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 187
 188 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 189 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 190
 191 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 192 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 193
 194 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 195         !defined(CONFIG_SPL_BUILD)
 196 #define CONFIG_SYS_RAMBOOT
 197 #endif
 198
 199 #define CONFIG_SYS_INIT_RAM_LOCK        1
 200 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 201 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 202
 203 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 204                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 205 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 206
 207 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 208 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 209 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 210
 211 /*
 212  * Local Bus LCRR and LBCR regs
 213  */
 214 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 215 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 216 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 217                                 | (0xFF << LBCR_BMT_SHIFT) \
 218                                 | 0xF)  /* 0x0004ff0f */
 219
 220                                 /* LB refresh timer prescal, 266MHz/32 */
 221 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 222
 223 /* drivers/mtd/nand/raw/nand.c */
 224 #if defined(CONFIG_SPL_BUILD)
 225 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 226 #else
 227 #define CONFIG_SYS_NAND_BASE            0xE2800000
 228 #endif
 229
 230 #define CONFIG_MTD_PARTITION
 231
 232 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 233 #define CONFIG_NAND_FSL_ELBC 1
 234 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 235 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 236
 237 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_NAND_BASE \
 238                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 239                                 | BR_PS_8               /* 8 bit port */ \
 240                                 | BR_MS_FCM             /* MSEL = FCM */ \
 241                                 | BR_V)                 /* valid */
 242 #define CONFIG_SYS_OR0_PRELIM   \
 243                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 244                                 | OR_FCM_CSCT \
 245                                 | OR_FCM_CST \
 246                                 | OR_FCM_CHT \
 247                                 | OR_FCM_SCY_1 \
 248                                 | OR_FCM_TRLX \
 249                                 | OR_FCM_EHTR)
 250                                 /* 0xFFFF8396 */
 251
 252 /* Still needed for spl_minimal.c */
 253 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
 254 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
 255
 256 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 257 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 258
 259 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 260 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 261
 262 /* local bus write LED / read status buffer (BCSR) mapping */
 263 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 264 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 265                                         /* map at 0xFA000000 on LCS3 */
 266 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
 267                                         | BR_PS_8       /* 8 bit port */ \
 268                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 269                                         | BR_V)         /* valid */
 270                                         /* 0xFA000801 */
 271 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
 272                                         | OR_GPCM_CSNT \
 273                                         | OR_GPCM_ACS_DIV2 \
 274                                         | OR_GPCM_XACS \
 275                                         | OR_GPCM_SCY_15 \
 276                                         | OR_GPCM_TRLX_SET \
 277                                         | OR_GPCM_EHTR_SET \
 278                                         | OR_GPCM_EAD)
 279                                         /* 0xFFFF8FF7 */
 280 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
 281 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 282
 283 /* Vitesse 7385 */
 284
 285 #ifdef CONFIG_VSC7385_ENET
 286
 287                                         /* VSC7385 Base address on LCS2 */
 288 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 289 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 290
 291 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 292                                         | BR_PS_8       /* 8 bit port */ \
 293                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 294                                         | BR_V)         /* valid */
 295 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 296                                         | OR_GPCM_CSNT \
 297                                         | OR_GPCM_XACS \
 298                                         | OR_GPCM_SCY_15 \
 299                                         | OR_GPCM_SETA \
 300                                         | OR_GPCM_TRLX_SET \
 301                                         | OR_GPCM_EHTR_SET \
 302                                         | OR_GPCM_EAD)
 303                                         /* 0xFFFE09FF */
 304
 305                                         /* Access window base at VSC7385 base */
 306 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 307 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 308
 309 #endif
 310
 311 #define CONFIG_MPC83XX_GPIO 1
 312
 313 /*
 314  * Serial Port
 315  */
 316 #define CONFIG_SYS_NS16550_SERIAL
 317 #define CONFIG_SYS_NS16550_REG_SIZE     1
 318
 319 #define CONFIG_SYS_BAUDRATE_TABLE       \
 320         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 321
 322 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 323 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 324
 325 /* I2C */
 326 #define CONFIG_SYS_I2C
 327 #define CONFIG_SYS_I2C_FSL
 328 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 329 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 330 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 331 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 332 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 333 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 334 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 335
 336 /*
 337  * General PCI
 338  * Addresses are mapped 1-1.
 339  */
 340 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 341 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 342 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 343 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 344 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 345 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 346 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 347 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 348 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 349
 350 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 351
 352 /*
 353  * TSEC
 354  */
 355
 356 #define CONFIG_GMII                     /* MII PHY management */
 357
 358 #ifdef CONFIG_TSEC1
 359 #define CONFIG_HAS_ETH0
 360 #define CONFIG_TSEC1_NAME       "TSEC0"
 361 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 362 #define TSEC1_PHY_ADDR          0x1c
 363 #define TSEC1_FLAGS             TSEC_GIGABIT
 364 #define TSEC1_PHYIDX            0
 365 #endif
 366
 367 #ifdef CONFIG_TSEC2
 368 #define CONFIG_HAS_ETH1
 369 #define CONFIG_TSEC2_NAME       "TSEC1"
 370 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 371 #define TSEC2_PHY_ADDR          4
 372 #define TSEC2_FLAGS             TSEC_GIGABIT
 373 #define TSEC2_PHYIDX            0
 374 #endif
 375
 376 /* Options are: TSEC[0-1] */
 377 #define CONFIG_ETHPRIME                 "TSEC1"
 378
 379 /*
 380  * Configure on-board RTC
 381  */
 382 #define CONFIG_RTC_DS1337
 383 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 384
 385 /*
 386  * Environment
 387  */
 388 #define CONFIG_ENV_OFFSET               (512 * 1024)
 389 #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 390 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 391 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 392 #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 393 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 394
 395 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 396 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 397
 398 /*
 399  * BOOTP options
 400  */
 401 #define CONFIG_BOOTP_BOOTFILESIZE
 402
 403 /*
 404  * Command line configuration.
 405  */
 406
 407 /*
 408  * Miscellaneous configurable options
 409  */
 410 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 411 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 412
 413                                 /* Boot Argument Buffer Size */
 414 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 415
 416 /*
 417  * For booting Linux, the board info and command line data
 418  * have to be in the first 256 MB of memory, since this is
 419  * the maximum mapped by the Linux kernel during initialization.
 420  */
 421                                 /* Initial Memory map for Linux*/
 422 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 423 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 424
 425 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 426
 427 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 428
 429 /* System IO Config */
 430 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 431                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 432 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 433
 434 #define CONFIG_SYS_HID0_INIT    0x000000000
 435 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 436                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 437                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 438
 439 #define CONFIG_SYS_HID2 HID2_HBE
 440
 441 /*
 442  * Environment Configuration
 443  */
 444 #define CONFIG_ENV_OVERWRITE
 445
 446 #define CONFIG_NETDEV           "eth1"
 447
 448 #define CONFIG_HOSTNAME         "mpc8313erdb"
 449 #define CONFIG_ROOTPATH         "/nfs/root/path"
 450 #define CONFIG_BOOTFILE         "uImage"
 451                                 /* U-Boot image on TFTP server */
 452 #define CONFIG_UBOOTPATH        "u-boot.bin"
 453 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 454
 455                                 /* default location for tftp and bootm */
 456 #define CONFIG_LOADADDR         800000
 457
 458 #define CONFIG_EXTRA_ENV_SETTINGS \
 459         "netdev=" CONFIG_NETDEV "\0"                                    \
 460         "ethprime=TSEC1\0"                                              \
 461         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 462         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 463                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 464                         " +$filesize; " \
 465                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 466                         " +$filesize; " \
 467                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 468                         " $filesize; "  \
 469                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 470                         " +$filesize; " \
 471                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 472                         " $filesize\0"  \
 473         "fdtaddr=780000\0"                                              \
 474         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 475         "console=ttyS0\0"                                               \
 476         "setbootargs=setenv bootargs "                                  \
 477                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 478         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 479                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 480                                                         "$netdev:off " \
 481                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 482
 483 #define CONFIG_NFSBOOTCOMMAND                                           \
 484         "setenv rootdev /dev/nfs;"                                      \
 485         "run setbootargs;"                                              \
 486         "run setipargs;"                                                \
 487         "tftp $loadaddr $bootfile;"                                     \
 488         "tftp $fdtaddr $fdtfile;"                                       \
 489         "bootm $loadaddr - $fdtaddr"
 490
 491 #define CONFIG_RAMBOOTCOMMAND                                           \
 492         "setenv rootdev /dev/ram;"                                      \
 493         "run setbootargs;"                                              \
 494         "tftp $ramdiskaddr $ramdiskfile;"                               \
 495         "tftp $loadaddr $bootfile;"                                     \
 496         "tftp $fdtaddr $fdtfile;"                                       \
 497         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 498
 499 #endif  /* __CONFIG_H */