include/configs/MPC8313ERDB_NAND.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16
  17 #define CONFIG_SPL_INIT_MINIMAL
  18 #define CONFIG_SPL_FLUSH_IMAGE
  19 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  20 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  21
  22 #ifdef CONFIG_SPL_BUILD
  23 #define CONFIG_NS16550_MIN_FUNCTIONS
  24 #endif
  25
  26 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  27 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
  28 #define CONFIG_SPL_PAD_TO       0x4000
  29
  30 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  31 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  33 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  34 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  35 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  36
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  39 #endif
  40
  41 #ifndef CONFIG_SYS_MONITOR_BASE
  42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  43 #endif
  44
  45 #define CONFIG_PCI_INDIRECT_BRIDGE
  46 #define CONFIG_FSL_ELBC 1
  47
  48 /*
  49  * On-board devices
  50  *
  51  * TSEC1 is VSC switch
  52  * TSEC2 is SoC TSEC
  53  */
  54 #define CONFIG_VSC7385_ENET
  55 #define CONFIG_TSEC2
  56
  57 #ifdef CONFIG_SYS_66MHZ
  58 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  59 #elif defined(CONFIG_SYS_33MHZ)
  60 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
  61 #else
  62 #error Unknown oscillator frequency.
  63 #endif
  64
  65 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  66
  67 #define CONFIG_SYS_IMMR         0xE0000000
  68
  69 #if !defined(CONFIG_SPL_BUILD)
  70 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  71 #endif
  72
  73 #define CONFIG_SYS_MEMTEST_START        0x00001000
  74 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  75
  76 /* Early revs of this board will lock up hard when attempting
  77  * to access the PMC registers, unless a JTAG debugger is
  78  * connected, or some resistor modifications are made.
  79  */
  80 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  81
  82 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  83 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  84
  85 /*
  86  * Device configurations
  87  */
  88
  89 /* Vitesse 7385 */
  90
  91 #ifdef CONFIG_VSC7385_ENET
  92
  93 #define CONFIG_TSEC1
  94
  95 /* The flash address and size of the VSC7385 firmware image */
  96 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  97 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  98
  99 #endif
 100
 101 /*
 102  * DDR Setup
 103  */
 104 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 105 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 106 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 107
 108 /*
 109  * Manually set up DDR parameters, as this board does not
 110  * seem to have the SPD connected to I2C.
 111  */
 112 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
 113 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 114                                 | CSCONFIG_ODT_RD_NEVER \
 115                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 116                                 | CSCONFIG_ROW_BIT_13 \
 117                                 | CSCONFIG_COL_BIT_10)
 118                                 /* 0x80010102 */
 119
 120 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 121 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 122                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 123                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 124                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 125                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 126                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 127                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 128                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 129                                 /* 0x00220802 */
 130 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 131                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 132                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 133                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 134                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 135                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 136                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 137                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 138                                 /* 0x3835a322 */
 139 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 140                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 141                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 142                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 143                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 144                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 145                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 146                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 147 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 148                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 149                                 /* 0x05100500 */
 150 #if defined(CONFIG_DDR_2T_TIMING)
 151 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 152                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 153                                 | SDRAM_CFG_DBW_32 \
 154                                 | SDRAM_CFG_2T_EN)
 155                                 /* 0x43088000 */
 156 #else
 157 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 158                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 159                                 | SDRAM_CFG_DBW_32)
 160                                 /* 0x43080000 */
 161 #endif
 162 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 163 /* set burst length to 8 for 32-bit data path */
 164 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 165                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 166                                 /* 0x44480632 */
 167 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 168
 169 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 170                                 /*0x02000000*/
 171 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 172                                 | DDRCDR_PZ_NOMZ \
 173                                 | DDRCDR_NZ_NOMZ \
 174                                 | DDRCDR_M_ODR)
 175
 176 /*
 177  * FLASH on the Local Bus
 178  */
 179 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 180 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 181 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 182
 183 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE \
 184                                         | BR_PS_16      /* 16 bit port */ \
 185                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 186                                         | BR_V)         /* valid */
 187 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 188                                 | OR_GPCM_XACS \
 189                                 | OR_GPCM_SCY_9 \
 190                                 | OR_GPCM_EHTR \
 191                                 | OR_GPCM_EAD)
 192                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 193                                         /* window base at flash base */
 194 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 195                                         /* 16 MB window size */
 196 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 197
 198 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 199 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 200
 201 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 202 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 203
 204 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 205         !defined(CONFIG_SPL_BUILD)
 206 #define CONFIG_SYS_RAMBOOT
 207 #endif
 208
 209 #define CONFIG_SYS_INIT_RAM_LOCK        1
 210 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 211 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 212
 213 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 214                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 215 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 216
 217 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 218 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 219 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 220
 221 /*
 222  * Local Bus LCRR and LBCR regs
 223  */
 224 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 225 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 226 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 227                                 | (0xFF << LBCR_BMT_SHIFT) \
 228                                 | 0xF)  /* 0x0004ff0f */
 229
 230                                 /* LB refresh timer prescal, 266MHz/32 */
 231 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 232
 233 /* drivers/mtd/nand/raw/nand.c */
 234 #if defined(CONFIG_SPL_BUILD)
 235 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 236 #else
 237 #define CONFIG_SYS_NAND_BASE            0xE2800000
 238 #endif
 239
 240 #define CONFIG_MTD_PARTITION
 241
 242 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 243 #define CONFIG_NAND_FSL_ELBC 1
 244 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 245 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 246
 247 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_NAND_BASE \
 248                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 249                                 | BR_PS_8               /* 8 bit port */ \
 250                                 | BR_MS_FCM             /* MSEL = FCM */ \
 251                                 | BR_V)                 /* valid */
 252 #define CONFIG_SYS_OR0_PRELIM   \
 253                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 254                                 | OR_FCM_CSCT \
 255                                 | OR_FCM_CST \
 256                                 | OR_FCM_CHT \
 257                                 | OR_FCM_SCY_1 \
 258                                 | OR_FCM_TRLX \
 259                                 | OR_FCM_EHTR)
 260                                 /* 0xFFFF8396 */
 261
 262 /* Still needed for spl_minimal.c */
 263 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
 264 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
 265
 266 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 267 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 268
 269 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 270 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 271
 272 /* local bus write LED / read status buffer (BCSR) mapping */
 273 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 274 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 275                                         /* map at 0xFA000000 on LCS3 */
 276 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
 277                                         | BR_PS_8       /* 8 bit port */ \
 278                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 279                                         | BR_V)         /* valid */
 280                                         /* 0xFA000801 */
 281 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
 282                                         | OR_GPCM_CSNT \
 283                                         | OR_GPCM_ACS_DIV2 \
 284                                         | OR_GPCM_XACS \
 285                                         | OR_GPCM_SCY_15 \
 286                                         | OR_GPCM_TRLX_SET \
 287                                         | OR_GPCM_EHTR_SET \
 288                                         | OR_GPCM_EAD)
 289                                         /* 0xFFFF8FF7 */
 290 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
 291 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 292
 293 /* Vitesse 7385 */
 294
 295 #ifdef CONFIG_VSC7385_ENET
 296
 297                                         /* VSC7385 Base address on LCS2 */
 298 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 299 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 300
 301 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 302                                         | BR_PS_8       /* 8 bit port */ \
 303                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 304                                         | BR_V)         /* valid */
 305 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 306                                         | OR_GPCM_CSNT \
 307                                         | OR_GPCM_XACS \
 308                                         | OR_GPCM_SCY_15 \
 309                                         | OR_GPCM_SETA \
 310                                         | OR_GPCM_TRLX_SET \
 311                                         | OR_GPCM_EHTR_SET \
 312                                         | OR_GPCM_EAD)
 313                                         /* 0xFFFE09FF */
 314
 315                                         /* Access window base at VSC7385 base */
 316 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 317 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 318
 319 #endif
 320
 321 #define CONFIG_MPC83XX_GPIO 1
 322
 323 /*
 324  * Serial Port
 325  */
 326 #define CONFIG_SYS_NS16550_SERIAL
 327 #define CONFIG_SYS_NS16550_REG_SIZE     1
 328
 329 #define CONFIG_SYS_BAUDRATE_TABLE       \
 330         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 331
 332 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 333 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 334
 335 /* I2C */
 336 #define CONFIG_SYS_I2C
 337 #define CONFIG_SYS_I2C_FSL
 338 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 339 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 340 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 341 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 342 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 343 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 344 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 345
 346 /*
 347  * General PCI
 348  * Addresses are mapped 1-1.
 349  */
 350 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 351 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 352 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 353 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 354 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 355 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 356 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 357 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 358 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 359
 360 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 361
 362 /*
 363  * TSEC
 364  */
 365
 366 #define CONFIG_GMII                     /* MII PHY management */
 367
 368 #ifdef CONFIG_TSEC1
 369 #define CONFIG_HAS_ETH0
 370 #define CONFIG_TSEC1_NAME       "TSEC0"
 371 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 372 #define TSEC1_PHY_ADDR          0x1c
 373 #define TSEC1_FLAGS             TSEC_GIGABIT
 374 #define TSEC1_PHYIDX            0
 375 #endif
 376
 377 #ifdef CONFIG_TSEC2
 378 #define CONFIG_HAS_ETH1
 379 #define CONFIG_TSEC2_NAME       "TSEC1"
 380 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 381 #define TSEC2_PHY_ADDR          4
 382 #define TSEC2_FLAGS             TSEC_GIGABIT
 383 #define TSEC2_PHYIDX            0
 384 #endif
 385
 386 /* Options are: TSEC[0-1] */
 387 #define CONFIG_ETHPRIME                 "TSEC1"
 388
 389 /*
 390  * Configure on-board RTC
 391  */
 392 #define CONFIG_RTC_DS1337
 393 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 394
 395 /*
 396  * Environment
 397  */
 398 #define CONFIG_ENV_OFFSET               (512 * 1024)
 399 #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 400 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 401 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 402 #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 403 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 404
 405 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 406 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 407
 408 /*
 409  * BOOTP options
 410  */
 411 #define CONFIG_BOOTP_BOOTFILESIZE
 412
 413 /*
 414  * Command line configuration.
 415  */
 416
 417 /*
 418  * Miscellaneous configurable options
 419  */
 420 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 421 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 422
 423                                 /* Boot Argument Buffer Size */
 424 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 425
 426 /*
 427  * For booting Linux, the board info and command line data
 428  * have to be in the first 256 MB of memory, since this is
 429  * the maximum mapped by the Linux kernel during initialization.
 430  */
 431                                 /* Initial Memory map for Linux*/
 432 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 433 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 434
 435 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 436
 437 #ifdef CONFIG_SYS_66MHZ
 438
 439 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 440 /* 0x62040000 */
 441 #define CONFIG_SYS_HRCW_LOW (\
 442         0x20000000 /* reserved, must be set */ |\
 443         HRCWL_DDRCM |\
 444         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 445         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 446         HRCWL_CSB_TO_CLKIN_2X1 |\
 447         HRCWL_CORE_TO_CSB_2X1)
 448
 449 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 450
 451 #elif defined(CONFIG_SYS_33MHZ)
 452
 453 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 454 /* 0x65040000 */
 455 #define CONFIG_SYS_HRCW_LOW (\
 456         0x20000000 /* reserved, must be set */ |\
 457         HRCWL_DDRCM |\
 458         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 459         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 460         HRCWL_CSB_TO_CLKIN_5X1 |\
 461         HRCWL_CORE_TO_CSB_2X1)
 462
 463 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 464
 465 #endif
 466
 467 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 468         HRCWH_PCI_HOST |\
 469         HRCWH_PCI1_ARBITER_ENABLE |\
 470         HRCWH_CORE_ENABLE |\
 471         HRCWH_BOOTSEQ_DISABLE |\
 472         HRCWH_SW_WATCHDOG_DISABLE |\
 473         HRCWH_TSEC1M_IN_RGMII |\
 474         HRCWH_TSEC2M_IN_RGMII |\
 475         HRCWH_BIG_ENDIAN)
 476
 477 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 478                        HRCWH_FROM_0XFFF00100 |\
 479                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
 480                        HRCWH_RL_EXT_NAND)
 481
 482 /* System IO Config */
 483 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 484                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 485 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 486
 487 #define CONFIG_SYS_HID0_INIT    0x000000000
 488 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 489                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 490                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 491
 492 #define CONFIG_SYS_HID2 HID2_HBE
 493
 494 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 495
 496 /* DDR @ 0x00000000 */
 497 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 498 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 499                                 | BATU_BL_256M \
 500                                 | BATU_VS \
 501                                 | BATU_VP)
 502
 503 /* PCI @ 0x80000000 */
 504 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 505 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 506                                 | BATU_BL_256M \
 507                                 | BATU_VS \
 508                                 | BATU_VP)
 509 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 510                                 | BATL_PP_RW \
 511                                 | BATL_CACHEINHIBIT \
 512                                 | BATL_GUARDEDSTORAGE)
 513 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 514                                 | BATU_BL_256M \
 515                                 | BATU_VS \
 516                                 | BATU_VP)
 517
 518 /* PCI2 not supported on 8313 */
 519 #define CONFIG_SYS_IBAT3L       (0)
 520 #define CONFIG_SYS_IBAT3U       (0)
 521 #define CONFIG_SYS_IBAT4L       (0)
 522 #define CONFIG_SYS_IBAT4U       (0)
 523
 524 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 525 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 526                                 | BATL_PP_RW \
 527                                 | BATL_CACHEINHIBIT \
 528                                 | BATL_GUARDEDSTORAGE)
 529 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 530                                 | BATU_BL_256M \
 531                                 | BATU_VS \
 532                                 | BATU_VP)
 533
 534 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 535 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 536 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 537
 538 #define CONFIG_SYS_IBAT7L       (0)
 539 #define CONFIG_SYS_IBAT7U       (0)
 540
 541 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 542 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 543 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 544 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 545 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 546 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 547 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 548 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 549 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 550 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 551 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 552 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 553 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 554 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 555 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 556 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 557
 558 /*
 559  * Environment Configuration
 560  */
 561 #define CONFIG_ENV_OVERWRITE
 562
 563 #define CONFIG_NETDEV           "eth1"
 564
 565 #define CONFIG_HOSTNAME         "mpc8313erdb"
 566 #define CONFIG_ROOTPATH         "/nfs/root/path"
 567 #define CONFIG_BOOTFILE         "uImage"
 568                                 /* U-Boot image on TFTP server */
 569 #define CONFIG_UBOOTPATH        "u-boot.bin"
 570 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 571
 572                                 /* default location for tftp and bootm */
 573 #define CONFIG_LOADADDR         800000
 574
 575 #define CONFIG_EXTRA_ENV_SETTINGS \
 576         "netdev=" CONFIG_NETDEV "\0"                                    \
 577         "ethprime=TSEC1\0"                                              \
 578         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 579         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 580                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 581                         " +$filesize; " \
 582                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 583                         " +$filesize; " \
 584                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 585                         " $filesize; "  \
 586                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 587                         " +$filesize; " \
 588                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 589                         " $filesize\0"  \
 590         "fdtaddr=780000\0"                                              \
 591         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 592         "console=ttyS0\0"                                               \
 593         "setbootargs=setenv bootargs "                                  \
 594                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 595         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 596                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 597                                                         "$netdev:off " \
 598                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 599
 600 #define CONFIG_NFSBOOTCOMMAND                                           \
 601         "setenv rootdev /dev/nfs;"                                      \
 602         "run setbootargs;"                                              \
 603         "run setipargs;"                                                \
 604         "tftp $loadaddr $bootfile;"                                     \
 605         "tftp $fdtaddr $fdtfile;"                                       \
 606         "bootm $loadaddr - $fdtaddr"
 607
 608 #define CONFIG_RAMBOOTCOMMAND                                           \
 609         "setenv rootdev /dev/ram;"                                      \
 610         "run setbootargs;"                                              \
 611         "tftp $ramdiskaddr $ramdiskfile;"                               \
 612         "tftp $loadaddr $bootfile;"                                     \
 613         "tftp $fdtaddr $fdtfile;"                                       \
 614         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 615
 616 #endif  /* __CONFIG_H */