include/configs/MPC8313ERDB.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 /*
   7  * mpc8313epb board configuration file
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_E300             1
  17 #define CONFIG_MPC831x          1
  18 #define CONFIG_MPC8313          1
  19 #define CONFIG_MPC8313ERDB      1
  20
  21 #ifdef CONFIG_NAND
  22 #define CONFIG_SPL_INIT_MINIMAL
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  25 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  26
  27 #ifdef CONFIG_SPL_BUILD
  28 #define CONFIG_NS16550_MIN_FUNCTIONS
  29 #endif
  30
  31 #define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
  32 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  33 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
  34 #define CONFIG_SPL_PAD_TO       0x4000
  35
  36 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  37 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  38 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  39 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  40 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  41 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  42
  43 #ifdef CONFIG_SPL_BUILD
  44 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  45 #endif
  46
  47 #endif /* CONFIG_NAND */
  48
  49 #ifndef CONFIG_SYS_TEXT_BASE
  50 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  51 #endif
  52
  53 #ifndef CONFIG_SYS_MONITOR_BASE
  54 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  55 #endif
  56
  57 #define CONFIG_PCI_INDIRECT_BRIDGE
  58 #define CONFIG_FSL_ELBC 1
  59
  60 #define CONFIG_MISC_INIT_R
  61
  62 /*
  63  * On-board devices
  64  *
  65  * TSEC1 is VSC switch
  66  * TSEC2 is SoC TSEC
  67  */
  68 #define CONFIG_VSC7385_ENET
  69 #define CONFIG_TSEC2
  70
  71 #ifdef CONFIG_SYS_66MHZ
  72 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  73 #elif defined(CONFIG_SYS_33MHZ)
  74 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
  75 #else
  76 #error Unknown oscillator frequency.
  77 #endif
  78
  79 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  80
  81 #define CONFIG_BOARD_EARLY_INIT_R               /* call board_early_init_r */
  82
  83 #define CONFIG_SYS_IMMR         0xE0000000
  84
  85 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
  86 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  87 #endif
  88
  89 #define CONFIG_SYS_MEMTEST_START        0x00001000
  90 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  91
  92 /* Early revs of this board will lock up hard when attempting
  93  * to access the PMC registers, unless a JTAG debugger is
  94  * connected, or some resistor modifications are made.
  95  */
  96 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  97
  98 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  99 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
 100
 101 /*
 102  * Device configurations
 103  */
 104
 105 /* Vitesse 7385 */
 106
 107 #ifdef CONFIG_VSC7385_ENET
 108
 109 #define CONFIG_TSEC1
 110
 111 /* The flash address and size of the VSC7385 firmware image */
 112 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 113 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 114
 115 #endif
 116
 117 /*
 118  * DDR Setup
 119  */
 120 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 121 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 122 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 123
 124 /*
 125  * Manually set up DDR parameters, as this board does not
 126  * seem to have the SPD connected to I2C.
 127  */
 128 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
 129 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 130                                 | CSCONFIG_ODT_RD_NEVER \
 131                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 132                                 | CSCONFIG_ROW_BIT_13 \
 133                                 | CSCONFIG_COL_BIT_10)
 134                                 /* 0x80010102 */
 135
 136 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 137 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 138                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 139                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 140                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 141                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 142                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 143                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 144                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 145                                 /* 0x00220802 */
 146 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 147                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 148                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 149                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 150                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 151                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 152                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 153                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 154                                 /* 0x3835a322 */
 155 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 156                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 157                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 158                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 159                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 160                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 161                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 162                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 163 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 164                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 165                                 /* 0x05100500 */
 166 #if defined(CONFIG_DDR_2T_TIMING)
 167 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 168                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 169                                 | SDRAM_CFG_DBW_32 \
 170                                 | SDRAM_CFG_2T_EN)
 171                                 /* 0x43088000 */
 172 #else
 173 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 174                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 175                                 | SDRAM_CFG_DBW_32)
 176                                 /* 0x43080000 */
 177 #endif
 178 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 179 /* set burst length to 8 for 32-bit data path */
 180 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 181                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 182                                 /* 0x44480632 */
 183 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 184
 185 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 186                                 /*0x02000000*/
 187 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 188                                 | DDRCDR_PZ_NOMZ \
 189                                 | DDRCDR_NZ_NOMZ \
 190                                 | DDRCDR_M_ODR)
 191
 192 /*
 193  * FLASH on the Local Bus
 194  */
 195 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 196 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 197 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 198 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 199 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 200 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 201 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
 202
 203 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 204                                         | BR_PS_16      /* 16 bit port */ \
 205                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 206                                         | BR_V)         /* valid */
 207 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 208                                 | OR_GPCM_XACS \
 209                                 | OR_GPCM_SCY_9 \
 210                                 | OR_GPCM_EHTR \
 211                                 | OR_GPCM_EAD)
 212                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 213                                         /* window base at flash base */
 214 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 215                                         /* 16 MB window size */
 216 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 217
 218 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 219 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 220
 221 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 222 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 223
 224 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 225         !defined(CONFIG_SPL_BUILD)
 226 #define CONFIG_SYS_RAMBOOT
 227 #endif
 228
 229 #define CONFIG_SYS_INIT_RAM_LOCK        1
 230 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 231 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 232
 233 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 234                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 235 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 236
 237 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 238 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 239 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 240
 241 /*
 242  * Local Bus LCRR and LBCR regs
 243  */
 244 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 245 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 246 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 247                                 | (0xFF << LBCR_BMT_SHIFT) \
 248                                 | 0xF)  /* 0x0004ff0f */
 249
 250                                 /* LB refresh timer prescal, 266MHz/32 */
 251 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 252
 253 /* drivers/mtd/nand/nand.c */
 254 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
 255 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 256 #else
 257 #define CONFIG_SYS_NAND_BASE            0xE2800000
 258 #endif
 259
 260 #define CONFIG_MTD_DEVICE
 261 #define CONFIG_MTD_PARTITION
 262 #define MTDIDS_DEFAULT                  "nand0=e2800000.flash"
 263 #define MTDPARTS_DEFAULT                \
 264         "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
 265
 266 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 267 #define CONFIG_NAND_FSL_ELBC 1
 268 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 269 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 270
 271 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 272                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 273                                 | BR_PS_8               /* 8 bit port */ \
 274                                 | BR_MS_FCM             /* MSEL = FCM */ \
 275                                 | BR_V)                 /* valid */
 276 #define CONFIG_SYS_NAND_OR_PRELIM       \
 277                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 278                                 | OR_FCM_CSCT \
 279                                 | OR_FCM_CST \
 280                                 | OR_FCM_CHT \
 281                                 | OR_FCM_SCY_1 \
 282                                 | OR_FCM_TRLX \
 283                                 | OR_FCM_EHTR)
 284                                 /* 0xFFFF8396 */
 285
 286 #ifdef CONFIG_NAND
 287 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 288 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 289 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 290 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 291 #else
 292 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 293 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 294 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 295 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 296 #endif
 297
 298 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 299 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 300
 301 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 302 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 303
 304 /* local bus write LED / read status buffer (BCSR) mapping */
 305 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 306 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 307                                         /* map at 0xFA000000 on LCS3 */
 308 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
 309                                         | BR_PS_8       /* 8 bit port */ \
 310                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 311                                         | BR_V)         /* valid */
 312                                         /* 0xFA000801 */
 313 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
 314                                         | OR_GPCM_CSNT \
 315                                         | OR_GPCM_ACS_DIV2 \
 316                                         | OR_GPCM_XACS \
 317                                         | OR_GPCM_SCY_15 \
 318                                         | OR_GPCM_TRLX_SET \
 319                                         | OR_GPCM_EHTR_SET \
 320                                         | OR_GPCM_EAD)
 321                                         /* 0xFFFF8FF7 */
 322 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
 323 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 324
 325 /* Vitesse 7385 */
 326
 327 #ifdef CONFIG_VSC7385_ENET
 328
 329                                         /* VSC7385 Base address on LCS2 */
 330 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 331 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 332
 333 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 334                                         | BR_PS_8       /* 8 bit port */ \
 335                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 336                                         | BR_V)         /* valid */
 337 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 338                                         | OR_GPCM_CSNT \
 339                                         | OR_GPCM_XACS \
 340                                         | OR_GPCM_SCY_15 \
 341                                         | OR_GPCM_SETA \
 342                                         | OR_GPCM_TRLX_SET \
 343                                         | OR_GPCM_EHTR_SET \
 344                                         | OR_GPCM_EAD)
 345                                         /* 0xFFFE09FF */
 346
 347                                         /* Access window base at VSC7385 base */
 348 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 349 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 350
 351 #endif
 352
 353 #define CONFIG_MPC83XX_GPIO 1
 354
 355 /*
 356  * Serial Port
 357  */
 358 #define CONFIG_CONS_INDEX       1
 359 #define CONFIG_SYS_NS16550_SERIAL
 360 #define CONFIG_SYS_NS16550_REG_SIZE     1
 361
 362 #define CONFIG_SYS_BAUDRATE_TABLE       \
 363         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 364
 365 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 366 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 367
 368 /* I2C */
 369 #define CONFIG_SYS_I2C
 370 #define CONFIG_SYS_I2C_FSL
 371 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 372 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 373 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 374 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 375 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 376 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 377 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 378
 379 /*
 380  * General PCI
 381  * Addresses are mapped 1-1.
 382  */
 383 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 384 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 385 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 386 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 387 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 388 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 389 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 390 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 391 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 392
 393 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 394
 395 /*
 396  * TSEC
 397  */
 398 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 399
 400 #define CONFIG_GMII                     /* MII PHY management */
 401
 402 #ifdef CONFIG_TSEC1
 403 #define CONFIG_HAS_ETH0
 404 #define CONFIG_TSEC1_NAME       "TSEC0"
 405 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 406 #define TSEC1_PHY_ADDR          0x1c
 407 #define TSEC1_FLAGS             TSEC_GIGABIT
 408 #define TSEC1_PHYIDX            0
 409 #endif
 410
 411 #ifdef CONFIG_TSEC2
 412 #define CONFIG_HAS_ETH1
 413 #define CONFIG_TSEC2_NAME       "TSEC1"
 414 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 415 #define TSEC2_PHY_ADDR          4
 416 #define TSEC2_FLAGS             TSEC_GIGABIT
 417 #define TSEC2_PHYIDX            0
 418 #endif
 419
 420 /* Options are: TSEC[0-1] */
 421 #define CONFIG_ETHPRIME                 "TSEC1"
 422
 423 /*
 424  * Configure on-board RTC
 425  */
 426 #define CONFIG_RTC_DS1337
 427 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 428
 429 /*
 430  * Environment
 431  */
 432 #if defined(CONFIG_NAND)
 433         #define CONFIG_ENV_OFFSET               (512 * 1024)
 434         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 435         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 436         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 437         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 438         #define CONFIG_ENV_OFFSET_REDUND        \
 439                                         (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 440 #elif !defined(CONFIG_SYS_RAMBOOT)
 441         #define CONFIG_ENV_ADDR         \
 442                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 443         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 444         #define CONFIG_ENV_SIZE         0x2000
 445
 446 /* Address and size of Redundant Environment Sector */
 447 #else
 448         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 449         #define CONFIG_ENV_SIZE         0x2000
 450 #endif
 451
 452 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 453 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 454
 455 /*
 456  * BOOTP options
 457  */
 458 #define CONFIG_BOOTP_BOOTFILESIZE
 459 #define CONFIG_BOOTP_BOOTPATH
 460 #define CONFIG_BOOTP_GATEWAY
 461 #define CONFIG_BOOTP_HOSTNAME
 462
 463 /*
 464  * Command line configuration.
 465  */
 466
 467 #define CONFIG_CMDLINE_EDITING 1
 468 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
 469
 470 /*
 471  * Miscellaneous configurable options
 472  */
 473 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 474 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 475 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 476
 477                                                 /* Print Buffer Size */
 478 #define CONFIG_SYS_PBSIZE       \
 479                         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 480 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 481                                 /* Boot Argument Buffer Size */
 482 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 483
 484 /*
 485  * For booting Linux, the board info and command line data
 486  * have to be in the first 256 MB of memory, since this is
 487  * the maximum mapped by the Linux kernel during initialization.
 488  */
 489                                 /* Initial Memory map for Linux*/
 490 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 491 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 492
 493 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 494
 495 #ifdef CONFIG_SYS_66MHZ
 496
 497 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 498 /* 0x62040000 */
 499 #define CONFIG_SYS_HRCW_LOW (\
 500         0x20000000 /* reserved, must be set */ |\
 501         HRCWL_DDRCM |\
 502         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 503         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 504         HRCWL_CSB_TO_CLKIN_2X1 |\
 505         HRCWL_CORE_TO_CSB_2X1)
 506
 507 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 508
 509 #elif defined(CONFIG_SYS_33MHZ)
 510
 511 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 512 /* 0x65040000 */
 513 #define CONFIG_SYS_HRCW_LOW (\
 514         0x20000000 /* reserved, must be set */ |\
 515         HRCWL_DDRCM |\
 516         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 517         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 518         HRCWL_CSB_TO_CLKIN_5X1 |\
 519         HRCWL_CORE_TO_CSB_2X1)
 520
 521 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 522
 523 #endif
 524
 525 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 526         HRCWH_PCI_HOST |\
 527         HRCWH_PCI1_ARBITER_ENABLE |\
 528         HRCWH_CORE_ENABLE |\
 529         HRCWH_BOOTSEQ_DISABLE |\
 530         HRCWH_SW_WATCHDOG_DISABLE |\
 531         HRCWH_TSEC1M_IN_RGMII |\
 532         HRCWH_TSEC2M_IN_RGMII |\
 533         HRCWH_BIG_ENDIAN)
 534
 535 #ifdef CONFIG_NAND
 536 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 537                        HRCWH_FROM_0XFFF00100 |\
 538                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
 539                        HRCWH_RL_EXT_NAND)
 540 #else
 541 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 542                        HRCWH_FROM_0X00000100 |\
 543                        HRCWH_ROM_LOC_LOCAL_16BIT |\
 544                        HRCWH_RL_EXT_LEGACY)
 545 #endif
 546
 547 /* System IO Config */
 548 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 549                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 550 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 551
 552 #define CONFIG_SYS_HID0_INIT    0x000000000
 553 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 554                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 555                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 556
 557 #define CONFIG_SYS_HID2 HID2_HBE
 558
 559 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 560
 561 /* DDR @ 0x00000000 */
 562 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 563 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 564                                 | BATU_BL_256M \
 565                                 | BATU_VS \
 566                                 | BATU_VP)
 567
 568 /* PCI @ 0x80000000 */
 569 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 570 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 571                                 | BATU_BL_256M \
 572                                 | BATU_VS \
 573                                 | BATU_VP)
 574 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 575                                 | BATL_PP_RW \
 576                                 | BATL_CACHEINHIBIT \
 577                                 | BATL_GUARDEDSTORAGE)
 578 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 579                                 | BATU_BL_256M \
 580                                 | BATU_VS \
 581                                 | BATU_VP)
 582
 583 /* PCI2 not supported on 8313 */
 584 #define CONFIG_SYS_IBAT3L       (0)
 585 #define CONFIG_SYS_IBAT3U       (0)
 586 #define CONFIG_SYS_IBAT4L       (0)
 587 #define CONFIG_SYS_IBAT4U       (0)
 588
 589 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 590 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 591                                 | BATL_PP_RW \
 592                                 | BATL_CACHEINHIBIT \
 593                                 | BATL_GUARDEDSTORAGE)
 594 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 595                                 | BATU_BL_256M \
 596                                 | BATU_VS \
 597                                 | BATU_VP)
 598
 599 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 600 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 601 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 602
 603 #define CONFIG_SYS_IBAT7L       (0)
 604 #define CONFIG_SYS_IBAT7U       (0)
 605
 606 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 607 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 608 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 609 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 610 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 611 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 612 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 613 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 614 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 615 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 616 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 617 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 618 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 619 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 620 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 621 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 622
 623 /*
 624  * Environment Configuration
 625  */
 626 #define CONFIG_ENV_OVERWRITE
 627
 628 #define CONFIG_NETDEV           "eth1"
 629
 630 #define CONFIG_HOSTNAME         mpc8313erdb
 631 #define CONFIG_ROOTPATH         "/nfs/root/path"
 632 #define CONFIG_BOOTFILE         "uImage"
 633                                 /* U-Boot image on TFTP server */
 634 #define CONFIG_UBOOTPATH        "u-boot.bin"
 635 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 636
 637                                 /* default location for tftp and bootm */
 638 #define CONFIG_LOADADDR         800000
 639
 640 #define CONFIG_EXTRA_ENV_SETTINGS \
 641         "netdev=" CONFIG_NETDEV "\0"                                    \
 642         "ethprime=TSEC1\0"                                              \
 643         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 644         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 645                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 646                         " +$filesize; " \
 647                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 648                         " +$filesize; " \
 649                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 650                         " $filesize; "  \
 651                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 652                         " +$filesize; " \
 653                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 654                         " $filesize\0"  \
 655         "fdtaddr=780000\0"                                              \
 656         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 657         "console=ttyS0\0"                                               \
 658         "setbootargs=setenv bootargs "                                  \
 659                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 660         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 661                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 662                                                         "$netdev:off " \
 663                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 664
 665 #define CONFIG_NFSBOOTCOMMAND                                           \
 666         "setenv rootdev /dev/nfs;"                                      \
 667         "run setbootargs;"                                              \
 668         "run setipargs;"                                                \
 669         "tftp $loadaddr $bootfile;"                                     \
 670         "tftp $fdtaddr $fdtfile;"                                       \
 671         "bootm $loadaddr - $fdtaddr"
 672
 673 #define CONFIG_RAMBOOTCOMMAND                                           \
 674         "setenv rootdev /dev/ram;"                                      \
 675         "run setbootargs;"                                              \
 676         "tftp $ramdiskaddr $ramdiskfile;"                               \
 677         "tftp $loadaddr $bootfile;"                                     \
 678         "tftp $fdtaddr $fdtfile;"                                       \
 679         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 680
 681 #endif  /* __CONFIG_H */