include/configs/MPC8308RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #ifdef CONFIG_MMC
  17 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  18 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
  19 #endif
  20
  21 /*
  22  * On-board devices
  23  *
  24  * TSEC1 is SoC TSEC
  25  * TSEC2 is VSC switch
  26  */
  27 #define CONFIG_TSEC1
  28 #define CONFIG_VSC7385_ENET
  29
  30 /*
  31  * System IO Config
  32  */
  33 #define CONFIG_SYS_SICRH (\
  34         SICRH_ESDHC_A_SD |\
  35         SICRH_ESDHC_B_SD |\
  36         SICRH_ESDHC_C_SD |\
  37         SICRH_GPIO_A_TSEC2 |\
  38         SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
  39         SICRH_IEEE1588_A_GPIO |\
  40         SICRH_USB |\
  41         SICRH_GTM_GPIO |\
  42         SICRH_IEEE1588_B_GPIO |\
  43         SICRH_ETSEC2_CRS |\
  44         SICRH_GPIOSEL_1 |\
  45         SICRH_TMROBI_V3P3 |\
  46         SICRH_TSOBI1_V2P5 |\
  47         SICRH_TSOBI2_V2P5)      /* 0x01b7d103 */
  48 #define CONFIG_SYS_SICRL (\
  49         SICRL_SPI_PF0 |\
  50         SICRL_UART_PF0 |\
  51         SICRL_IRQ_PF0 |\
  52         SICRL_I2C2_PF0 |\
  53         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000040 */
  54
  55 /*
  56  * IMMR new address
  57  */
  58 #define CONFIG_SYS_IMMR         0xE0000000
  59
  60 /*
  61  * SERDES
  62  */
  63 #define CONFIG_FSL_SERDES
  64 #define CONFIG_FSL_SERDES1      0xe3000
  65
  66 /*
  67  * Arbiter Setup
  68  */
  69 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  70 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  71 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  72
  73 /*
  74  * DDR Setup
  75  */
  76 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  77 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  78 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  79 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  80 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  81                                 | DDRCDR_PZ_LOZ \
  82                                 | DDRCDR_NZ_LOZ \
  83                                 | DDRCDR_ODT \
  84                                 | DDRCDR_Q_DRN)
  85                                 /* 0x7b880001 */
  86 /*
  87  * Manually set up DDR parameters
  88  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  89  */
  90
  91 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  92
  93 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  94 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  95                                 | CSCONFIG_ODT_RD_NEVER \
  96                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  97                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  98                                 /* 0x80010102 */
  99 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 100 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 101                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 102                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 103                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 104                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 105                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 106                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 107                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 108                                 /* 0x00220802 */
 109 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 110                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 111                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 112                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 113                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 114                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 115                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 116                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 117                                 /* 0x27256222 */
 118 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 119                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 120                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 121                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 122                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 123                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 124                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 125                                 /* 0x121048c5 */
 126 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 127                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 128                                 /* 0x03600100 */
 129 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 130                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 131                                 | SDRAM_CFG_DBW_32)
 132                                 /* 0x43080000 */
 133
 134 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 135 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 136                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 137                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 138 #define CONFIG_SYS_DDR_MODE2            0x00000000
 139
 140 /*
 141  * Memory test
 142  */
 143 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 144 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 145
 146 /*
 147  * The reserved memory
 148  */
 149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 150
 151 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 152 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 153
 154 /*
 155  * Initial RAM Base Address Setup
 156  */
 157 #define CONFIG_SYS_INIT_RAM_LOCK        1
 158 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 159 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 160 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 161         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 162
 163 /*
 164  * Local Bus Configuration & Clock Setup
 165  */
 166 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 167 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 168 #define CONFIG_SYS_LBC_LBCR             0x00040000
 169
 170 /*
 171  * FLASH on the Local Bus
 172  */
 173 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 174
 175 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 176 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
 177
 178
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 180 /* 127 64KB sectors and 8 8KB top sectors per device */
 181 #define CONFIG_SYS_MAX_FLASH_SECT       135
 182
 183 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 184 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 185
 186 /*
 187  * NAND Flash on the Local Bus
 188  */
 189 #define CONFIG_SYS_NAND_BASE    0xE0600000              /* 0xE0600000 */
 190 #define CONFIG_SYS_NAND_WINDOW_SIZE     (32 * 1024)     /* 0x00008000 */
 191                                 /* 0xFFFF8396 */
 192
 193 #ifdef CONFIG_VSC7385_ENET
 194 #define CONFIG_TSEC2
 195                                         /* VSC7385 Base address on CS2 */
 196 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 197 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024) /* 0x00020000 */
 198                                         /* 0xFFFE09FF */
 199 /* The flash address and size of the VSC7385 firmware image */
 200 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 201 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 202 #endif
 203 /*
 204  * Serial Port
 205  */
 206 #define CONFIG_SYS_NS16550_SERIAL
 207 #define CONFIG_SYS_NS16550_REG_SIZE     1
 208 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 209
 210 #define CONFIG_SYS_BAUDRATE_TABLE  \
 211         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 212
 213 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 214 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 215
 216 /* I2C */
 217 #define CONFIG_SYS_I2C
 218 #define CONFIG_SYS_I2C_FSL
 219 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 220 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 221 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 222 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 223 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 224 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 225 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 226
 227 /*
 228  * SPI on header J8
 229  *
 230  * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
 231  * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
 232  */
 233 #ifdef CONFIG_MPC8XXX_SPI
 234 #define CONFIG_USE_SPIFLASH
 235 #endif
 236
 237 /*
 238  * Board info - revision and where boot from
 239  */
 240 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 241
 242 /*
 243  * Config on-board RTC
 244  */
 245 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 246 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 247
 248 /*
 249  * General PCI
 250  * Addresses are mapped 1-1.
 251  */
 252 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 253 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 254 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 255 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 256 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 257 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 258 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 259 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 260 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 261
 262 /* enable PCIE clock */
 263 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 264
 265 #define CONFIG_PCI_INDIRECT_BRIDGE
 266 #define CONFIG_PCIE
 267
 268 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 269 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 270
 271 /*
 272  * TSEC
 273  */
 274 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 275 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 276 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 277 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 278
 279 /*
 280  * TSEC ethernet configuration
 281  */
 282 #define CONFIG_TSEC1_NAME       "eTSEC0"
 283 #define CONFIG_TSEC2_NAME       "eTSEC1"
 284 #define TSEC1_PHY_ADDR          2
 285 #define TSEC2_PHY_ADDR          1
 286 #define TSEC1_PHYIDX            0
 287 #define TSEC2_PHYIDX            0
 288 #define TSEC1_FLAGS             TSEC_GIGABIT
 289 #define TSEC2_FLAGS             TSEC_GIGABIT
 290
 291 /* Options are: eTSEC[0-1] */
 292 #define CONFIG_ETHPRIME         "eTSEC0"
 293
 294 /*
 295  * Environment
 296  */
 297 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 298                                  CONFIG_SYS_MONITOR_LEN)
 299 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 300 #define CONFIG_ENV_SIZE         0x2000
 301 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 302 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 303
 304 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 305 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 306
 307 /*
 308  * BOOTP options
 309  */
 310 #define CONFIG_BOOTP_BOOTFILESIZE
 311
 312 /*
 313  * Command line configuration.
 314  */
 315
 316 /*
 317  * Miscellaneous configurable options
 318  */
 319 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 320
 321 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 322
 323 /* Boot Argument Buffer Size */
 324 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 325
 326 /*
 327  * For booting Linux, the board info and command line data
 328  * have to be in the first 256 MB of memory, since this is
 329  * the maximum mapped by the Linux kernel during initialization.
 330  */
 331 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 332 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 333
 334 /*
 335  * Environment Configuration
 336  */
 337
 338 #define CONFIG_ENV_OVERWRITE
 339
 340 #if defined(CONFIG_TSEC_ENET)
 341 #define CONFIG_HAS_ETH0
 342 #define CONFIG_HAS_ETH1
 343 #endif
 344
 345 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 346
 347
 348 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 349         "netdev=eth0\0"                                                 \
 350         "consoledev=ttyS0\0"                                            \
 351         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 352                 "nfsroot=${serverip}:${rootpath}\0"                     \
 353         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 354         "addip=setenv bootargs ${bootargs} "                            \
 355                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 356                 ":${hostname}:${netdev}:off panic=1\0"                  \
 357         "addtty=setenv bootargs ${bootargs}"                            \
 358                 " console=${consoledev},${baudrate}\0"                  \
 359         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 360         "addmisc=setenv bootargs ${bootargs}\0"                         \
 361         "kernel_addr=FE080000\0"                                        \
 362         "fdt_addr=FE280000\0"                                           \
 363         "ramdisk_addr=FE290000\0"                                       \
 364         "u-boot=mpc8308rdb/u-boot.bin\0"                                \
 365         "kernel_addr_r=1000000\0"                                       \
 366         "fdt_addr_r=C00000\0"                                           \
 367         "hostname=mpc8308rdb\0"                                         \
 368         "bootfile=mpc8308rdb/uImage\0"                                  \
 369         "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"                           \
 370         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 371         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 372                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 373         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 374                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 375         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 376                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 377                 "run nfsargs addip addtty addmtd addmisc;"              \
 378                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 379         "bootcmd=run flash_self\0"                                      \
 380         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 381         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 382                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 383                 " +${filesize};cp.b ${fileaddr} "                       \
 384                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 385         "upd=run load update\0"                                         \
 386
 387 #endif  /* __CONFIG_H */