include/configs/MPC8308RDB.h

   1 /*
   2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   4  *
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1 /* E300 family */
  16 #define CONFIG_MPC830x          1 /* MPC830x family */
  17 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  18 #define CONFIG_MPC8308RDB       1 /* MPC8308RDB board specific */
  19
  20 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  21
  22 #define CONFIG_MISC_INIT_R
  23
  24 #ifdef CONFIG_MMC
  25 #define CONFIG_FSL_ESDHC
  26 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  27 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
  28
  29 #define CONFIG_GENERIC_MMC
  30 #define CONFIG_DOS_PARTITION
  31 #endif
  32
  33 /*
  34  * On-board devices
  35  *
  36  * TSEC1 is SoC TSEC
  37  * TSEC2 is VSC switch
  38  */
  39 #define CONFIG_TSEC1
  40 #define CONFIG_VSC7385_ENET
  41
  42 /*
  43  * System Clock Setup
  44  */
  45 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  46 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  47
  48 /*
  49  * Hardware Reset Configuration Word
  50  * if CLKIN is 66.66MHz, then
  51  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  52  * We choose the A type silicon as default, so the core is 400Mhz.
  53  */
  54 #define CONFIG_SYS_HRCW_LOW (\
  55         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  56         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  57         HRCWL_SVCOD_DIV_2 |\
  58         HRCWL_CSB_TO_CLKIN_4X1 |\
  59         HRCWL_CORE_TO_CSB_3X1)
  60 /*
  61  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  62  * in 8308's HRCWH according to the manual, but original Freescale's
  63  * code has them and I've expirienced some problems using the board
  64  * with BDI3000 attached when I've tried to set these bits to zero
  65  * (UART doesn't work after the 'reset run' command).
  66  */
  67 #define CONFIG_SYS_HRCW_HIGH (\
  68         HRCWH_PCI_HOST |\
  69         HRCWH_PCI1_ARBITER_ENABLE |\
  70         HRCWH_CORE_ENABLE |\
  71         HRCWH_FROM_0X00000100 |\
  72         HRCWH_BOOTSEQ_DISABLE |\
  73         HRCWH_SW_WATCHDOG_DISABLE |\
  74         HRCWH_ROM_LOC_LOCAL_16BIT |\
  75         HRCWH_RL_EXT_LEGACY |\
  76         HRCWH_TSEC1M_IN_RGMII |\
  77         HRCWH_TSEC2M_IN_RGMII |\
  78         HRCWH_BIG_ENDIAN)
  79
  80 /*
  81  * System IO Config
  82  */
  83 #define CONFIG_SYS_SICRH (\
  84         SICRH_ESDHC_A_SD |\
  85         SICRH_ESDHC_B_SD |\
  86         SICRH_ESDHC_C_SD |\
  87         SICRH_GPIO_A_TSEC2 |\
  88         SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
  89         SICRH_IEEE1588_A_GPIO |\
  90         SICRH_USB |\
  91         SICRH_GTM_GPIO |\
  92         SICRH_IEEE1588_B_GPIO |\
  93         SICRH_ETSEC2_CRS |\
  94         SICRH_GPIOSEL_1 |\
  95         SICRH_TMROBI_V3P3 |\
  96         SICRH_TSOBI1_V2P5 |\
  97         SICRH_TSOBI2_V2P5)      /* 0x01b7d103 */
  98 #define CONFIG_SYS_SICRL (\
  99         SICRL_SPI_PF0 |\
 100         SICRL_UART_PF0 |\
 101         SICRL_IRQ_PF0 |\
 102         SICRL_I2C2_PF0 |\
 103         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000040 */
 104
 105 /*
 106  * IMMR new address
 107  */
 108 #define CONFIG_SYS_IMMR         0xE0000000
 109
 110 /*
 111  * SERDES
 112  */
 113 #define CONFIG_FSL_SERDES
 114 #define CONFIG_FSL_SERDES1      0xe3000
 115
 116 /*
 117  * Arbiter Setup
 118  */
 119 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 120 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 121 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 122
 123 /*
 124  * DDR Setup
 125  */
 126 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 127 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 128 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 129 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 130 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 131                                 | DDRCDR_PZ_LOZ \
 132                                 | DDRCDR_NZ_LOZ \
 133                                 | DDRCDR_ODT \
 134                                 | DDRCDR_Q_DRN)
 135                                 /* 0x7b880001 */
 136 /*
 137  * Manually set up DDR parameters
 138  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 139  */
 140
 141 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 142
 143 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 144 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 145                                 | CSCONFIG_ODT_RD_NEVER \
 146                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 147                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 148                                 /* 0x80010102 */
 149 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 150 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 151                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 152                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 153                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 154                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 155                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 156                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 157                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 158                                 /* 0x00220802 */
 159 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 160                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 161                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 162                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 163                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 164                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 165                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 166                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 167                                 /* 0x27256222 */
 168 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 169                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 170                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 171                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 172                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 173                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 174                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 175                                 /* 0x121048c5 */
 176 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 177                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 178                                 /* 0x03600100 */
 179 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 180                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 181                                 | SDRAM_CFG_DBW_32)
 182                                 /* 0x43080000 */
 183
 184 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 185 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 186                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 187                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 188 #define CONFIG_SYS_DDR_MODE2            0x00000000
 189
 190 /*
 191  * Memory test
 192  */
 193 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 194 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 195
 196 /*
 197  * The reserved memory
 198  */
 199 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 200
 201 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 202 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 203
 204 /*
 205  * Initial RAM Base Address Setup
 206  */
 207 #define CONFIG_SYS_INIT_RAM_LOCK        1
 208 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 209 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 210 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 211         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 212
 213 /*
 214  * Local Bus Configuration & Clock Setup
 215  */
 216 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 217 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 218 #define CONFIG_SYS_LBC_LBCR             0x00040000
 219
 220 /*
 221  * FLASH on the Local Bus
 222  */
 223 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 224 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 225 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 226
 227 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 228 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
 229 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 230
 231 /* Window base at flash base */
 232 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 233 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 234
 235 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 236                                 | BR_PS_16      /* 16 bit port */ \
 237                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 238                                 | BR_V)         /* valid */
 239 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 240                                 | OR_UPM_XAM \
 241                                 | OR_GPCM_CSNT \
 242                                 | OR_GPCM_ACS_DIV2 \
 243                                 | OR_GPCM_XACS \
 244                                 | OR_GPCM_SCY_15 \
 245                                 | OR_GPCM_TRLX_SET \
 246                                 | OR_GPCM_EHTR_SET)
 247
 248 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 249 /* 127 64KB sectors and 8 8KB top sectors per device */
 250 #define CONFIG_SYS_MAX_FLASH_SECT       135
 251
 252 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 253 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 254
 255 /*
 256  * NAND Flash on the Local Bus
 257  */
 258 #define CONFIG_SYS_NAND_BASE    0xE0600000              /* 0xE0600000 */
 259 #define CONFIG_SYS_NAND_WINDOW_SIZE     (32 * 1024)     /* 0x00008000 */
 260 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 261                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 262                                 | BR_PS_8               /* 8 bit Port */ \
 263                                 | BR_MS_FCM             /* MSEL = FCM */ \
 264                                 | BR_V)                 /* valid */
 265 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 266                                 | OR_FCM_CSCT \
 267                                 | OR_FCM_CST \
 268                                 | OR_FCM_CHT \
 269                                 | OR_FCM_SCY_1 \
 270                                 | OR_FCM_TRLX \
 271                                 | OR_FCM_EHTR)
 272                                 /* 0xFFFF8396 */
 273
 274 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 275 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 276
 277 #ifdef CONFIG_VSC7385_ENET
 278 #define CONFIG_TSEC2
 279                                         /* VSC7385 Base address on CS2 */
 280 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 281 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024) /* 0x00020000 */
 282 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 283                                         | BR_PS_8       /* 8-bit port */ \
 284                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 285                                         | BR_V)         /* valid */
 286                                         /* 0xF0000801 */
 287 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 288                                         | OR_GPCM_CSNT \
 289                                         | OR_GPCM_XACS \
 290                                         | OR_GPCM_SCY_15 \
 291                                         | OR_GPCM_SETA \
 292                                         | OR_GPCM_TRLX_SET \
 293                                         | OR_GPCM_EHTR_SET)
 294                                         /* 0xFFFE09FF */
 295 /* Access window base at VSC7385 base */
 296 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 297 /* Access window size 128K */
 298 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 299 /* The flash address and size of the VSC7385 firmware image */
 300 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 301 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 302 #endif
 303 /*
 304  * Serial Port
 305  */
 306 #define CONFIG_CONS_INDEX       1
 307 #define CONFIG_SYS_NS16550_SERIAL
 308 #define CONFIG_SYS_NS16550_REG_SIZE     1
 309 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 310
 311 #define CONFIG_SYS_BAUDRATE_TABLE  \
 312         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 313
 314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 316
 317 /* I2C */
 318 #define CONFIG_SYS_I2C
 319 #define CONFIG_SYS_I2C_FSL
 320 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 321 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 322 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 323 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 324 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 325 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 326 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 327
 328 /*
 329  * SPI on header J8
 330  *
 331  * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
 332  * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
 333  */
 334 #ifdef CONFIG_MPC8XXX_SPI
 335 #define CONFIG_USE_SPIFLASH
 336 #endif
 337
 338 /*
 339  * Board info - revision and where boot from
 340  */
 341 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 342
 343 /*
 344  * Config on-board RTC
 345  */
 346 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 347 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 348
 349 /*
 350  * General PCI
 351  * Addresses are mapped 1-1.
 352  */
 353 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 354 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 355 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 356 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 357 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 358 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 359 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 360 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 361 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 362
 363 /* enable PCIE clock */
 364 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 365
 366 #define CONFIG_PCI_INDIRECT_BRIDGE
 367 #define CONFIG_PCIE
 368
 369 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 370 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 371
 372 /*
 373  * TSEC
 374  */
 375 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 376 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 377 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 378 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 379 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 380
 381 /*
 382  * TSEC ethernet configuration
 383  */
 384 #define CONFIG_MII              1 /* MII PHY management */
 385 #define CONFIG_TSEC1_NAME       "eTSEC0"
 386 #define CONFIG_TSEC2_NAME       "eTSEC1"
 387 #define TSEC1_PHY_ADDR          2
 388 #define TSEC2_PHY_ADDR          1
 389 #define TSEC1_PHYIDX            0
 390 #define TSEC2_PHYIDX            0
 391 #define TSEC1_FLAGS             TSEC_GIGABIT
 392 #define TSEC2_FLAGS             TSEC_GIGABIT
 393
 394 /* Options are: eTSEC[0-1] */
 395 #define CONFIG_ETHPRIME         "eTSEC0"
 396
 397 /*
 398  * Environment
 399  */
 400 #define CONFIG_ENV_IS_IN_FLASH  1
 401 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 402                                  CONFIG_SYS_MONITOR_LEN)
 403 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 404 #define CONFIG_ENV_SIZE         0x2000
 405 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 406 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 407
 408 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 409 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 410
 411 /*
 412  * BOOTP options
 413  */
 414 #define CONFIG_BOOTP_BOOTFILESIZE
 415 #define CONFIG_BOOTP_BOOTPATH
 416 #define CONFIG_BOOTP_GATEWAY
 417 #define CONFIG_BOOTP_HOSTNAME
 418
 419 /*
 420  * Command line configuration.
 421  */
 422 #define CONFIG_CMD_DATE
 423 #define CONFIG_CMD_PCI
 424
 425 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 426
 427 /*
 428  * Miscellaneous configurable options
 429  */
 430 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 431 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 432
 433 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 434
 435 /* Print Buffer Size */
 436 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 437 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 438 /* Boot Argument Buffer Size */
 439 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 440
 441 /*
 442  * For booting Linux, the board info and command line data
 443  * have to be in the first 256 MB of memory, since this is
 444  * the maximum mapped by the Linux kernel during initialization.
 445  */
 446 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 447 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 448
 449 /*
 450  * Core HID Setup
 451  */
 452 #define CONFIG_SYS_HID0_INIT    0x000000000
 453 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 454                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 455                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 456 #define CONFIG_SYS_HID2         HID2_HBE
 457
 458 /*
 459  * MMU Setup
 460  */
 461
 462 /* DDR: cache cacheable */
 463 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 464                                         BATL_MEMCOHERENCE)
 465 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 466                                         BATU_VS | BATU_VP)
 467 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 468 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 469
 470 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 471 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 472                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 473 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 474                                         BATU_VP)
 475 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 476 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 477
 478 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 479 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 480                                         BATL_MEMCOHERENCE)
 481 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 482                                         BATU_VS | BATU_VP)
 483 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 484                                         BATL_CACHEINHIBIT | \
 485                                         BATL_GUARDEDSTORAGE)
 486 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 487
 488 /* Stack in dcache: cacheable, no memory coherence */
 489 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 490 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 491                                         BATU_VS | BATU_VP)
 492 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 493 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 494
 495 /*
 496  * Environment Configuration
 497  */
 498
 499 #define CONFIG_ENV_OVERWRITE
 500
 501 #if defined(CONFIG_TSEC_ENET)
 502 #define CONFIG_HAS_ETH0
 503 #define CONFIG_HAS_ETH1
 504 #endif
 505
 506 #define CONFIG_BAUDRATE 115200
 507
 508 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 509
 510
 511 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 512         "netdev=eth0\0"                                                 \
 513         "consoledev=ttyS0\0"                                            \
 514         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 515                 "nfsroot=${serverip}:${rootpath}\0"                     \
 516         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 517         "addip=setenv bootargs ${bootargs} "                            \
 518                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 519                 ":${hostname}:${netdev}:off panic=1\0"                  \
 520         "addtty=setenv bootargs ${bootargs}"                            \
 521                 " console=${consoledev},${baudrate}\0"                  \
 522         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 523         "addmisc=setenv bootargs ${bootargs}\0"                         \
 524         "kernel_addr=FE080000\0"                                        \
 525         "fdt_addr=FE280000\0"                                           \
 526         "ramdisk_addr=FE290000\0"                                       \
 527         "u-boot=mpc8308rdb/u-boot.bin\0"                                \
 528         "kernel_addr_r=1000000\0"                                       \
 529         "fdt_addr_r=C00000\0"                                           \
 530         "hostname=mpc8308rdb\0"                                         \
 531         "bootfile=mpc8308rdb/uImage\0"                                  \
 532         "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"                           \
 533         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 534         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 535                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 536         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 537                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 538         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 539                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 540                 "run nfsargs addip addtty addmtd addmisc;"              \
 541                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 542         "bootcmd=run flash_self\0"                                      \
 543         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 544         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 545                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 546                 " +${filesize};cp.b ${fileaddr} "                       \
 547                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 548         "upd=run load update\0"                                         \
 549
 550 #endif  /* __CONFIG_H */