1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
17 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
18 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
28 #define CONFIG_VSC7385_ENET
33 #define CONFIG_SYS_SICRH (\
38 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
39 SICRH_IEEE1588_A_GPIO |\
42 SICRH_IEEE1588_B_GPIO |\
47 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
48 #define CONFIG_SYS_SICRL (\
53 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
58 #define CONFIG_SYS_IMMR 0xE0000000
63 #define CONFIG_FSL_SERDES
64 #define CONFIG_FSL_SERDES1 0xe3000
69 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
70 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
71 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
76 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
78 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
79 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
80 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
87 * Manually set up DDR parameters
88 * consist of two chips HY5PS12621BFP-C4 from HYNIX
91 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
93 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
94 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
95 | CSCONFIG_ODT_RD_NEVER \
96 | CSCONFIG_ODT_WR_ONLY_CURRENT \
97 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
99 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
100 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
101 | (0 << TIMING_CFG0_WRT_SHIFT) \
102 | (0 << TIMING_CFG0_RRT_SHIFT) \
103 | (0 << TIMING_CFG0_WWT_SHIFT) \
104 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
105 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
106 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
107 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
109 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
110 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
111 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
112 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
113 | (6 << TIMING_CFG1_REFREC_SHIFT) \
114 | (2 << TIMING_CFG1_WRREC_SHIFT) \
115 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
116 | (2 << TIMING_CFG1_WRTORD_SHIFT))
118 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
119 | (4 << TIMING_CFG2_CPO_SHIFT) \
120 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
121 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
122 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
123 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
124 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
126 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
127 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
129 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
130 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
134 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
135 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
136 | (0x0232 << SDRAM_MODE_SD_SHIFT))
137 /* ODT 150ohm CL=3, AL=1 on SDRAM */
138 #define CONFIG_SYS_DDR_MODE2 0x00000000
143 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
144 #define CONFIG_SYS_MEMTEST_END 0x07f00000
147 * The reserved memory
149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
151 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
152 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
155 * Initial RAM Base Address Setup
157 #define CONFIG_SYS_INIT_RAM_LOCK 1
158 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
159 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
160 #define CONFIG_SYS_GBL_DATA_OFFSET \
161 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
164 * Local Bus Configuration & Clock Setup
166 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
167 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
168 #define CONFIG_SYS_LBC_LBCR 0x00040000
171 * FLASH on the Local Bus
173 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
175 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
176 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
178 /* Window base at flash base */
179 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
180 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
182 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
183 | BR_PS_16 /* 16 bit port */ \
184 | BR_MS_GPCM /* MSEL = GPCM */ \
186 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
195 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
196 /* 127 64KB sectors and 8 8KB top sectors per device */
197 #define CONFIG_SYS_MAX_FLASH_SECT 135
199 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
200 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
203 * NAND Flash on the Local Bus
205 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
206 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
207 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
208 | BR_DECC_CHK_GEN /* Use HW ECC */ \
209 | BR_PS_8 /* 8 bit Port */ \
210 | BR_MS_FCM /* MSEL = FCM */ \
212 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
221 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
222 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
224 #ifdef CONFIG_VSC7385_ENET
226 /* VSC7385 Base address on CS2 */
227 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
228 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
229 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
230 | BR_PS_8 /* 8-bit port */ \
231 | BR_MS_GPCM /* MSEL = GPCM */ \
234 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
242 /* Access window base at VSC7385 base */
243 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
244 /* Access window size 128K */
245 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
246 /* The flash address and size of the VSC7385 firmware image */
247 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
248 #define CONFIG_VSC7385_IMAGE_SIZE 8192
253 #define CONFIG_SYS_NS16550_SERIAL
254 #define CONFIG_SYS_NS16550_REG_SIZE 1
255 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
257 #define CONFIG_SYS_BAUDRATE_TABLE \
258 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
260 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
261 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
264 #define CONFIG_SYS_I2C
265 #define CONFIG_SYS_I2C_FSL
266 #define CONFIG_SYS_FSL_I2C_SPEED 400000
267 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
268 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
269 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
270 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
271 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
272 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
277 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
278 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
280 #ifdef CONFIG_MPC8XXX_SPI
281 #define CONFIG_USE_SPIFLASH
285 * Board info - revision and where boot from
287 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
290 * Config on-board RTC
292 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
293 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
297 * Addresses are mapped 1-1.
299 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
300 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
301 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
302 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
303 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
304 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
305 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
306 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
307 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
309 /* enable PCIE clock */
310 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
312 #define CONFIG_PCI_INDIRECT_BRIDGE
315 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
316 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
321 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
322 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
323 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
324 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
327 * TSEC ethernet configuration
329 #define CONFIG_TSEC1_NAME "eTSEC0"
330 #define CONFIG_TSEC2_NAME "eTSEC1"
331 #define TSEC1_PHY_ADDR 2
332 #define TSEC2_PHY_ADDR 1
333 #define TSEC1_PHYIDX 0
334 #define TSEC2_PHYIDX 0
335 #define TSEC1_FLAGS TSEC_GIGABIT
336 #define TSEC2_FLAGS TSEC_GIGABIT
338 /* Options are: eTSEC[0-1] */
339 #define CONFIG_ETHPRIME "eTSEC0"
344 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
345 CONFIG_SYS_MONITOR_LEN)
346 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
347 #define CONFIG_ENV_SIZE 0x2000
348 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
349 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
351 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
352 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
357 #define CONFIG_BOOTP_BOOTFILESIZE
360 * Command line configuration.
364 * Miscellaneous configurable options
366 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
368 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
370 /* Boot Argument Buffer Size */
371 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
374 * For booting Linux, the board info and command line data
375 * have to be in the first 256 MB of memory, since this is
376 * the maximum mapped by the Linux kernel during initialization.
378 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
379 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
384 #define CONFIG_SYS_HID0_INIT 0x000000000
385 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
386 HID0_ENABLE_INSTRUCTION_CACHE | \
387 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
388 #define CONFIG_SYS_HID2 HID2_HBE
391 * Environment Configuration
394 #define CONFIG_ENV_OVERWRITE
396 #if defined(CONFIG_TSEC_ENET)
397 #define CONFIG_HAS_ETH0
398 #define CONFIG_HAS_ETH1
401 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
404 #define CONFIG_EXTRA_ENV_SETTINGS \
406 "consoledev=ttyS0\0" \
407 "nfsargs=setenv bootargs root=/dev/nfs rw " \
408 "nfsroot=${serverip}:${rootpath}\0" \
409 "ramargs=setenv bootargs root=/dev/ram rw\0" \
410 "addip=setenv bootargs ${bootargs} " \
411 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
412 ":${hostname}:${netdev}:off panic=1\0" \
413 "addtty=setenv bootargs ${bootargs}" \
414 " console=${consoledev},${baudrate}\0" \
415 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
416 "addmisc=setenv bootargs ${bootargs}\0" \
417 "kernel_addr=FE080000\0" \
418 "fdt_addr=FE280000\0" \
419 "ramdisk_addr=FE290000\0" \
420 "u-boot=mpc8308rdb/u-boot.bin\0" \
421 "kernel_addr_r=1000000\0" \
422 "fdt_addr_r=C00000\0" \
423 "hostname=mpc8308rdb\0" \
424 "bootfile=mpc8308rdb/uImage\0" \
425 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
426 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
427 "flash_self=run ramargs addip addtty addmtd addmisc;" \
428 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
429 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
430 "bootm ${kernel_addr} - ${fdt_addr}\0" \
431 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
432 "tftp ${fdt_addr_r} ${fdtfile};" \
433 "run nfsargs addip addtty addmtd addmisc;" \
434 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
435 "bootcmd=run flash_self\0" \
436 "load=tftp ${loadaddr} ${u-boot}\0" \
437 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
438 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
439 " +${filesize};cp.b ${fileaddr} " \
440 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
441 "upd=run load update\0" \
443 #endif /* __CONFIG_H */